Root/arch/arm/mach-s3c2412/s3c2412.c

1/* linux/arch/arm/mach-s3c2412/s3c2412.c
2 *
3 * Copyright (c) 2006 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * http://armlinux.simtec.co.uk/.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/kernel.h>
14#include <linux/types.h>
15#include <linux/interrupt.h>
16#include <linux/list.h>
17#include <linux/timer.h>
18#include <linux/init.h>
19#include <linux/clk.h>
20#include <linux/delay.h>
21#include <linux/sysdev.h>
22#include <linux/serial_core.h>
23#include <linux/platform_device.h>
24#include <linux/io.h>
25
26#include <asm/mach/arch.h>
27#include <asm/mach/map.h>
28#include <asm/mach/irq.h>
29
30#include <mach/hardware.h>
31#include <asm/proc-fns.h>
32#include <asm/irq.h>
33
34#include <mach/reset.h>
35#include <mach/idle.h>
36
37#include <plat/cpu-freq.h>
38
39#include <mach/regs-clock.h>
40#include <plat/regs-serial.h>
41#include <mach/regs-power.h>
42#include <mach/regs-gpio.h>
43#include <mach/regs-gpioj.h>
44#include <mach/regs-dsc.h>
45#include <plat/regs-spi.h>
46#include <mach/regs-s3c2412.h>
47
48#include <plat/s3c2412.h>
49#include <plat/cpu.h>
50#include <plat/devs.h>
51#include <plat/clock.h>
52#include <plat/pm.h>
53#include <plat/pll.h>
54#include <plat/nand-core.h>
55
56#ifndef CONFIG_CPU_S3C2412_ONLY
57void __iomem *s3c24xx_va_gpio2 = S3C24XX_VA_GPIO;
58
59static inline void s3c2412_init_gpio2(void)
60{
61    s3c24xx_va_gpio2 = S3C24XX_VA_GPIO + 0x10;
62}
63#else
64#define s3c2412_init_gpio2() do { } while(0)
65#endif
66
67/* Initial IO mappings */
68
69static struct map_desc s3c2412_iodesc[] __initdata = {
70    IODESC_ENT(CLKPWR),
71    IODESC_ENT(TIMER),
72    IODESC_ENT(WATCHDOG),
73    {
74        .virtual = (unsigned long)S3C2412_VA_SSMC,
75        .pfn = __phys_to_pfn(S3C2412_PA_SSMC),
76        .length = SZ_1M,
77        .type = MT_DEVICE,
78    },
79    {
80        .virtual = (unsigned long)S3C2412_VA_EBI,
81        .pfn = __phys_to_pfn(S3C2412_PA_EBI),
82        .length = SZ_1M,
83        .type = MT_DEVICE,
84    },
85};
86
87/* uart registration process */
88
89void __init s3c2412_init_uarts(struct s3c2410_uartcfg *cfg, int no)
90{
91    s3c24xx_init_uartdevs("s3c2412-uart", s3c2410_uart_resources, cfg, no);
92
93    /* rename devices that are s3c2412/s3c2413 specific */
94    s3c_device_sdi.name = "s3c2412-sdi";
95    s3c_device_lcd.name = "s3c2412-lcd";
96    s3c_nand_setname("s3c2412-nand");
97
98    /* alter IRQ of SDI controller */
99
100    s3c_device_sdi.resource[1].start = IRQ_S3C2412_SDI;
101    s3c_device_sdi.resource[1].end = IRQ_S3C2412_SDI;
102
103    /* spi channel related changes, s3c2412/13 specific */
104    s3c_device_spi0.name = "s3c2412-spi";
105    s3c_device_spi0.resource[0].end = S3C24XX_PA_SPI + 0x24;
106    s3c_device_spi1.name = "s3c2412-spi";
107    s3c_device_spi1.resource[0].start = S3C24XX_PA_SPI + S3C2412_SPI1;
108    s3c_device_spi1.resource[0].end = S3C24XX_PA_SPI + S3C2412_SPI1 + 0x24;
109
110}
111
112/* s3c2412_idle
113 *
114 * use the standard idle call by ensuring the idle mode
115 * in power config, then issuing the idle co-processor
116 * instruction
117*/
118
119static void s3c2412_idle(void)
120{
121    unsigned long tmp;
122
123    /* ensure our idle mode is to go to idle */
124
125    tmp = __raw_readl(S3C2412_PWRCFG);
126    tmp &= ~S3C2412_PWRCFG_STANDBYWFI_MASK;
127    tmp |= S3C2412_PWRCFG_STANDBYWFI_IDLE;
128    __raw_writel(tmp, S3C2412_PWRCFG);
129
130    cpu_do_idle();
131}
132
133static void s3c2412_hard_reset(void)
134{
135    /* errata "Watch-dog/Software Reset Problem" specifies that
136     * this reset must be done with the SYSCLK sourced from
137     * EXTCLK instead of FOUT to avoid a glitch in the reset
138     * mechanism.
139     *
140     * See the watchdog section of the S3C2412 manual for more
141     * information on this fix.
142     */
143
144    __raw_writel(0x00, S3C2412_CLKSRC);
145    __raw_writel(S3C2412_SWRST_RESET, S3C2412_SWRST);
146
147    mdelay(1);
148}
149
150/* s3c2412_map_io
151 *
152 * register the standard cpu IO areas, and any passed in from the
153 * machine specific initialisation.
154*/
155
156void __init s3c2412_map_io(void)
157{
158    /* move base of IO */
159
160    s3c2412_init_gpio2();
161
162    /* set our idle function */
163
164    s3c24xx_idle = s3c2412_idle;
165
166    /* set custom reset hook */
167
168    s3c24xx_reset_hook = s3c2412_hard_reset;
169
170    /* register our io-tables */
171
172    iotable_init(s3c2412_iodesc, ARRAY_SIZE(s3c2412_iodesc));
173}
174
175void __init_or_cpufreq s3c2412_setup_clocks(void)
176{
177    struct clk *xtal_clk;
178    unsigned long tmp;
179    unsigned long xtal;
180    unsigned long fclk;
181    unsigned long hclk;
182    unsigned long pclk;
183
184    xtal_clk = clk_get(NULL, "xtal");
185    xtal = clk_get_rate(xtal_clk);
186    clk_put(xtal_clk);
187
188    /* now we've got our machine bits initialised, work out what
189     * clocks we've got */
190
191    fclk = s3c24xx_get_pll(__raw_readl(S3C2410_MPLLCON), xtal * 2);
192
193    clk_mpll.rate = fclk;
194
195    tmp = __raw_readl(S3C2410_CLKDIVN);
196
197    /* work out clock scalings */
198
199    hclk = fclk / ((tmp & S3C2412_CLKDIVN_HDIVN_MASK) + 1);
200    hclk /= ((tmp & S3C2412_CLKDIVN_ARMDIVN) ? 2 : 1);
201    pclk = hclk / ((tmp & S3C2412_CLKDIVN_PDIVN) ? 2 : 1);
202
203    /* print brieft summary of clocks, etc */
204
205    printk("S3C2412: core %ld.%03ld MHz, memory %ld.%03ld MHz, peripheral %ld.%03ld MHz\n",
206           print_mhz(fclk), print_mhz(hclk), print_mhz(pclk));
207
208    s3c24xx_setup_clocks(fclk, hclk, pclk);
209}
210
211void __init s3c2412_init_clocks(int xtal)
212{
213    /* initialise the clocks here, to allow other things like the
214     * console to use them
215     */
216
217    s3c24xx_register_baseclocks(xtal);
218    s3c2412_setup_clocks();
219    s3c2412_baseclk_add();
220}
221
222/* need to register class before we actually register the device, and
223 * we also need to ensure that it has been initialised before any of the
224 * drivers even try to use it (even if not on an s3c2412 based system)
225 * as a driver which may support both 2410 and 2440 may try and use it.
226*/
227
228struct sysdev_class s3c2412_sysclass = {
229    .name = "s3c2412-core",
230};
231
232static int __init s3c2412_core_init(void)
233{
234    return sysdev_class_register(&s3c2412_sysclass);
235}
236
237core_initcall(s3c2412_core_init);
238
239static struct sys_device s3c2412_sysdev = {
240    .cls = &s3c2412_sysclass,
241};
242
243int __init s3c2412_init(void)
244{
245    printk("S3C2412: Initialising architecture\n");
246
247    return sysdev_register(&s3c2412_sysdev);
248}
249

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