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1 | /* linux/arch/arm/mach-s5pv210/cpufreq.c |
2 | * |
3 | * Copyright (c) 2010 Samsung Electronics Co., Ltd. |
4 | * http://www.samsung.com |
5 | * |
6 | * CPU frequency scaling for S5PC110/S5PV210 |
7 | * |
8 | * This program is free software; you can redistribute it and/or modify |
9 | * it under the terms of the GNU General Public License version 2 as |
10 | * published by the Free Software Foundation. |
11 | */ |
12 | |
13 | #include <linux/types.h> |
14 | #include <linux/kernel.h> |
15 | #include <linux/init.h> |
16 | #include <linux/err.h> |
17 | #include <linux/clk.h> |
18 | #include <linux/io.h> |
19 | #include <linux/cpufreq.h> |
20 | |
21 | #include <mach/map.h> |
22 | #include <mach/regs-clock.h> |
23 | |
24 | static struct clk *cpu_clk; |
25 | static struct clk *dmc0_clk; |
26 | static struct clk *dmc1_clk; |
27 | static struct cpufreq_freqs freqs; |
28 | |
29 | /* APLL M,P,S values for 1G/800Mhz */ |
30 | #define APLL_VAL_1000 ((1 << 31) | (125 << 16) | (3 << 8) | 1) |
31 | #define APLL_VAL_800 ((1 << 31) | (100 << 16) | (3 << 8) | 1) |
32 | |
33 | /* |
34 | * DRAM configurations to calculate refresh counter for changing |
35 | * frequency of memory. |
36 | */ |
37 | struct dram_conf { |
38 | unsigned long freq; /* HZ */ |
39 | unsigned long refresh; /* DRAM refresh counter * 1000 */ |
40 | }; |
41 | |
42 | /* DRAM configuration (DMC0 and DMC1) */ |
43 | static struct dram_conf s5pv210_dram_conf[2]; |
44 | |
45 | enum perf_level { |
46 | L0, L1, L2, L3, L4, |
47 | }; |
48 | |
49 | enum s5pv210_mem_type { |
50 | LPDDR = 0x1, |
51 | LPDDR2 = 0x2, |
52 | DDR2 = 0x4, |
53 | }; |
54 | |
55 | enum s5pv210_dmc_port { |
56 | DMC0 = 0, |
57 | DMC1, |
58 | }; |
59 | |
60 | static struct cpufreq_frequency_table s5pv210_freq_table[] = { |
61 | {L0, 1000*1000}, |
62 | {L1, 800*1000}, |
63 | {L2, 400*1000}, |
64 | {L3, 200*1000}, |
65 | {L4, 100*1000}, |
66 | {0, CPUFREQ_TABLE_END}, |
67 | }; |
68 | |
69 | static u32 clkdiv_val[5][11] = { |
70 | /* |
71 | * Clock divider value for following |
72 | * { APLL, A2M, HCLK_MSYS, PCLK_MSYS, |
73 | * HCLK_DSYS, PCLK_DSYS, HCLK_PSYS, PCLK_PSYS, |
74 | * ONEDRAM, MFC, G3D } |
75 | */ |
76 | |
77 | /* L0 : [1000/200/100][166/83][133/66][200/200] */ |
78 | {0, 4, 4, 1, 3, 1, 4, 1, 3, 0, 0}, |
79 | |
80 | /* L1 : [800/200/100][166/83][133/66][200/200] */ |
81 | {0, 3, 3, 1, 3, 1, 4, 1, 3, 0, 0}, |
82 | |
83 | /* L2 : [400/200/100][166/83][133/66][200/200] */ |
84 | {1, 3, 1, 1, 3, 1, 4, 1, 3, 0, 0}, |
85 | |
86 | /* L3 : [200/200/100][166/83][133/66][200/200] */ |
87 | {3, 3, 1, 1, 3, 1, 4, 1, 3, 0, 0}, |
88 | |
89 | /* L4 : [100/100/100][83/83][66/66][100/100] */ |
90 | {7, 7, 0, 0, 7, 0, 9, 0, 7, 0, 0}, |
91 | }; |
92 | |
93 | /* |
94 | * This function set DRAM refresh counter |
95 | * accoriding to operating frequency of DRAM |
96 | * ch: DMC port number 0 or 1 |
97 | * freq: Operating frequency of DRAM(KHz) |
98 | */ |
99 | static void s5pv210_set_refresh(enum s5pv210_dmc_port ch, unsigned long freq) |
100 | { |
101 | unsigned long tmp, tmp1; |
102 | void __iomem *reg = NULL; |
103 | |
104 | if (ch == DMC0) |
105 | reg = (S5P_VA_DMC0 + 0x30); |
106 | else if (ch == DMC1) |
107 | reg = (S5P_VA_DMC1 + 0x30); |
108 | else |
109 | printk(KERN_ERR "Cannot find DMC port\n"); |
110 | |
111 | /* Find current DRAM frequency */ |
112 | tmp = s5pv210_dram_conf[ch].freq; |
113 | |
114 | do_div(tmp, freq); |
115 | |
116 | tmp1 = s5pv210_dram_conf[ch].refresh; |
117 | |
118 | do_div(tmp1, tmp); |
119 | |
120 | __raw_writel(tmp1, reg); |
121 | } |
122 | |
123 | int s5pv210_verify_speed(struct cpufreq_policy *policy) |
124 | { |
125 | if (policy->cpu) |
126 | return -EINVAL; |
127 | |
128 | return cpufreq_frequency_table_verify(policy, s5pv210_freq_table); |
129 | } |
130 | |
131 | unsigned int s5pv210_getspeed(unsigned int cpu) |
132 | { |
133 | if (cpu) |
134 | return 0; |
135 | |
136 | return clk_get_rate(cpu_clk) / 1000; |
137 | } |
138 | |
139 | static int s5pv210_target(struct cpufreq_policy *policy, |
140 | unsigned int target_freq, |
141 | unsigned int relation) |
142 | { |
143 | unsigned long reg; |
144 | unsigned int index, priv_index; |
145 | unsigned int pll_changing = 0; |
146 | unsigned int bus_speed_changing = 0; |
147 | |
148 | freqs.old = s5pv210_getspeed(0); |
149 | |
150 | if (cpufreq_frequency_table_target(policy, s5pv210_freq_table, |
151 | target_freq, relation, &index)) |
152 | return -EINVAL; |
153 | |
154 | freqs.new = s5pv210_freq_table[index].frequency; |
155 | freqs.cpu = 0; |
156 | |
157 | if (freqs.new == freqs.old) |
158 | return 0; |
159 | |
160 | /* Finding current running level index */ |
161 | if (cpufreq_frequency_table_target(policy, s5pv210_freq_table, |
162 | freqs.old, relation, &priv_index)) |
163 | return -EINVAL; |
164 | |
165 | cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE); |
166 | |
167 | if (freqs.new > freqs.old) { |
168 | /* Voltage up: will be implemented */ |
169 | } |
170 | |
171 | /* Check if there need to change PLL */ |
172 | if ((index == L0) || (priv_index == L0)) |
173 | pll_changing = 1; |
174 | |
175 | /* Check if there need to change System bus clock */ |
176 | if ((index == L4) || (priv_index == L4)) |
177 | bus_speed_changing = 1; |
178 | |
179 | if (bus_speed_changing) { |
180 | /* |
181 | * Reconfigure DRAM refresh counter value for minimum |
182 | * temporary clock while changing divider. |
183 | * expected clock is 83Mhz : 7.8usec/(1/83Mhz) = 0x287 |
184 | */ |
185 | if (pll_changing) |
186 | s5pv210_set_refresh(DMC1, 83000); |
187 | else |
188 | s5pv210_set_refresh(DMC1, 100000); |
189 | |
190 | s5pv210_set_refresh(DMC0, 83000); |
191 | } |
192 | |
193 | /* |
194 | * APLL should be changed in this level |
195 | * APLL -> MPLL(for stable transition) -> APLL |
196 | * Some clock source's clock API are not prepared. |
197 | * Do not use clock API in below code. |
198 | */ |
199 | if (pll_changing) { |
200 | /* |
201 | * 1. Temporary Change divider for MFC and G3D |
202 | * SCLKA2M(200/1=200)->(200/4=50)Mhz |
203 | */ |
204 | reg = __raw_readl(S5P_CLK_DIV2); |
205 | reg &= ~(S5P_CLKDIV2_G3D_MASK | S5P_CLKDIV2_MFC_MASK); |
206 | reg |= (3 << S5P_CLKDIV2_G3D_SHIFT) | |
207 | (3 << S5P_CLKDIV2_MFC_SHIFT); |
208 | __raw_writel(reg, S5P_CLK_DIV2); |
209 | |
210 | /* For MFC, G3D dividing */ |
211 | do { |
212 | reg = __raw_readl(S5P_CLKDIV_STAT0); |
213 | } while (reg & ((1 << 16) | (1 << 17))); |
214 | |
215 | /* |
216 | * 2. Change SCLKA2M(200Mhz)to SCLKMPLL in MFC_MUX, G3D MUX |
217 | * (200/4=50)->(667/4=166)Mhz |
218 | */ |
219 | reg = __raw_readl(S5P_CLK_SRC2); |
220 | reg &= ~(S5P_CLKSRC2_G3D_MASK | S5P_CLKSRC2_MFC_MASK); |
221 | reg |= (1 << S5P_CLKSRC2_G3D_SHIFT) | |
222 | (1 << S5P_CLKSRC2_MFC_SHIFT); |
223 | __raw_writel(reg, S5P_CLK_SRC2); |
224 | |
225 | do { |
226 | reg = __raw_readl(S5P_CLKMUX_STAT1); |
227 | } while (reg & ((1 << 7) | (1 << 3))); |
228 | |
229 | /* |
230 | * 3. DMC1 refresh count for 133Mhz if (index == L4) is |
231 | * true refresh counter is already programed in upper |
232 | * code. 0x287@83Mhz |
233 | */ |
234 | if (!bus_speed_changing) |
235 | s5pv210_set_refresh(DMC1, 133000); |
236 | |
237 | /* 4. SCLKAPLL -> SCLKMPLL */ |
238 | reg = __raw_readl(S5P_CLK_SRC0); |
239 | reg &= ~(S5P_CLKSRC0_MUX200_MASK); |
240 | reg |= (0x1 << S5P_CLKSRC0_MUX200_SHIFT); |
241 | __raw_writel(reg, S5P_CLK_SRC0); |
242 | |
243 | do { |
244 | reg = __raw_readl(S5P_CLKMUX_STAT0); |
245 | } while (reg & (0x1 << 18)); |
246 | |
247 | } |
248 | |
249 | /* Change divider */ |
250 | reg = __raw_readl(S5P_CLK_DIV0); |
251 | |
252 | reg &= ~(S5P_CLKDIV0_APLL_MASK | S5P_CLKDIV0_A2M_MASK | |
253 | S5P_CLKDIV0_HCLK200_MASK | S5P_CLKDIV0_PCLK100_MASK | |
254 | S5P_CLKDIV0_HCLK166_MASK | S5P_CLKDIV0_PCLK83_MASK | |
255 | S5P_CLKDIV0_HCLK133_MASK | S5P_CLKDIV0_PCLK66_MASK); |
256 | |
257 | reg |= ((clkdiv_val[index][0] << S5P_CLKDIV0_APLL_SHIFT) | |
258 | (clkdiv_val[index][1] << S5P_CLKDIV0_A2M_SHIFT) | |
259 | (clkdiv_val[index][2] << S5P_CLKDIV0_HCLK200_SHIFT) | |
260 | (clkdiv_val[index][3] << S5P_CLKDIV0_PCLK100_SHIFT) | |
261 | (clkdiv_val[index][4] << S5P_CLKDIV0_HCLK166_SHIFT) | |
262 | (clkdiv_val[index][5] << S5P_CLKDIV0_PCLK83_SHIFT) | |
263 | (clkdiv_val[index][6] << S5P_CLKDIV0_HCLK133_SHIFT) | |
264 | (clkdiv_val[index][7] << S5P_CLKDIV0_PCLK66_SHIFT)); |
265 | |
266 | __raw_writel(reg, S5P_CLK_DIV0); |
267 | |
268 | do { |
269 | reg = __raw_readl(S5P_CLKDIV_STAT0); |
270 | } while (reg & 0xff); |
271 | |
272 | /* ARM MCS value changed */ |
273 | reg = __raw_readl(S5P_ARM_MCS_CON); |
274 | reg &= ~0x3; |
275 | if (index >= L3) |
276 | reg |= 0x3; |
277 | else |
278 | reg |= 0x1; |
279 | |
280 | __raw_writel(reg, S5P_ARM_MCS_CON); |
281 | |
282 | if (pll_changing) { |
283 | /* 5. Set Lock time = 30us*24Mhz = 0x2cf */ |
284 | __raw_writel(0x2cf, S5P_APLL_LOCK); |
285 | |
286 | /* |
287 | * 6. Turn on APLL |
288 | * 6-1. Set PMS values |
289 | * 6-2. Wait untile the PLL is locked |
290 | */ |
291 | if (index == L0) |
292 | __raw_writel(APLL_VAL_1000, S5P_APLL_CON); |
293 | else |
294 | __raw_writel(APLL_VAL_800, S5P_APLL_CON); |
295 | |
296 | do { |
297 | reg = __raw_readl(S5P_APLL_CON); |
298 | } while (!(reg & (0x1 << 29))); |
299 | |
300 | /* |
301 | * 7. Change souce clock from SCLKMPLL(667Mhz) |
302 | * to SCLKA2M(200Mhz) in MFC_MUX and G3D MUX |
303 | * (667/4=166)->(200/4=50)Mhz |
304 | */ |
305 | reg = __raw_readl(S5P_CLK_SRC2); |
306 | reg &= ~(S5P_CLKSRC2_G3D_MASK | S5P_CLKSRC2_MFC_MASK); |
307 | reg |= (0 << S5P_CLKSRC2_G3D_SHIFT) | |
308 | (0 << S5P_CLKSRC2_MFC_SHIFT); |
309 | __raw_writel(reg, S5P_CLK_SRC2); |
310 | |
311 | do { |
312 | reg = __raw_readl(S5P_CLKMUX_STAT1); |
313 | } while (reg & ((1 << 7) | (1 << 3))); |
314 | |
315 | /* |
316 | * 8. Change divider for MFC and G3D |
317 | * (200/4=50)->(200/1=200)Mhz |
318 | */ |
319 | reg = __raw_readl(S5P_CLK_DIV2); |
320 | reg &= ~(S5P_CLKDIV2_G3D_MASK | S5P_CLKDIV2_MFC_MASK); |
321 | reg |= (clkdiv_val[index][10] << S5P_CLKDIV2_G3D_SHIFT) | |
322 | (clkdiv_val[index][9] << S5P_CLKDIV2_MFC_SHIFT); |
323 | __raw_writel(reg, S5P_CLK_DIV2); |
324 | |
325 | /* For MFC, G3D dividing */ |
326 | do { |
327 | reg = __raw_readl(S5P_CLKDIV_STAT0); |
328 | } while (reg & ((1 << 16) | (1 << 17))); |
329 | |
330 | /* 9. Change MPLL to APLL in MSYS_MUX */ |
331 | reg = __raw_readl(S5P_CLK_SRC0); |
332 | reg &= ~(S5P_CLKSRC0_MUX200_MASK); |
333 | reg |= (0x0 << S5P_CLKSRC0_MUX200_SHIFT); |
334 | __raw_writel(reg, S5P_CLK_SRC0); |
335 | |
336 | do { |
337 | reg = __raw_readl(S5P_CLKMUX_STAT0); |
338 | } while (reg & (0x1 << 18)); |
339 | |
340 | /* |
341 | * 10. DMC1 refresh counter |
342 | * L4 : DMC1 = 100Mhz 7.8us/(1/100) = 0x30c |
343 | * Others : DMC1 = 200Mhz 7.8us/(1/200) = 0x618 |
344 | */ |
345 | if (!bus_speed_changing) |
346 | s5pv210_set_refresh(DMC1, 200000); |
347 | } |
348 | |
349 | /* |
350 | * L4 level need to change memory bus speed, hence onedram clock divier |
351 | * and memory refresh parameter should be changed |
352 | */ |
353 | if (bus_speed_changing) { |
354 | reg = __raw_readl(S5P_CLK_DIV6); |
355 | reg &= ~S5P_CLKDIV6_ONEDRAM_MASK; |
356 | reg |= (clkdiv_val[index][8] << S5P_CLKDIV6_ONEDRAM_SHIFT); |
357 | __raw_writel(reg, S5P_CLK_DIV6); |
358 | |
359 | do { |
360 | reg = __raw_readl(S5P_CLKDIV_STAT1); |
361 | } while (reg & (1 << 15)); |
362 | |
363 | /* Reconfigure DRAM refresh counter value */ |
364 | if (index != L4) { |
365 | /* |
366 | * DMC0 : 166Mhz |
367 | * DMC1 : 200Mhz |
368 | */ |
369 | s5pv210_set_refresh(DMC0, 166000); |
370 | s5pv210_set_refresh(DMC1, 200000); |
371 | } else { |
372 | /* |
373 | * DMC0 : 83Mhz |
374 | * DMC1 : 100Mhz |
375 | */ |
376 | s5pv210_set_refresh(DMC0, 83000); |
377 | s5pv210_set_refresh(DMC1, 100000); |
378 | } |
379 | } |
380 | |
381 | if (freqs.new < freqs.old) { |
382 | /* Voltage down: will be implemented */ |
383 | } |
384 | |
385 | cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE); |
386 | |
387 | printk(KERN_DEBUG "Perf changed[L%d]\n", index); |
388 | |
389 | return 0; |
390 | } |
391 | |
392 | #ifdef CONFIG_PM |
393 | static int s5pv210_cpufreq_suspend(struct cpufreq_policy *policy, |
394 | pm_message_t pmsg) |
395 | { |
396 | return 0; |
397 | } |
398 | |
399 | static int s5pv210_cpufreq_resume(struct cpufreq_policy *policy) |
400 | { |
401 | return 0; |
402 | } |
403 | #endif |
404 | |
405 | static int check_mem_type(void __iomem *dmc_reg) |
406 | { |
407 | unsigned long val; |
408 | |
409 | val = __raw_readl(dmc_reg + 0x4); |
410 | val = (val & (0xf << 8)); |
411 | |
412 | return val >> 8; |
413 | } |
414 | |
415 | static int __init s5pv210_cpu_init(struct cpufreq_policy *policy) |
416 | { |
417 | unsigned long mem_type; |
418 | |
419 | cpu_clk = clk_get(NULL, "armclk"); |
420 | if (IS_ERR(cpu_clk)) |
421 | return PTR_ERR(cpu_clk); |
422 | |
423 | dmc0_clk = clk_get(NULL, "sclk_dmc0"); |
424 | if (IS_ERR(dmc0_clk)) { |
425 | clk_put(cpu_clk); |
426 | return PTR_ERR(dmc0_clk); |
427 | } |
428 | |
429 | dmc1_clk = clk_get(NULL, "hclk_msys"); |
430 | if (IS_ERR(dmc1_clk)) { |
431 | clk_put(dmc0_clk); |
432 | clk_put(cpu_clk); |
433 | return PTR_ERR(dmc1_clk); |
434 | } |
435 | |
436 | if (policy->cpu != 0) |
437 | return -EINVAL; |
438 | |
439 | /* |
440 | * check_mem_type : This driver only support LPDDR & LPDDR2. |
441 | * other memory type is not supported. |
442 | */ |
443 | mem_type = check_mem_type(S5P_VA_DMC0); |
444 | |
445 | if ((mem_type != LPDDR) && (mem_type != LPDDR2)) { |
446 | printk(KERN_ERR "CPUFreq doesn't support this memory type\n"); |
447 | return -EINVAL; |
448 | } |
449 | |
450 | /* Find current refresh counter and frequency each DMC */ |
451 | s5pv210_dram_conf[0].refresh = (__raw_readl(S5P_VA_DMC0 + 0x30) * 1000); |
452 | s5pv210_dram_conf[0].freq = clk_get_rate(dmc0_clk); |
453 | |
454 | s5pv210_dram_conf[1].refresh = (__raw_readl(S5P_VA_DMC1 + 0x30) * 1000); |
455 | s5pv210_dram_conf[1].freq = clk_get_rate(dmc1_clk); |
456 | |
457 | policy->cur = policy->min = policy->max = s5pv210_getspeed(0); |
458 | |
459 | cpufreq_frequency_table_get_attr(s5pv210_freq_table, policy->cpu); |
460 | |
461 | policy->cpuinfo.transition_latency = 40000; |
462 | |
463 | return cpufreq_frequency_table_cpuinfo(policy, s5pv210_freq_table); |
464 | } |
465 | |
466 | static struct cpufreq_driver s5pv210_driver = { |
467 | .flags = CPUFREQ_STICKY, |
468 | .verify = s5pv210_verify_speed, |
469 | .target = s5pv210_target, |
470 | .get = s5pv210_getspeed, |
471 | .init = s5pv210_cpu_init, |
472 | .name = "s5pv210", |
473 | #ifdef CONFIG_PM |
474 | .suspend = s5pv210_cpufreq_suspend, |
475 | .resume = s5pv210_cpufreq_resume, |
476 | #endif |
477 | }; |
478 | |
479 | static int __init s5pv210_cpufreq_init(void) |
480 | { |
481 | return cpufreq_register_driver(&s5pv210_driver); |
482 | } |
483 | |
484 | late_initcall(s5pv210_cpufreq_init); |
485 |
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