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1 | /* linux/arch/arm/plat-s5p/sleep.S |
2 | * |
3 | * Copyright (c) 2010 Samsung Electronics Co., Ltd. |
4 | * http://www.samsung.com |
5 | * |
6 | * S5PV210 power Manager (Suspend-To-RAM) support |
7 | * Based on S3C2410 sleep code by: |
8 | * Ben Dooks, (c) 2004 Simtec Electronics |
9 | * |
10 | * Based on PXA/SA1100 sleep code by: |
11 | * Nicolas Pitre, (c) 2002 Monta Vista Software Inc |
12 | * Cliff Brake, (c) 2001 |
13 | * |
14 | * This program is free software; you can redistribute it and/or modify |
15 | * it under the terms of the GNU General Public License as published by |
16 | * the Free Software Foundation; either version 2 of the License, or |
17 | * (at your option) any later version. |
18 | * |
19 | * This program is distributed in the hope that it will be useful, |
20 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
21 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
22 | * GNU General Public License for more details. |
23 | * |
24 | * You should have received a copy of the GNU General Public License |
25 | * along with this program; if not, write to the Free Software |
26 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
27 | */ |
28 | |
29 | #include <linux/linkage.h> |
30 | #include <asm/assembler.h> |
31 | #include <asm/memory.h> |
32 | |
33 | .text |
34 | |
35 | /* s3c_cpu_save |
36 | * |
37 | * entry: |
38 | * r0 = save address (virtual addr of s3c_sleep_save_phys) |
39 | */ |
40 | |
41 | ENTRY(s3c_cpu_save) |
42 | |
43 | stmfd sp!, { r3 - r12, lr } |
44 | |
45 | mrc p15, 0, r4, c13, c0, 0 @ FCSE/PID |
46 | mrc p15, 0, r5, c3, c0, 0 @ Domain ID |
47 | mrc p15, 0, r6, c2, c0, 0 @ Translation Table BASE0 |
48 | mrc p15, 0, r7, c2, c0, 1 @ Translation Table BASE1 |
49 | mrc p15, 0, r8, c2, c0, 2 @ Translation Table Control |
50 | mrc p15, 0, r9, c1, c0, 0 @ Control register |
51 | mrc p15, 0, r10, c1, c0, 1 @ Auxiliary control register |
52 | mrc p15, 0, r11, c1, c0, 2 @ Co-processor access controls |
53 | mrc p15, 0, r12, c10, c2, 0 @ Read PRRR |
54 | mrc p15, 0, r3, c10, c2, 1 @ READ NMRR |
55 | |
56 | stmia r0, { r3 - r13 } |
57 | |
58 | bl s3c_pm_cb_flushcache |
59 | |
60 | ldr r0, =pm_cpu_sleep |
61 | ldr r0, [ r0 ] |
62 | mov pc, r0 |
63 | |
64 | resume_with_mmu: |
65 | /* |
66 | * After MMU is turned on, restore the previous MMU table. |
67 | */ |
68 | ldr r9 , =(PAGE_OFFSET - PHYS_OFFSET) |
69 | add r4, r4, r9 |
70 | str r12, [r4] |
71 | |
72 | ldmfd sp!, { r3 - r12, pc } |
73 | |
74 | .ltorg |
75 | |
76 | .data |
77 | |
78 | .global s3c_sleep_save_phys |
79 | s3c_sleep_save_phys: |
80 | .word 0 |
81 | |
82 | /* sleep magic, to allow the bootloader to check for an valid |
83 | * image to resume to. Must be the first word before the |
84 | * s3c_cpu_resume entry. |
85 | */ |
86 | |
87 | .word 0x2bedf00d |
88 | |
89 | /* s3c_cpu_resume |
90 | * |
91 | * resume code entry for bootloader to call |
92 | * |
93 | * we must put this code here in the data segment as we have no |
94 | * other way of restoring the stack pointer after sleep, and we |
95 | * must not write to the code segment (code is read-only) |
96 | */ |
97 | |
98 | ENTRY(s3c_cpu_resume) |
99 | mov r0, #PSR_I_BIT | PSR_F_BIT | SVC_MODE |
100 | msr cpsr_c, r0 |
101 | |
102 | mov r1, #0 |
103 | mcr p15, 0, r1, c8, c7, 0 @ invalidate TLBs |
104 | mcr p15, 0, r1, c7, c5, 0 @ invalidate I Cache |
105 | |
106 | ldr r0, s3c_sleep_save_phys @ address of restore block |
107 | ldmia r0, { r3 - r13 } |
108 | |
109 | mcr p15, 0, r4, c13, c0, 0 @ FCSE/PID |
110 | mcr p15, 0, r5, c3, c0, 0 @ Domain ID |
111 | |
112 | mcr p15, 0, r8, c2, c0, 2 @ Translation Table Control |
113 | mcr p15, 0, r7, c2, c0, 1 @ Translation Table BASE1 |
114 | mcr p15, 0, r6, c2, c0, 0 @ Translation Table BASE0 |
115 | |
116 | mcr p15, 0, r10, c1, c0, 1 @ Auxiliary control register |
117 | |
118 | mov r0, #0 |
119 | mcr p15, 0, r0, c8, c7, 0 @ Invalidate I & D TLB |
120 | |
121 | mov r0, #0 @ restore copro access |
122 | mcr p15, 0, r11, c1, c0, 2 @ Co-processor access |
123 | mcr p15, 0, r0, c7, c5, 4 |
124 | |
125 | mcr p15, 0, r12, c10, c2, 0 @ write PRRR |
126 | mcr p15, 0, r3, c10, c2, 1 @ write NMRR |
127 | |
128 | /* |
129 | * In Cortex-A8, when MMU is turned on, the pipeline is flushed. |
130 | * And there are no valid entries in the MMU table at this point. |
131 | * So before turning on the MMU, the MMU entry for the DRAM address |
132 | * range is added. After the MMU is turned on, the other entries |
133 | * in the MMU table will be restored. |
134 | */ |
135 | |
136 | /* r6 = Translation Table BASE0 */ |
137 | mov r4, r6 |
138 | mov r4, r4, LSR #14 |
139 | mov r4, r4, LSL #14 |
140 | |
141 | /* Load address for adding to MMU table list */ |
142 | ldr r11, =0xE010F000 @ INFORM0 reg. |
143 | ldr r10, [r11, #0] |
144 | mov r10, r10, LSR #18 |
145 | bic r10, r10, #0x3 |
146 | orr r4, r4, r10 |
147 | |
148 | /* Calculate MMU table entry */ |
149 | mov r10, r10, LSL #18 |
150 | ldr r5, =0x40E |
151 | orr r10, r10, r5 |
152 | |
153 | /* Back up originally data */ |
154 | ldr r12, [r4] |
155 | |
156 | /* Add calculated MMU table entry into MMU table list */ |
157 | str r10, [r4] |
158 | |
159 | ldr r2, =resume_with_mmu |
160 | mcr p15, 0, r9, c1, c0, 0 @ turn on MMU, etc |
161 | |
162 | nop |
163 | nop |
164 | nop |
165 | nop |
166 | nop @ second-to-last before mmu |
167 | |
168 | mov pc, r2 @ go back to virtual address |
169 | |
170 | .ltorg |
171 |
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od-2011-09-18
v2.6.34-rc5
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v3.9