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1 | /* linux/arch/arm/mach-s5pv310/platsmp.c |
2 | * |
3 | * Copyright (c) 2010 Samsung Electronics Co., Ltd. |
4 | * http://www.samsung.com/ |
5 | * |
6 | * Cloned from linux/arch/arm/mach-vexpress/platsmp.c |
7 | * |
8 | * Copyright (C) 2002 ARM Ltd. |
9 | * All Rights Reserved |
10 | * |
11 | * This program is free software; you can redistribute it and/or modify |
12 | * it under the terms of the GNU General Public License version 2 as |
13 | * published by the Free Software Foundation. |
14 | */ |
15 | |
16 | #include <linux/init.h> |
17 | #include <linux/errno.h> |
18 | #include <linux/delay.h> |
19 | #include <linux/device.h> |
20 | #include <linux/jiffies.h> |
21 | #include <linux/smp.h> |
22 | #include <linux/io.h> |
23 | |
24 | #include <asm/cacheflush.h> |
25 | #include <asm/localtimer.h> |
26 | #include <asm/smp_scu.h> |
27 | #include <asm/unified.h> |
28 | |
29 | #include <mach/hardware.h> |
30 | #include <mach/regs-clock.h> |
31 | |
32 | extern void s5pv310_secondary_startup(void); |
33 | |
34 | /* |
35 | * control for which core is the next to come out of the secondary |
36 | * boot "holding pen" |
37 | */ |
38 | |
39 | volatile int __cpuinitdata pen_release = -1; |
40 | |
41 | static void __iomem *scu_base_addr(void) |
42 | { |
43 | return (void __iomem *)(S5P_VA_SCU); |
44 | } |
45 | |
46 | static DEFINE_SPINLOCK(boot_lock); |
47 | |
48 | void __cpuinit platform_secondary_init(unsigned int cpu) |
49 | { |
50 | trace_hardirqs_off(); |
51 | |
52 | /* |
53 | * if any interrupts are already enabled for the primary |
54 | * core (e.g. timer irq), then they will not have been enabled |
55 | * for us: do so |
56 | */ |
57 | gic_cpu_init(0, gic_cpu_base_addr); |
58 | |
59 | /* |
60 | * let the primary processor know we're out of the |
61 | * pen, then head off into the C entry point |
62 | */ |
63 | pen_release = -1; |
64 | smp_wmb(); |
65 | |
66 | /* |
67 | * Synchronise with the boot thread. |
68 | */ |
69 | spin_lock(&boot_lock); |
70 | spin_unlock(&boot_lock); |
71 | } |
72 | |
73 | int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle) |
74 | { |
75 | unsigned long timeout; |
76 | |
77 | /* |
78 | * Set synchronisation state between this boot processor |
79 | * and the secondary one |
80 | */ |
81 | spin_lock(&boot_lock); |
82 | |
83 | /* |
84 | * The secondary processor is waiting to be released from |
85 | * the holding pen - release it, then wait for it to flag |
86 | * that it has been released by resetting pen_release. |
87 | * |
88 | * Note that "pen_release" is the hardware CPU ID, whereas |
89 | * "cpu" is Linux's internal ID. |
90 | */ |
91 | pen_release = cpu; |
92 | __cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release)); |
93 | outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1)); |
94 | |
95 | /* |
96 | * Send the secondary CPU a soft interrupt, thereby causing |
97 | * the boot monitor to read the system wide flags register, |
98 | * and branch to the address found there. |
99 | */ |
100 | smp_cross_call(cpumask_of(cpu)); |
101 | |
102 | timeout = jiffies + (1 * HZ); |
103 | while (time_before(jiffies, timeout)) { |
104 | smp_rmb(); |
105 | if (pen_release == -1) |
106 | break; |
107 | |
108 | udelay(10); |
109 | } |
110 | |
111 | /* |
112 | * now the secondary core is starting up let it run its |
113 | * calibrations, then wait for it to finish |
114 | */ |
115 | spin_unlock(&boot_lock); |
116 | |
117 | return pen_release != -1 ? -ENOSYS : 0; |
118 | } |
119 | |
120 | /* |
121 | * Initialise the CPU possible map early - this describes the CPUs |
122 | * which may be present or become present in the system. |
123 | */ |
124 | |
125 | void __init smp_init_cpus(void) |
126 | { |
127 | void __iomem *scu_base = scu_base_addr(); |
128 | unsigned int i, ncores; |
129 | |
130 | ncores = scu_base ? scu_get_core_count(scu_base) : 1; |
131 | |
132 | /* sanity check */ |
133 | if (ncores == 0) { |
134 | printk(KERN_ERR |
135 | "S5PV310: strange CM count of 0? Default to 1\n"); |
136 | |
137 | ncores = 1; |
138 | } |
139 | |
140 | if (ncores > NR_CPUS) { |
141 | printk(KERN_WARNING |
142 | "S5PV310: no. of cores (%d) greater than configured " |
143 | "maximum of %d - clipping\n", |
144 | ncores, NR_CPUS); |
145 | ncores = NR_CPUS; |
146 | } |
147 | |
148 | for (i = 0; i < ncores; i++) |
149 | set_cpu_possible(i, true); |
150 | } |
151 | |
152 | void __init smp_prepare_cpus(unsigned int max_cpus) |
153 | { |
154 | unsigned int ncores = num_possible_cpus(); |
155 | unsigned int cpu = smp_processor_id(); |
156 | int i; |
157 | |
158 | smp_store_cpu_info(cpu); |
159 | |
160 | /* are we trying to boot more cores than exist? */ |
161 | if (max_cpus > ncores) |
162 | max_cpus = ncores; |
163 | |
164 | /* |
165 | * Initialise the present map, which describes the set of CPUs |
166 | * actually populated at the present time. |
167 | */ |
168 | for (i = 0; i < max_cpus; i++) |
169 | set_cpu_present(i, true); |
170 | |
171 | /* |
172 | * Initialise the SCU if there are more than one CPU and let |
173 | * them know where to start. |
174 | */ |
175 | if (max_cpus > 1) { |
176 | /* |
177 | * Enable the local timer or broadcast device for the |
178 | * boot CPU, but only if we have more than one CPU. |
179 | */ |
180 | percpu_timer_setup(); |
181 | |
182 | scu_enable(scu_base_addr()); |
183 | |
184 | /* |
185 | * Write the address of secondary startup into the |
186 | * system-wide flags register. The boot monitor waits |
187 | * until it receives a soft interrupt, and then the |
188 | * secondary CPU branches to this address. |
189 | */ |
190 | __raw_writel(BSYM(virt_to_phys(s5pv310_secondary_startup)), S5P_VA_SYSRAM); |
191 | } |
192 | } |
193 |
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