Root/arch/arm/plat-samsung/clock.c

1/* linux/arch/arm/plat-s3c24xx/clock.c
2 *
3 * Copyright 2004-2005 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * S3C24XX Core clock control support
7 *
8 * Based on, and code from linux/arch/arm/mach-versatile/clock.c
9 **
10 ** Copyright (C) 2004 ARM Limited.
11 ** Written by Deep Blue Solutions Limited.
12 *
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
27*/
28
29#include <linux/init.h>
30#include <linux/module.h>
31#include <linux/kernel.h>
32#include <linux/list.h>
33#include <linux/errno.h>
34#include <linux/err.h>
35#include <linux/platform_device.h>
36#include <linux/sysdev.h>
37#include <linux/interrupt.h>
38#include <linux/ioport.h>
39#include <linux/clk.h>
40#include <linux/spinlock.h>
41#include <linux/io.h>
42
43#include <mach/hardware.h>
44#include <asm/irq.h>
45
46#include <plat/cpu-freq.h>
47
48#include <plat/clock.h>
49#include <plat/cpu.h>
50
51#include <linux/serial_core.h>
52#include <plat/regs-serial.h> /* for s3c24xx_uart_devs */
53
54/* clock information */
55
56static LIST_HEAD(clocks);
57
58/* We originally used an mutex here, but some contexts (see resume)
59 * are calling functions such as clk_set_parent() with IRQs disabled
60 * causing an BUG to be triggered.
61 */
62DEFINE_SPINLOCK(clocks_lock);
63
64/* enable and disable calls for use with the clk struct */
65
66static int clk_null_enable(struct clk *clk, int enable)
67{
68    return 0;
69}
70
71static int dev_is_s3c_uart(struct device *dev)
72{
73    struct platform_device **pdev = s3c24xx_uart_devs;
74    int i;
75    for (i = 0; i < ARRAY_SIZE(s3c24xx_uart_devs); i++, pdev++)
76        if (*pdev && dev == &(*pdev)->dev)
77            return 1;
78    return 0;
79}
80
81/*
82 * Serial drivers call get_clock() very early, before platform bus
83 * has been set up, this requires a special check to let them get
84 * a proper clock
85 */
86
87static int dev_is_platform_device(struct device *dev)
88{
89    return dev->bus == &platform_bus_type ||
90           (dev->bus == NULL && dev_is_s3c_uart(dev));
91}
92
93/* Clock API calls */
94
95struct clk *clk_get(struct device *dev, const char *id)
96{
97    struct clk *p;
98    struct clk *clk = ERR_PTR(-ENOENT);
99    int idno;
100
101    if (dev == NULL || !dev_is_platform_device(dev))
102        idno = -1;
103    else
104        idno = to_platform_device(dev)->id;
105
106    spin_lock(&clocks_lock);
107
108    list_for_each_entry(p, &clocks, list) {
109        if (p->id == idno &&
110            strcmp(id, p->name) == 0 &&
111            try_module_get(p->owner)) {
112            clk = p;
113            break;
114        }
115    }
116
117    /* check for the case where a device was supplied, but the
118     * clock that was being searched for is not device specific */
119
120    if (IS_ERR(clk)) {
121        list_for_each_entry(p, &clocks, list) {
122            if (p->id == -1 && strcmp(id, p->name) == 0 &&
123                try_module_get(p->owner)) {
124                clk = p;
125                break;
126            }
127        }
128    }
129
130    spin_unlock(&clocks_lock);
131    return clk;
132}
133
134void clk_put(struct clk *clk)
135{
136    module_put(clk->owner);
137}
138
139int clk_enable(struct clk *clk)
140{
141    if (IS_ERR(clk) || clk == NULL)
142        return -EINVAL;
143
144    clk_enable(clk->parent);
145
146    spin_lock(&clocks_lock);
147
148    if ((clk->usage++) == 0)
149        (clk->enable)(clk, 1);
150
151    spin_unlock(&clocks_lock);
152    return 0;
153}
154
155void clk_disable(struct clk *clk)
156{
157    if (IS_ERR(clk) || clk == NULL)
158        return;
159
160    spin_lock(&clocks_lock);
161
162    if ((--clk->usage) == 0)
163        (clk->enable)(clk, 0);
164
165    spin_unlock(&clocks_lock);
166    clk_disable(clk->parent);
167}
168
169
170unsigned long clk_get_rate(struct clk *clk)
171{
172    if (IS_ERR(clk))
173        return 0;
174
175    if (clk->rate != 0)
176        return clk->rate;
177
178    if (clk->ops != NULL && clk->ops->get_rate != NULL)
179        return (clk->ops->get_rate)(clk);
180
181    if (clk->parent != NULL)
182        return clk_get_rate(clk->parent);
183
184    return clk->rate;
185}
186
187long clk_round_rate(struct clk *clk, unsigned long rate)
188{
189    if (!IS_ERR(clk) && clk->ops && clk->ops->round_rate)
190        return (clk->ops->round_rate)(clk, rate);
191
192    return rate;
193}
194
195int clk_set_rate(struct clk *clk, unsigned long rate)
196{
197    int ret;
198
199    if (IS_ERR(clk))
200        return -EINVAL;
201
202    /* We do not default just do a clk->rate = rate as
203     * the clock may have been made this way by choice.
204     */
205
206    WARN_ON(clk->ops == NULL);
207    WARN_ON(clk->ops && clk->ops->set_rate == NULL);
208
209    if (clk->ops == NULL || clk->ops->set_rate == NULL)
210        return -EINVAL;
211
212    spin_lock(&clocks_lock);
213    ret = (clk->ops->set_rate)(clk, rate);
214    spin_unlock(&clocks_lock);
215
216    return ret;
217}
218
219struct clk *clk_get_parent(struct clk *clk)
220{
221    return clk->parent;
222}
223
224int clk_set_parent(struct clk *clk, struct clk *parent)
225{
226    int ret = 0;
227
228    if (IS_ERR(clk))
229        return -EINVAL;
230
231    spin_lock(&clocks_lock);
232
233    if (clk->ops && clk->ops->set_parent)
234        ret = (clk->ops->set_parent)(clk, parent);
235
236    spin_unlock(&clocks_lock);
237
238    return ret;
239}
240
241EXPORT_SYMBOL(clk_get);
242EXPORT_SYMBOL(clk_put);
243EXPORT_SYMBOL(clk_enable);
244EXPORT_SYMBOL(clk_disable);
245EXPORT_SYMBOL(clk_get_rate);
246EXPORT_SYMBOL(clk_round_rate);
247EXPORT_SYMBOL(clk_set_rate);
248EXPORT_SYMBOL(clk_get_parent);
249EXPORT_SYMBOL(clk_set_parent);
250
251/* base clocks */
252
253int clk_default_setrate(struct clk *clk, unsigned long rate)
254{
255    clk->rate = rate;
256    return 0;
257}
258
259struct clk_ops clk_ops_def_setrate = {
260    .set_rate = clk_default_setrate,
261};
262
263struct clk clk_xtal = {
264    .name = "xtal",
265    .id = -1,
266    .rate = 0,
267    .parent = NULL,
268    .ctrlbit = 0,
269};
270
271struct clk clk_ext = {
272    .name = "ext",
273    .id = -1,
274};
275
276struct clk clk_epll = {
277    .name = "epll",
278    .id = -1,
279};
280
281struct clk clk_mpll = {
282    .name = "mpll",
283    .id = -1,
284    .ops = &clk_ops_def_setrate,
285};
286
287struct clk clk_upll = {
288    .name = "upll",
289    .id = -1,
290    .parent = NULL,
291    .ctrlbit = 0,
292};
293
294struct clk clk_f = {
295    .name = "fclk",
296    .id = -1,
297    .rate = 0,
298    .parent = &clk_mpll,
299    .ctrlbit = 0,
300};
301
302struct clk clk_h = {
303    .name = "hclk",
304    .id = -1,
305    .rate = 0,
306    .parent = NULL,
307    .ctrlbit = 0,
308    .ops = &clk_ops_def_setrate,
309};
310
311struct clk clk_p = {
312    .name = "pclk",
313    .id = -1,
314    .rate = 0,
315    .parent = NULL,
316    .ctrlbit = 0,
317    .ops = &clk_ops_def_setrate,
318};
319
320struct clk clk_usb_bus = {
321    .name = "usb-bus",
322    .id = -1,
323    .rate = 0,
324    .parent = &clk_upll,
325};
326
327
328struct clk s3c24xx_uclk = {
329    .name = "uclk",
330    .id = -1,
331};
332
333/* initialise the clock system */
334
335/**
336 * s3c24xx_register_clock() - register a clock
337 * @clk: The clock to register
338 *
339 * Add the specified clock to the list of clocks known by the system.
340 */
341int s3c24xx_register_clock(struct clk *clk)
342{
343    if (clk->enable == NULL)
344        clk->enable = clk_null_enable;
345
346    /* add to the list of available clocks */
347
348    /* Quick check to see if this clock has already been registered. */
349    BUG_ON(clk->list.prev != clk->list.next);
350
351    spin_lock(&clocks_lock);
352    list_add(&clk->list, &clocks);
353    spin_unlock(&clocks_lock);
354
355    return 0;
356}
357
358/**
359 * s3c24xx_register_clocks() - register an array of clock pointers
360 * @clks: Pointer to an array of struct clk pointers
361 * @nr_clks: The number of clocks in the @clks array.
362 *
363 * Call s3c24xx_register_clock() for all the clock pointers contained
364 * in the @clks list. Returns the number of failures.
365 */
366int s3c24xx_register_clocks(struct clk **clks, int nr_clks)
367{
368    int fails = 0;
369
370    for (; nr_clks > 0; nr_clks--, clks++) {
371        if (s3c24xx_register_clock(*clks) < 0) {
372            struct clk *clk = *clks;
373            printk(KERN_ERR "%s: failed to register %p: %s\n",
374                   __func__, clk, clk->name);
375            fails++;
376        }
377    }
378
379    return fails;
380}
381
382/**
383 * s3c_register_clocks() - register an array of clocks
384 * @clkp: Pointer to the first clock in the array.
385 * @nr_clks: Number of clocks to register.
386 *
387 * Call s3c24xx_register_clock() on the @clkp array given, printing an
388 * error if it fails to register the clock (unlikely).
389 */
390void __init s3c_register_clocks(struct clk *clkp, int nr_clks)
391{
392    int ret;
393
394    for (; nr_clks > 0; nr_clks--, clkp++) {
395        ret = s3c24xx_register_clock(clkp);
396
397        if (ret < 0) {
398            printk(KERN_ERR "Failed to register clock %s (%d)\n",
399                   clkp->name, ret);
400        }
401    }
402}
403
404/**
405 * s3c_disable_clocks() - disable an array of clocks
406 * @clkp: Pointer to the first clock in the array.
407 * @nr_clks: Number of clocks to register.
408 *
409 * for internal use only at initialisation time. disable the clocks in the
410 * @clkp array.
411 */
412
413void __init s3c_disable_clocks(struct clk *clkp, int nr_clks)
414{
415    for (; nr_clks > 0; nr_clks--, clkp++)
416        (clkp->enable)(clkp, 0);
417}
418
419/* initialise all the clocks */
420
421int __init s3c24xx_register_baseclocks(unsigned long xtal)
422{
423    printk(KERN_INFO "S3C24XX Clocks, Copyright 2004 Simtec Electronics\n");
424
425    clk_xtal.rate = xtal;
426
427    /* register our clocks */
428
429    if (s3c24xx_register_clock(&clk_xtal) < 0)
430        printk(KERN_ERR "failed to register master xtal\n");
431
432    if (s3c24xx_register_clock(&clk_mpll) < 0)
433        printk(KERN_ERR "failed to register mpll clock\n");
434
435    if (s3c24xx_register_clock(&clk_upll) < 0)
436        printk(KERN_ERR "failed to register upll clock\n");
437
438    if (s3c24xx_register_clock(&clk_f) < 0)
439        printk(KERN_ERR "failed to register cpu fclk\n");
440
441    if (s3c24xx_register_clock(&clk_h) < 0)
442        printk(KERN_ERR "failed to register cpu hclk\n");
443
444    if (s3c24xx_register_clock(&clk_p) < 0)
445        printk(KERN_ERR "failed to register cpu pclk\n");
446
447    return 0;
448}
449
450

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