Root/arch/blackfin/Kconfig

1config SYMBOL_PREFIX
2    string
3    default "_"
4
5config MMU
6    def_bool n
7
8config FPU
9    def_bool n
10
11config RWSEM_GENERIC_SPINLOCK
12    def_bool y
13
14config RWSEM_XCHGADD_ALGORITHM
15    def_bool n
16
17config BLACKFIN
18    def_bool y
19    select HAVE_ARCH_KGDB
20    select HAVE_ARCH_TRACEHOOK
21    select HAVE_DYNAMIC_FTRACE
22    select HAVE_FTRACE_MCOUNT_RECORD
23    select HAVE_FUNCTION_GRAPH_TRACER
24    select HAVE_FUNCTION_TRACER
25    select HAVE_FUNCTION_TRACE_MCOUNT_TEST
26    select HAVE_IDE
27    select HAVE_KERNEL_GZIP if RAMKERNEL
28    select HAVE_KERNEL_BZIP2 if RAMKERNEL
29    select HAVE_KERNEL_LZMA if RAMKERNEL
30    select HAVE_KERNEL_LZO if RAMKERNEL
31    select HAVE_OPROFILE
32    select ARCH_WANT_OPTIONAL_GPIOLIB
33
34config GENERIC_CSUM
35    def_bool y
36
37config GENERIC_BUG
38    def_bool y
39    depends on BUG
40
41config ZONE_DMA
42    def_bool y
43
44config GENERIC_FIND_NEXT_BIT
45    def_bool y
46
47config GENERIC_HARDIRQS
48    def_bool y
49
50config GENERIC_IRQ_PROBE
51    def_bool y
52
53config GENERIC_HARDIRQS_NO__DO_IRQ
54    def_bool y
55
56config GENERIC_GPIO
57    def_bool y
58
59config FORCE_MAX_ZONEORDER
60    int
61    default "14"
62
63config GENERIC_CALIBRATE_DELAY
64    def_bool y
65
66config LOCKDEP_SUPPORT
67    def_bool y
68
69config STACKTRACE_SUPPORT
70    def_bool y
71
72config TRACE_IRQFLAGS_SUPPORT
73    def_bool y
74
75source "init/Kconfig"
76
77source "kernel/Kconfig.preempt"
78
79source "kernel/Kconfig.freezer"
80
81menu "Blackfin Processor Options"
82
83comment "Processor and Board Settings"
84
85choice
86    prompt "CPU"
87    default BF533
88
89config BF512
90    bool "BF512"
91    help
92      BF512 Processor Support.
93
94config BF514
95    bool "BF514"
96    help
97      BF514 Processor Support.
98
99config BF516
100    bool "BF516"
101    help
102      BF516 Processor Support.
103
104config BF518
105    bool "BF518"
106    help
107      BF518 Processor Support.
108
109config BF522
110    bool "BF522"
111    help
112      BF522 Processor Support.
113
114config BF523
115    bool "BF523"
116    help
117      BF523 Processor Support.
118
119config BF524
120    bool "BF524"
121    help
122      BF524 Processor Support.
123
124config BF525
125    bool "BF525"
126    help
127      BF525 Processor Support.
128
129config BF526
130    bool "BF526"
131    help
132      BF526 Processor Support.
133
134config BF527
135    bool "BF527"
136    help
137      BF527 Processor Support.
138
139config BF531
140    bool "BF531"
141    help
142      BF531 Processor Support.
143
144config BF532
145    bool "BF532"
146    help
147      BF532 Processor Support.
148
149config BF533
150    bool "BF533"
151    help
152      BF533 Processor Support.
153
154config BF534
155    bool "BF534"
156    help
157      BF534 Processor Support.
158
159config BF536
160    bool "BF536"
161    help
162      BF536 Processor Support.
163
164config BF537
165    bool "BF537"
166    help
167      BF537 Processor Support.
168
169config BF538
170    bool "BF538"
171    help
172      BF538 Processor Support.
173
174config BF539
175    bool "BF539"
176    help
177      BF539 Processor Support.
178
179config BF542_std
180    bool "BF542"
181    help
182      BF542 Processor Support.
183
184config BF542M
185    bool "BF542m"
186    help
187      BF542 Processor Support.
188
189config BF544_std
190    bool "BF544"
191    help
192      BF544 Processor Support.
193
194config BF544M
195    bool "BF544m"
196    help
197      BF544 Processor Support.
198
199config BF547_std
200    bool "BF547"
201    help
202      BF547 Processor Support.
203
204config BF547M
205    bool "BF547m"
206    help
207      BF547 Processor Support.
208
209config BF548_std
210    bool "BF548"
211    help
212      BF548 Processor Support.
213
214config BF548M
215    bool "BF548m"
216    help
217      BF548 Processor Support.
218
219config BF549_std
220    bool "BF549"
221    help
222      BF549 Processor Support.
223
224config BF549M
225    bool "BF549m"
226    help
227      BF549 Processor Support.
228
229config BF561
230    bool "BF561"
231    help
232      BF561 Processor Support.
233
234endchoice
235
236config SMP
237    depends on BF561
238    select TICKSOURCE_CORETMR
239    bool "Symmetric multi-processing support"
240    ---help---
241      This enables support for systems with more than one CPU,
242      like the dual core BF561. If you have a system with only one
243      CPU, say N. If you have a system with more than one CPU, say Y.
244
245      If you don't know what to do here, say N.
246
247config NR_CPUS
248    int
249    depends on SMP
250    default 2 if BF561
251
252config HOTPLUG_CPU
253    bool "Support for hot-pluggable CPUs"
254    depends on SMP && HOTPLUG
255    default y
256
257config IRQ_PER_CPU
258    bool
259    depends on SMP
260    default y
261
262config HAVE_LEGACY_PER_CPU_AREA
263    def_bool y
264    depends on SMP
265
266config BF_REV_MIN
267    int
268    default 0 if (BF51x || BF52x || (BF54x && !BF54xM))
269    default 2 if (BF537 || BF536 || BF534)
270    default 3 if (BF561 || BF533 || BF532 || BF531 || BF54xM)
271    default 4 if (BF538 || BF539)
272
273config BF_REV_MAX
274    int
275    default 2 if (BF51x || BF52x || (BF54x && !BF54xM))
276    default 3 if (BF537 || BF536 || BF534 || BF54xM)
277    default 5 if (BF561 || BF538 || BF539)
278    default 6 if (BF533 || BF532 || BF531)
279
280choice
281    prompt "Silicon Rev"
282    default BF_REV_0_0 if (BF51x || BF52x)
283    default BF_REV_0_2 if (BF534 || BF536 || BF537 || (BF54x && !BF54xM))
284    default BF_REV_0_3 if (BF531 || BF532 || BF533 || BF54xM || BF561)
285
286config BF_REV_0_0
287    bool "0.0"
288    depends on (BF51x || BF52x || (BF54x && !BF54xM))
289
290config BF_REV_0_1
291    bool "0.1"
292    depends on (BF51x || BF52x || (BF54x && !BF54xM))
293
294config BF_REV_0_2
295    bool "0.2"
296    depends on (BF51x || BF52x || BF537 || BF536 || BF534 || (BF54x && !BF54xM))
297
298config BF_REV_0_3
299    bool "0.3"
300    depends on (BF54xM || BF561 || BF537 || BF536 || BF534 || BF533 || BF532 || BF531)
301
302config BF_REV_0_4
303    bool "0.4"
304    depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539)
305
306config BF_REV_0_5
307    bool "0.5"
308    depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539)
309
310config BF_REV_0_6
311    bool "0.6"
312    depends on (BF533 || BF532 || BF531)
313
314config BF_REV_ANY
315    bool "any"
316
317config BF_REV_NONE
318    bool "none"
319
320endchoice
321
322config BF53x
323    bool
324    depends on (BF531 || BF532 || BF533 || BF534 || BF536 || BF537)
325    default y
326
327config MEM_MT48LC64M4A2FB_7E
328    bool
329    depends on (BFIN533_STAMP)
330    default y
331
332config MEM_MT48LC16M16A2TG_75
333    bool
334    depends on (BFIN533_EZKIT || BFIN561_EZKIT \
335        || BFIN533_BLUETECHNIX_CM || BFIN537_BLUETECHNIX_CM_E \
336        || BFIN537_BLUETECHNIX_CM_U || H8606_HVSISTEMAS \
337        || BFIN527_BLUETECHNIX_CM)
338    default y
339
340config MEM_MT48LC32M8A2_75
341    bool
342    depends on (BFIN518F_EZBRD || BFIN537_STAMP || PNAV10 || BFIN538_EZKIT)
343    default y
344
345config MEM_MT48LC8M32B2B5_7
346    bool
347    depends on (BFIN561_BLUETECHNIX_CM)
348    default y
349
350config MEM_MT48LC32M16A2TG_75
351    bool
352    depends on (BFIN527_EZKIT || BFIN527_EZKIT_V2 || BFIN532_IP0X || BLACKSTAMP || BFIN527_AD7160EVAL)
353    default y
354
355config MEM_MT48H32M16LFCJ_75
356    bool
357    depends on (BFIN526_EZBRD)
358    default y
359
360source "arch/blackfin/mach-bf518/Kconfig"
361source "arch/blackfin/mach-bf527/Kconfig"
362source "arch/blackfin/mach-bf533/Kconfig"
363source "arch/blackfin/mach-bf561/Kconfig"
364source "arch/blackfin/mach-bf537/Kconfig"
365source "arch/blackfin/mach-bf538/Kconfig"
366source "arch/blackfin/mach-bf548/Kconfig"
367
368menu "Board customizations"
369
370config CMDLINE_BOOL
371    bool "Default bootloader kernel arguments"
372
373config CMDLINE
374    string "Initial kernel command string"
375    depends on CMDLINE_BOOL
376    default "console=ttyBF0,57600"
377    help
378      If you don't have a boot loader capable of passing a command line string
379      to the kernel, you may specify one here. As a minimum, you should specify
380      the memory size and the root device (e.g., mem=8M, root=/dev/nfs).
381
382config BOOT_LOAD
383    hex "Kernel load address for booting"
384    default "0x1000"
385    range 0x1000 0x20000000
386    help
387      This option allows you to set the load address of the kernel.
388      This can be useful if you are on a board which has a small amount
389      of memory or you wish to reserve some memory at the beginning of
390      the address space.
391
392      Note that you need to keep this value above 4k (0x1000) as this
393      memory region is used to capture NULL pointer references as well
394      as some core kernel functions.
395
396config ROM_BASE
397    hex "Kernel ROM Base"
398    depends on ROMKERNEL
399    default "0x20040040"
400    range 0x20000000 0x20400000 if !(BF54x || BF561)
401    range 0x20000000 0x30000000 if (BF54x || BF561)
402    help
403      Make sure your ROM base does not include any file-header
404      information that is prepended to the kernel.
405
406      For example, the bootable U-Boot format (created with
407      mkimage) has a 64 byte header (0x40). So while the image
408      you write to flash might start at say 0x20080000, you have
409      to add 0x40 to get the kernel's ROM base as it will come
410      after the header.
411
412comment "Clock/PLL Setup"
413
414config CLKIN_HZ
415    int "Frequency of the crystal on the board in Hz"
416    default "10000000" if BFIN532_IP0X
417    default "11059200" if BFIN533_STAMP
418    default "24576000" if PNAV10
419    default "25000000" # most people use this
420    default "27000000" if BFIN533_EZKIT
421    default "30000000" if BFIN561_EZKIT
422    default "24000000" if BFIN527_AD7160EVAL
423    help
424      The frequency of CLKIN crystal oscillator on the board in Hz.
425      Warning: This value should match the crystal on the board. Otherwise,
426      peripherals won't work properly.
427
428config BFIN_KERNEL_CLOCK
429    bool "Re-program Clocks while Kernel boots?"
430    default n
431    help
432      This option decides if kernel clocks are re-programed from the
433      bootloader settings. If the clocks are not set, the SDRAM settings
434      are also not changed, and the Bootloader does 100% of the hardware
435      configuration.
436
437config PLL_BYPASS
438    bool "Bypass PLL"
439    depends on BFIN_KERNEL_CLOCK
440    default n
441
442config CLKIN_HALF
443    bool "Half Clock In"
444    depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
445    default n
446    help
447      If this is set the clock will be divided by 2, before it goes to the PLL.
448
449config VCO_MULT
450    int "VCO Multiplier"
451    depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
452    range 1 64
453    default "22" if BFIN533_EZKIT
454    default "45" if BFIN533_STAMP
455    default "20" if (BFIN537_STAMP || BFIN527_EZKIT || BFIN527_EZKIT_V2 || BFIN548_EZKIT || BFIN548_BLUETECHNIX_CM || BFIN538_EZKIT)
456    default "22" if BFIN533_BLUETECHNIX_CM
457    default "20" if (BFIN537_BLUETECHNIX_CM_E || BFIN537_BLUETECHNIX_CM_U || BFIN527_BLUETECHNIX_CM || BFIN561_BLUETECHNIX_CM)
458    default "20" if BFIN561_EZKIT
459    default "16" if (H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD || BFIN518F_EZBRD)
460    default "25" if BFIN527_AD7160EVAL
461    help
462      This controls the frequency of the on-chip PLL. This can be between 1 and 64.
463      PLL Frequency = (Crystal Frequency) * (this setting)
464
465choice
466    prompt "Core Clock Divider"
467    depends on BFIN_KERNEL_CLOCK
468    default CCLK_DIV_1
469    help
470      This sets the frequency of the core. It can be 1, 2, 4 or 8
471      Core Frequency = (PLL frequency) / (this setting)
472
473config CCLK_DIV_1
474    bool "1"
475
476config CCLK_DIV_2
477    bool "2"
478
479config CCLK_DIV_4
480    bool "4"
481
482config CCLK_DIV_8
483    bool "8"
484endchoice
485
486config SCLK_DIV
487    int "System Clock Divider"
488    depends on BFIN_KERNEL_CLOCK
489    range 1 15
490    default 5
491    help
492      This sets the frequency of the system clock (including SDRAM or DDR).
493      This can be between 1 and 15
494      System Clock = (PLL frequency) / (this setting)
495
496choice
497    prompt "DDR SDRAM Chip Type"
498    depends on BFIN_KERNEL_CLOCK
499    depends on BF54x
500    default MEM_MT46V32M16_5B
501
502config MEM_MT46V32M16_6T
503    bool "MT46V32M16_6T"
504
505config MEM_MT46V32M16_5B
506    bool "MT46V32M16_5B"
507endchoice
508
509choice
510    prompt "DDR/SDRAM Timing"
511    depends on BFIN_KERNEL_CLOCK
512    default BFIN_KERNEL_CLOCK_MEMINIT_CALC
513    help
514      This option allows you to specify Blackfin SDRAM/DDR Timing parameters
515      The calculated SDRAM timing parameters may not be 100%
516      accurate - This option is therefore marked experimental.
517
518config BFIN_KERNEL_CLOCK_MEMINIT_CALC
519    bool "Calculate Timings (EXPERIMENTAL)"
520    depends on EXPERIMENTAL
521
522config BFIN_KERNEL_CLOCK_MEMINIT_SPEC
523    bool "Provide accurate Timings based on target SCLK"
524    help
525      Please consult the Blackfin Hardware Reference Manuals as well
526      as the memory device datasheet.
527      http://docs.blackfin.uclinux.org/doku.php?id=bfin:sdram
528endchoice
529
530menu "Memory Init Control"
531    depends on BFIN_KERNEL_CLOCK_MEMINIT_SPEC
532
533config MEM_DDRCTL0
534    depends on BF54x
535    hex "DDRCTL0"
536    default 0x0
537
538config MEM_DDRCTL1
539    depends on BF54x
540    hex "DDRCTL1"
541    default 0x0
542
543config MEM_DDRCTL2
544    depends on BF54x
545    hex "DDRCTL2"
546    default 0x0
547
548config MEM_EBIU_DDRQUE
549    depends on BF54x
550    hex "DDRQUE"
551    default 0x0
552
553config MEM_SDRRC
554    depends on !BF54x
555    hex "SDRRC"
556    default 0x0
557
558config MEM_SDGCTL
559    depends on !BF54x
560    hex "SDGCTL"
561    default 0x0
562endmenu
563
564#
565# Max & Min Speeds for various Chips
566#
567config MAX_VCO_HZ
568    int
569    default 400000000 if BF512
570    default 400000000 if BF514
571    default 400000000 if BF516
572    default 400000000 if BF518
573    default 400000000 if BF522
574    default 600000000 if BF523
575    default 400000000 if BF524
576    default 600000000 if BF525
577    default 400000000 if BF526
578    default 600000000 if BF527
579    default 400000000 if BF531
580    default 400000000 if BF532
581    default 750000000 if BF533
582    default 500000000 if BF534
583    default 400000000 if BF536
584    default 600000000 if BF537
585    default 533333333 if BF538
586    default 533333333 if BF539
587    default 600000000 if BF542
588    default 533333333 if BF544
589    default 600000000 if BF547
590    default 600000000 if BF548
591    default 533333333 if BF549
592    default 600000000 if BF561
593
594config MIN_VCO_HZ
595    int
596    default 50000000
597
598config MAX_SCLK_HZ
599    int
600    default 133333333
601
602config MIN_SCLK_HZ
603    int
604    default 27000000
605
606comment "Kernel Timer/Scheduler"
607
608source kernel/Kconfig.hz
609
610config GENERIC_CLOCKEVENTS
611    bool "Generic clock events"
612    default y
613
614menu "Clock event device"
615    depends on GENERIC_CLOCKEVENTS
616config TICKSOURCE_GPTMR0
617    bool "GPTimer0"
618    depends on !SMP
619    select BFIN_GPTIMERS
620
621config TICKSOURCE_CORETMR
622    bool "Core timer"
623    default y
624endmenu
625
626menu "Clock souce"
627    depends on GENERIC_CLOCKEVENTS
628config CYCLES_CLOCKSOURCE
629    bool "CYCLES"
630    default y
631    depends on !BFIN_SCRATCH_REG_CYCLES
632    depends on !SMP
633    help
634      If you say Y here, you will enable support for using the 'cycles'
635      registers as a clock source. Doing so means you will be unable to
636      safely write to the 'cycles' register during runtime. You will
637      still be able to read it (such as for performance monitoring), but
638      writing the registers will most likely crash the kernel.
639
640config GPTMR0_CLOCKSOURCE
641    bool "GPTimer0"
642    select BFIN_GPTIMERS
643    depends on !TICKSOURCE_GPTMR0
644endmenu
645
646config ARCH_USES_GETTIMEOFFSET
647    depends on !GENERIC_CLOCKEVENTS
648    def_bool y
649
650source kernel/time/Kconfig
651
652comment "Misc"
653
654choice
655    prompt "Blackfin Exception Scratch Register"
656    default BFIN_SCRATCH_REG_RETN
657    help
658      Select the resource to reserve for the Exception handler:
659        - RETN: Non-Maskable Interrupt (NMI)
660        - RETE: Exception Return (JTAG/ICE)
661        - CYCLES: Performance counter
662
663      If you are unsure, please select "RETN".
664
665config BFIN_SCRATCH_REG_RETN
666    bool "RETN"
667    help
668      Use the RETN register in the Blackfin exception handler
669      as a stack scratch register. This means you cannot
670      safely use NMI on the Blackfin while running Linux, but
671      you can debug the system with a JTAG ICE and use the
672      CYCLES performance registers.
673
674      If you are unsure, please select "RETN".
675
676config BFIN_SCRATCH_REG_RETE
677    bool "RETE"
678    help
679      Use the RETE register in the Blackfin exception handler
680      as a stack scratch register. This means you cannot
681      safely use a JTAG ICE while debugging a Blackfin board,
682      but you can safely use the CYCLES performance registers
683      and the NMI.
684
685      If you are unsure, please select "RETN".
686
687config BFIN_SCRATCH_REG_CYCLES
688    bool "CYCLES"
689    help
690      Use the CYCLES register in the Blackfin exception handler
691      as a stack scratch register. This means you cannot
692      safely use the CYCLES performance registers on a Blackfin
693      board at anytime, but you can debug the system with a JTAG
694      ICE and use the NMI.
695
696      If you are unsure, please select "RETN".
697
698endchoice
699
700endmenu
701
702
703menu "Blackfin Kernel Optimizations"
704    depends on !SMP
705
706comment "Memory Optimizations"
707
708config I_ENTRY_L1
709    bool "Locate interrupt entry code in L1 Memory"
710    default y
711    help
712      If enabled, interrupt entry code (STORE/RESTORE CONTEXT) is linked
713      into L1 instruction memory. (less latency)
714
715config EXCPT_IRQ_SYSC_L1
716    bool "Locate entire ASM lowlevel exception / interrupt - Syscall and CPLB handler code in L1 Memory"
717    default y
718    help
719      If enabled, the entire ASM lowlevel exception and interrupt entry code
720      (STORE/RESTORE CONTEXT) is linked into L1 instruction memory.
721      (less latency)
722
723config DO_IRQ_L1
724    bool "Locate frequently called do_irq dispatcher function in L1 Memory"
725    default y
726    help
727      If enabled, the frequently called do_irq dispatcher function is linked
728      into L1 instruction memory. (less latency)
729
730config CORE_TIMER_IRQ_L1
731    bool "Locate frequently called timer_interrupt() function in L1 Memory"
732    default y
733    help
734      If enabled, the frequently called timer_interrupt() function is linked
735      into L1 instruction memory. (less latency)
736
737config IDLE_L1
738    bool "Locate frequently idle function in L1 Memory"
739    default y
740    help
741      If enabled, the frequently called idle function is linked
742      into L1 instruction memory. (less latency)
743
744config SCHEDULE_L1
745    bool "Locate kernel schedule function in L1 Memory"
746    default y
747    help
748      If enabled, the frequently called kernel schedule is linked
749      into L1 instruction memory. (less latency)
750
751config ARITHMETIC_OPS_L1
752    bool "Locate kernel owned arithmetic functions in L1 Memory"
753    default y
754    help
755      If enabled, arithmetic functions are linked
756      into L1 instruction memory. (less latency)
757
758config ACCESS_OK_L1
759    bool "Locate access_ok function in L1 Memory"
760    default y
761    help
762      If enabled, the access_ok function is linked
763      into L1 instruction memory. (less latency)
764
765config MEMSET_L1
766    bool "Locate memset function in L1 Memory"
767    default y
768    help
769      If enabled, the memset function is linked
770      into L1 instruction memory. (less latency)
771
772config MEMCPY_L1
773    bool "Locate memcpy function in L1 Memory"
774    default y
775    help
776      If enabled, the memcpy function is linked
777      into L1 instruction memory. (less latency)
778
779config STRCMP_L1
780    bool "locate strcmp function in L1 Memory"
781    default y
782    help
783      If enabled, the strcmp function is linked
784      into L1 instruction memory (less latency).
785
786config STRNCMP_L1
787    bool "locate strncmp function in L1 Memory"
788    default y
789    help
790      If enabled, the strncmp function is linked
791      into L1 instruction memory (less latency).
792
793config STRCPY_L1
794    bool "locate strcpy function in L1 Memory"
795    default y
796    help
797      If enabled, the strcpy function is linked
798      into L1 instruction memory (less latency).
799
800config STRNCPY_L1
801    bool "locate strncpy function in L1 Memory"
802    default y
803    help
804      If enabled, the strncpy function is linked
805      into L1 instruction memory (less latency).
806
807config SYS_BFIN_SPINLOCK_L1
808    bool "Locate sys_bfin_spinlock function in L1 Memory"
809    default y
810    help
811      If enabled, sys_bfin_spinlock function is linked
812      into L1 instruction memory. (less latency)
813
814config IP_CHECKSUM_L1
815    bool "Locate IP Checksum function in L1 Memory"
816    default n
817    help
818      If enabled, the IP Checksum function is linked
819      into L1 instruction memory. (less latency)
820
821config CACHELINE_ALIGNED_L1
822    bool "Locate cacheline_aligned data to L1 Data Memory"
823    default y if !BF54x
824    default n if BF54x
825    depends on !BF531
826    help
827      If enabled, cacheline_aligned data is linked
828      into L1 data memory. (less latency)
829
830config SYSCALL_TAB_L1
831    bool "Locate Syscall Table L1 Data Memory"
832    default n
833    depends on !BF531
834    help
835      If enabled, the Syscall LUT is linked
836      into L1 data memory. (less latency)
837
838config CPLB_SWITCH_TAB_L1
839    bool "Locate CPLB Switch Tables L1 Data Memory"
840    default n
841    depends on !BF531
842    help
843      If enabled, the CPLB Switch Tables are linked
844      into L1 data memory. (less latency)
845
846config CACHE_FLUSH_L1
847    bool "Locate cache flush funcs in L1 Inst Memory"
848    default y
849    help
850      If enabled, the Blackfin cache flushing functions are linked
851      into L1 instruction memory.
852
853      Note that this might be required to address anomalies, but
854      these functions are pretty small, so it shouldn't be too bad.
855      If you are using a processor affected by an anomaly, the build
856      system will double check for you and prevent it.
857
858config APP_STACK_L1
859    bool "Support locating application stack in L1 Scratch Memory"
860    default y
861    help
862      If enabled the application stack can be located in L1
863      scratch memory (less latency).
864
865      Currently only works with FLAT binaries.
866
867config EXCEPTION_L1_SCRATCH
868    bool "Locate exception stack in L1 Scratch Memory"
869    default n
870    depends on !APP_STACK_L1
871    help
872      Whenever an exception occurs, use the L1 Scratch memory for
873      stack storage. You cannot place the stacks of FLAT binaries
874      in L1 when using this option.
875
876      If you don't use L1 Scratch, then you should say Y here.
877
878comment "Speed Optimizations"
879config BFIN_INS_LOWOVERHEAD
880    bool "ins[bwl] low overhead, higher interrupt latency"
881    default y
882    help
883      Reads on the Blackfin are speculative. In Blackfin terms, this means
884      they can be interrupted at any time (even after they have been issued
885      on to the external bus), and re-issued after the interrupt occurs.
886      For memory - this is not a big deal, since memory does not change if
887      it sees a read.
888
889      If a FIFO is sitting on the end of the read, it will see two reads,
890      when the core only sees one since the FIFO receives both the read
891      which is cancelled (and not delivered to the core) and the one which
892      is re-issued (which is delivered to the core).
893
894      To solve this, interrupts are turned off before reads occur to
895      I/O space. This option controls which the overhead/latency of
896      controlling interrupts during this time
897       "n" turns interrupts off every read
898        (higher overhead, but lower interrupt latency)
899       "y" turns interrupts off every loop
900        (low overhead, but longer interrupt latency)
901
902      default behavior is to leave this set to on (type "Y"). If you are experiencing
903      interrupt latency issues, it is safe and OK to turn this off.
904
905endmenu
906
907choice
908    prompt "Kernel executes from"
909    help
910      Choose the memory type that the kernel will be running in.
911
912config RAMKERNEL
913    bool "RAM"
914    help
915      The kernel will be resident in RAM when running.
916
917config ROMKERNEL
918    bool "ROM"
919    help
920      The kernel will be resident in FLASH/ROM when running.
921
922endchoice
923
924# Common code uses "ROMKERNEL" or "XIP_KERNEL", so define both
925config XIP_KERNEL
926    bool
927    default y
928    depends on ROMKERNEL
929
930source "mm/Kconfig"
931
932config BFIN_GPTIMERS
933    tristate "Enable Blackfin General Purpose Timers API"
934    default n
935    help
936      Enable support for the General Purpose Timers API. If you
937      are unsure, say N.
938
939      To compile this driver as a module, choose M here: the module
940      will be called gptimers.
941
942choice
943    prompt "Uncached DMA region"
944    default DMA_UNCACHED_1M
945config DMA_UNCACHED_4M
946    bool "Enable 4M DMA region"
947config DMA_UNCACHED_2M
948    bool "Enable 2M DMA region"
949config DMA_UNCACHED_1M
950    bool "Enable 1M DMA region"
951config DMA_UNCACHED_512K
952    bool "Enable 512K DMA region"
953config DMA_UNCACHED_256K
954    bool "Enable 256K DMA region"
955config DMA_UNCACHED_128K
956    bool "Enable 128K DMA region"
957config DMA_UNCACHED_NONE
958    bool "Disable DMA region"
959endchoice
960
961
962comment "Cache Support"
963
964config BFIN_ICACHE
965    bool "Enable ICACHE"
966    default y
967config BFIN_EXTMEM_ICACHEABLE
968    bool "Enable ICACHE for external memory"
969    depends on BFIN_ICACHE
970    default y
971config BFIN_L2_ICACHEABLE
972    bool "Enable ICACHE for L2 SRAM"
973    depends on BFIN_ICACHE
974    depends on BF54x || BF561
975    default n
976
977config BFIN_DCACHE
978    bool "Enable DCACHE"
979    default y
980config BFIN_DCACHE_BANKA
981    bool "Enable only 16k BankA DCACHE - BankB is SRAM"
982    depends on BFIN_DCACHE && !BF531
983    default n
984config BFIN_EXTMEM_DCACHEABLE
985    bool "Enable DCACHE for external memory"
986    depends on BFIN_DCACHE
987    default y
988choice
989    prompt "External memory DCACHE policy"
990    depends on BFIN_EXTMEM_DCACHEABLE
991    default BFIN_EXTMEM_WRITEBACK if !SMP
992    default BFIN_EXTMEM_WRITETHROUGH if SMP
993config BFIN_EXTMEM_WRITEBACK
994    bool "Write back"
995    depends on !SMP
996    help
997      Write Back Policy:
998        Cached data will be written back to SDRAM only when needed.
999        This can give a nice increase in performance, but beware of
1000        broken drivers that do not properly invalidate/flush their
1001        cache.
1002
1003      Write Through Policy:
1004        Cached data will always be written back to SDRAM when the
1005        cache is updated. This is a completely safe setting, but
1006        performance is worse than Write Back.
1007
1008      If you are unsure of the options and you want to be safe,
1009      then go with Write Through.
1010
1011config BFIN_EXTMEM_WRITETHROUGH
1012    bool "Write through"
1013    help
1014      Write Back Policy:
1015        Cached data will be written back to SDRAM only when needed.
1016        This can give a nice increase in performance, but beware of
1017        broken drivers that do not properly invalidate/flush their
1018        cache.
1019
1020      Write Through Policy:
1021        Cached data will always be written back to SDRAM when the
1022        cache is updated. This is a completely safe setting, but
1023        performance is worse than Write Back.
1024
1025      If you are unsure of the options and you want to be safe,
1026      then go with Write Through.
1027
1028endchoice
1029
1030config BFIN_L2_DCACHEABLE
1031    bool "Enable DCACHE for L2 SRAM"
1032    depends on BFIN_DCACHE
1033    depends on (BF54x || BF561) && !SMP
1034    default n
1035choice
1036    prompt "L2 SRAM DCACHE policy"
1037    depends on BFIN_L2_DCACHEABLE
1038    default BFIN_L2_WRITEBACK
1039config BFIN_L2_WRITEBACK
1040    bool "Write back"
1041
1042config BFIN_L2_WRITETHROUGH
1043    bool "Write through"
1044endchoice
1045
1046
1047comment "Memory Protection Unit"
1048config MPU
1049    bool "Enable the memory protection unit (EXPERIMENTAL)"
1050    default n
1051    help
1052      Use the processor's MPU to protect applications from accessing
1053      memory they do not own. This comes at a performance penalty
1054      and is recommended only for debugging.
1055
1056comment "Asynchronous Memory Configuration"
1057
1058menu "EBIU_AMGCTL Global Control"
1059config C_AMCKEN
1060    bool "Enable CLKOUT"
1061    default y
1062
1063config C_CDPRIO
1064    bool "DMA has priority over core for ext. accesses"
1065    default n
1066
1067config C_B0PEN
1068    depends on BF561
1069    bool "Bank 0 16 bit packing enable"
1070    default y
1071
1072config C_B1PEN
1073    depends on BF561
1074    bool "Bank 1 16 bit packing enable"
1075    default y
1076
1077config C_B2PEN
1078    depends on BF561
1079    bool "Bank 2 16 bit packing enable"
1080    default y
1081
1082config C_B3PEN
1083    depends on BF561
1084    bool "Bank 3 16 bit packing enable"
1085    default n
1086
1087choice
1088    prompt "Enable Asynchronous Memory Banks"
1089    default C_AMBEN_ALL
1090
1091config C_AMBEN
1092    bool "Disable All Banks"
1093
1094config C_AMBEN_B0
1095    bool "Enable Bank 0"
1096
1097config C_AMBEN_B0_B1
1098    bool "Enable Bank 0 & 1"
1099
1100config C_AMBEN_B0_B1_B2
1101    bool "Enable Bank 0 & 1 & 2"
1102
1103config C_AMBEN_ALL
1104    bool "Enable All Banks"
1105endchoice
1106endmenu
1107
1108menu "EBIU_AMBCTL Control"
1109config BANK_0
1110    hex "Bank 0 (AMBCTL0.L)"
1111    default 0x7BB0
1112    help
1113      These are the low 16 bits of the EBIU_AMBCTL0 MMR which are
1114      used to control the Asynchronous Memory Bank 0 settings.
1115
1116config BANK_1
1117    hex "Bank 1 (AMBCTL0.H)"
1118    default 0x7BB0
1119    default 0x5558 if BF54x
1120    help
1121      These are the high 16 bits of the EBIU_AMBCTL0 MMR which are
1122      used to control the Asynchronous Memory Bank 1 settings.
1123
1124config BANK_2
1125    hex "Bank 2 (AMBCTL1.L)"
1126    default 0x7BB0
1127    help
1128      These are the low 16 bits of the EBIU_AMBCTL1 MMR which are
1129      used to control the Asynchronous Memory Bank 2 settings.
1130
1131config BANK_3
1132    hex "Bank 3 (AMBCTL1.H)"
1133    default 0x99B3
1134    help
1135      These are the high 16 bits of the EBIU_AMBCTL1 MMR which are
1136      used to control the Asynchronous Memory Bank 3 settings.
1137
1138endmenu
1139
1140config EBIU_MBSCTLVAL
1141    hex "EBIU Bank Select Control Register"
1142    depends on BF54x
1143    default 0
1144
1145config EBIU_MODEVAL
1146    hex "Flash Memory Mode Control Register"
1147    depends on BF54x
1148    default 1
1149
1150config EBIU_FCTLVAL
1151    hex "Flash Memory Bank Control Register"
1152    depends on BF54x
1153    default 6
1154endmenu
1155
1156#############################################################################
1157menu "Bus options (PCI, PCMCIA, EISA, MCA, ISA)"
1158
1159config PCI
1160    bool "PCI support"
1161    depends on BROKEN
1162    help
1163      Support for PCI bus.
1164
1165source "drivers/pci/Kconfig"
1166
1167source "drivers/pcmcia/Kconfig"
1168
1169source "drivers/pci/hotplug/Kconfig"
1170
1171endmenu
1172
1173menu "Executable file formats"
1174
1175source "fs/Kconfig.binfmt"
1176
1177endmenu
1178
1179menu "Power management options"
1180
1181source "kernel/power/Kconfig"
1182
1183config ARCH_SUSPEND_POSSIBLE
1184    def_bool y
1185
1186choice
1187    prompt "Standby Power Saving Mode"
1188    depends on PM
1189    default PM_BFIN_SLEEP_DEEPER
1190config PM_BFIN_SLEEP_DEEPER
1191    bool "Sleep Deeper"
1192    help
1193      Sleep "Deeper" Mode (High Power Savings) - This mode reduces dynamic
1194      power dissipation by disabling the clock to the processor core (CCLK).
1195      Furthermore, Standby sets the internal power supply voltage (VDDINT)
1196      to 0.85 V to provide the greatest power savings, while preserving the
1197      processor state.
1198      The PLL and system clock (SCLK) continue to operate at a very low
1199      frequency of about 3.3 MHz. To preserve data integrity in the SDRAM,
1200      the SDRAM is put into Self Refresh Mode. Typically an external event
1201      such as GPIO interrupt or RTC activity wakes up the processor.
1202      Various Peripherals such as UART, SPORT, PPI may not function as
1203      normal during Sleep Deeper, due to the reduced SCLK frequency.
1204      When in the sleep mode, system DMA access to L1 memory is not supported.
1205
1206      If unsure, select "Sleep Deeper".
1207
1208config PM_BFIN_SLEEP
1209    bool "Sleep"
1210    help
1211      Sleep Mode (High Power Savings) - The sleep mode reduces power
1212      dissipation by disabling the clock to the processor core (CCLK).
1213      The PLL and system clock (SCLK), however, continue to operate in
1214      this mode. Typically an external event or RTC activity will wake
1215      up the processor. When in the sleep mode, system DMA access to L1
1216      memory is not supported.
1217
1218      If unsure, select "Sleep Deeper".
1219endchoice
1220
1221comment "Possible Suspend Mem / Hibernate Wake-Up Sources"
1222    depends on PM
1223
1224config PM_BFIN_WAKE_PH6
1225    bool "Allow Wake-Up from on-chip PHY or PH6 GP"
1226    depends on PM && (BF51x || BF52x || BF534 || BF536 || BF537)
1227    default n
1228    help
1229      Enable PHY and PH6 GP Wake-Up (Voltage Regulator Power-Up)
1230
1231config PM_BFIN_WAKE_GP
1232    bool "Allow Wake-Up from GPIOs"
1233    depends on PM && BF54x
1234    default n
1235    help
1236      Enable General-Purpose Wake-Up (Voltage Regulator Power-Up)
1237      (all processors, except ADSP-BF549). This option sets
1238      the general-purpose wake-up enable (GPWE) control bit to enable
1239      wake-up upon detection of an active low signal on the /GPW (PH7) pin.
1240      On ADSP-BF549 this option enables the the same functionality on the
1241      /MRXON pin also PH7.
1242
1243endmenu
1244
1245menu "CPU Frequency scaling"
1246
1247source "drivers/cpufreq/Kconfig"
1248
1249config BFIN_CPU_FREQ
1250    bool
1251    depends on CPU_FREQ
1252    select CPU_FREQ_TABLE
1253    default y
1254
1255config CPU_VOLTAGE
1256    bool "CPU Voltage scaling"
1257    depends on EXPERIMENTAL
1258    depends on CPU_FREQ
1259    default n
1260    help
1261      Say Y here if you want CPU voltage scaling according to the CPU frequency.
1262      This option violates the PLL BYPASS recommendation in the Blackfin Processor
1263      manuals. There is a theoretical risk that during VDDINT transitions
1264      the PLL may unlock.
1265
1266endmenu
1267
1268source "net/Kconfig"
1269
1270source "drivers/Kconfig"
1271
1272source "drivers/firmware/Kconfig"
1273
1274source "fs/Kconfig"
1275
1276source "arch/blackfin/Kconfig.debug"
1277
1278source "security/Kconfig"
1279
1280source "crypto/Kconfig"
1281
1282source "lib/Kconfig"
1283

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