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1 | /* sun4d_smp.c: Sparc SS1000/SC2000 SMP support. |
2 | * |
3 | * Copyright (C) 1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz) |
4 | * |
5 | * Based on sun4m's smp.c, which is: |
6 | * Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu) |
7 | */ |
8 | |
9 | #include <asm/head.h> |
10 | |
11 | #include <linux/kernel.h> |
12 | #include <linux/sched.h> |
13 | #include <linux/threads.h> |
14 | #include <linux/smp.h> |
15 | #include <linux/interrupt.h> |
16 | #include <linux/kernel_stat.h> |
17 | #include <linux/init.h> |
18 | #include <linux/spinlock.h> |
19 | #include <linux/mm.h> |
20 | #include <linux/swap.h> |
21 | #include <linux/profile.h> |
22 | #include <linux/delay.h> |
23 | #include <linux/cpu.h> |
24 | |
25 | #include <asm/ptrace.h> |
26 | #include <asm/atomic.h> |
27 | #include <asm/irq_regs.h> |
28 | |
29 | #include <asm/irq.h> |
30 | #include <asm/page.h> |
31 | #include <asm/pgalloc.h> |
32 | #include <asm/pgtable.h> |
33 | #include <asm/oplib.h> |
34 | #include <asm/sbi.h> |
35 | #include <asm/tlbflush.h> |
36 | #include <asm/cacheflush.h> |
37 | #include <asm/cpudata.h> |
38 | |
39 | #include "irq.h" |
40 | #define IRQ_CROSS_CALL 15 |
41 | |
42 | extern ctxd_t *srmmu_ctx_table_phys; |
43 | |
44 | static volatile int smp_processors_ready = 0; |
45 | static int smp_highest_cpu; |
46 | extern volatile unsigned long cpu_callin_map[NR_CPUS]; |
47 | extern cpuinfo_sparc cpu_data[NR_CPUS]; |
48 | extern unsigned char boot_cpu_id; |
49 | extern volatile int smp_process_available; |
50 | |
51 | extern cpumask_t smp_commenced_mask; |
52 | |
53 | extern int __smp4d_processor_id(void); |
54 | |
55 | /* #define SMP_DEBUG */ |
56 | |
57 | #ifdef SMP_DEBUG |
58 | #define SMP_PRINTK(x) printk x |
59 | #else |
60 | #define SMP_PRINTK(x) |
61 | #endif |
62 | |
63 | static inline unsigned long sun4d_swap(volatile unsigned long *ptr, unsigned long val) |
64 | { |
65 | __asm__ __volatile__("swap [%1], %0\n\t" : |
66 | "=&r" (val), "=&r" (ptr) : |
67 | "0" (val), "1" (ptr)); |
68 | return val; |
69 | } |
70 | |
71 | static void smp_setup_percpu_timer(void); |
72 | extern void cpu_probe(void); |
73 | extern void sun4d_distribute_irqs(void); |
74 | |
75 | static unsigned char cpu_leds[32]; |
76 | |
77 | static inline void show_leds(int cpuid) |
78 | { |
79 | cpuid &= 0x1e; |
80 | __asm__ __volatile__ ("stba %0, [%1] %2" : : |
81 | "r" ((cpu_leds[cpuid] << 4) | cpu_leds[cpuid+1]), |
82 | "r" (ECSR_BASE(cpuid) | BB_LEDS), |
83 | "i" (ASI_M_CTL)); |
84 | } |
85 | |
86 | void __cpuinit smp4d_callin(void) |
87 | { |
88 | int cpuid = hard_smp4d_processor_id(); |
89 | extern spinlock_t sun4d_imsk_lock; |
90 | unsigned long flags; |
91 | |
92 | /* Show we are alive */ |
93 | cpu_leds[cpuid] = 0x6; |
94 | show_leds(cpuid); |
95 | |
96 | /* Enable level15 interrupt, disable level14 interrupt for now */ |
97 | cc_set_imsk((cc_get_imsk() & ~0x8000) | 0x4000); |
98 | |
99 | local_flush_cache_all(); |
100 | local_flush_tlb_all(); |
101 | |
102 | notify_cpu_starting(cpuid); |
103 | /* |
104 | * Unblock the master CPU _only_ when the scheduler state |
105 | * of all secondary CPUs will be up-to-date, so after |
106 | * the SMP initialization the master will be just allowed |
107 | * to call the scheduler code. |
108 | */ |
109 | /* Get our local ticker going. */ |
110 | smp_setup_percpu_timer(); |
111 | |
112 | calibrate_delay(); |
113 | smp_store_cpu_info(cpuid); |
114 | local_flush_cache_all(); |
115 | local_flush_tlb_all(); |
116 | |
117 | /* Allow master to continue. */ |
118 | sun4d_swap((unsigned long *)&cpu_callin_map[cpuid], 1); |
119 | local_flush_cache_all(); |
120 | local_flush_tlb_all(); |
121 | |
122 | cpu_probe(); |
123 | |
124 | while((unsigned long)current_set[cpuid] < PAGE_OFFSET) |
125 | barrier(); |
126 | |
127 | while(current_set[cpuid]->cpu != cpuid) |
128 | barrier(); |
129 | |
130 | /* Fix idle thread fields. */ |
131 | __asm__ __volatile__("ld [%0], %%g6\n\t" |
132 | : : "r" (¤t_set[cpuid]) |
133 | : "memory" /* paranoid */); |
134 | |
135 | cpu_leds[cpuid] = 0x9; |
136 | show_leds(cpuid); |
137 | |
138 | /* Attach to the address space of init_task. */ |
139 | atomic_inc(&init_mm.mm_count); |
140 | current->active_mm = &init_mm; |
141 | |
142 | local_flush_cache_all(); |
143 | local_flush_tlb_all(); |
144 | |
145 | local_irq_enable(); /* We don't allow PIL 14 yet */ |
146 | |
147 | while (!cpu_isset(cpuid, smp_commenced_mask)) |
148 | barrier(); |
149 | |
150 | spin_lock_irqsave(&sun4d_imsk_lock, flags); |
151 | cc_set_imsk(cc_get_imsk() & ~0x4000); /* Allow PIL 14 as well */ |
152 | spin_unlock_irqrestore(&sun4d_imsk_lock, flags); |
153 | set_cpu_online(cpuid, true); |
154 | |
155 | } |
156 | |
157 | extern void init_IRQ(void); |
158 | extern void cpu_panic(void); |
159 | |
160 | /* |
161 | * Cycle through the processors asking the PROM to start each one. |
162 | */ |
163 | |
164 | extern struct linux_prom_registers smp_penguin_ctable; |
165 | |
166 | void __init smp4d_boot_cpus(void) |
167 | { |
168 | if (boot_cpu_id) |
169 | current_set[0] = NULL; |
170 | smp_setup_percpu_timer(); |
171 | local_flush_cache_all(); |
172 | } |
173 | |
174 | int __cpuinit smp4d_boot_one_cpu(int i) |
175 | { |
176 | extern unsigned long sun4d_cpu_startup; |
177 | unsigned long *entry = &sun4d_cpu_startup; |
178 | struct task_struct *p; |
179 | int timeout; |
180 | int cpu_node; |
181 | |
182 | cpu_find_by_instance(i, &cpu_node,NULL); |
183 | /* Cook up an idler for this guy. */ |
184 | p = fork_idle(i); |
185 | current_set[i] = task_thread_info(p); |
186 | |
187 | /* |
188 | * Initialize the contexts table |
189 | * Since the call to prom_startcpu() trashes the structure, |
190 | * we need to re-initialize it for each cpu |
191 | */ |
192 | smp_penguin_ctable.which_io = 0; |
193 | smp_penguin_ctable.phys_addr = (unsigned int) srmmu_ctx_table_phys; |
194 | smp_penguin_ctable.reg_size = 0; |
195 | |
196 | /* whirrr, whirrr, whirrrrrrrrr... */ |
197 | SMP_PRINTK(("Starting CPU %d at %p\n", i, entry)); |
198 | local_flush_cache_all(); |
199 | prom_startcpu(cpu_node, |
200 | &smp_penguin_ctable, 0, (char *)entry); |
201 | |
202 | SMP_PRINTK(("prom_startcpu returned :)\n")); |
203 | |
204 | /* wheee... it's going... */ |
205 | for(timeout = 0; timeout < 10000; timeout++) { |
206 | if(cpu_callin_map[i]) |
207 | break; |
208 | udelay(200); |
209 | } |
210 | |
211 | if (!(cpu_callin_map[i])) { |
212 | printk("Processor %d is stuck.\n", i); |
213 | return -ENODEV; |
214 | |
215 | } |
216 | local_flush_cache_all(); |
217 | return 0; |
218 | } |
219 | |
220 | void __init smp4d_smp_done(void) |
221 | { |
222 | int i, first; |
223 | int *prev; |
224 | |
225 | /* setup cpu list for irq rotation */ |
226 | first = 0; |
227 | prev = &first; |
228 | for_each_online_cpu(i) { |
229 | *prev = i; |
230 | prev = &cpu_data(i).next; |
231 | } |
232 | *prev = first; |
233 | local_flush_cache_all(); |
234 | |
235 | /* Ok, they are spinning and ready to go. */ |
236 | smp_processors_ready = 1; |
237 | sun4d_distribute_irqs(); |
238 | } |
239 | |
240 | static struct smp_funcall { |
241 | smpfunc_t func; |
242 | unsigned long arg1; |
243 | unsigned long arg2; |
244 | unsigned long arg3; |
245 | unsigned long arg4; |
246 | unsigned long arg5; |
247 | unsigned char processors_in[NR_CPUS]; /* Set when ipi entered. */ |
248 | unsigned char processors_out[NR_CPUS]; /* Set when ipi exited. */ |
249 | } ccall_info __attribute__((aligned(8))); |
250 | |
251 | static DEFINE_SPINLOCK(cross_call_lock); |
252 | |
253 | /* Cross calls must be serialized, at least currently. */ |
254 | static void smp4d_cross_call(smpfunc_t func, cpumask_t mask, unsigned long arg1, |
255 | unsigned long arg2, unsigned long arg3, |
256 | unsigned long arg4) |
257 | { |
258 | if(smp_processors_ready) { |
259 | register int high = smp_highest_cpu; |
260 | unsigned long flags; |
261 | |
262 | spin_lock_irqsave(&cross_call_lock, flags); |
263 | |
264 | { |
265 | /* If you make changes here, make sure gcc generates proper code... */ |
266 | register smpfunc_t f asm("i0") = func; |
267 | register unsigned long a1 asm("i1") = arg1; |
268 | register unsigned long a2 asm("i2") = arg2; |
269 | register unsigned long a3 asm("i3") = arg3; |
270 | register unsigned long a4 asm("i4") = arg4; |
271 | register unsigned long a5 asm("i5") = 0; |
272 | |
273 | __asm__ __volatile__( |
274 | "std %0, [%6]\n\t" |
275 | "std %2, [%6 + 8]\n\t" |
276 | "std %4, [%6 + 16]\n\t" : : |
277 | "r"(f), "r"(a1), "r"(a2), "r"(a3), "r"(a4), "r"(a5), |
278 | "r" (&ccall_info.func)); |
279 | } |
280 | |
281 | /* Init receive/complete mapping, plus fire the IPI's off. */ |
282 | { |
283 | register int i; |
284 | |
285 | cpu_clear(smp_processor_id(), mask); |
286 | cpus_and(mask, cpu_online_map, mask); |
287 | for(i = 0; i <= high; i++) { |
288 | if (cpu_isset(i, mask)) { |
289 | ccall_info.processors_in[i] = 0; |
290 | ccall_info.processors_out[i] = 0; |
291 | sun4d_send_ipi(i, IRQ_CROSS_CALL); |
292 | } |
293 | } |
294 | } |
295 | |
296 | { |
297 | register int i; |
298 | |
299 | i = 0; |
300 | do { |
301 | if (!cpu_isset(i, mask)) |
302 | continue; |
303 | while(!ccall_info.processors_in[i]) |
304 | barrier(); |
305 | } while(++i <= high); |
306 | |
307 | i = 0; |
308 | do { |
309 | if (!cpu_isset(i, mask)) |
310 | continue; |
311 | while(!ccall_info.processors_out[i]) |
312 | barrier(); |
313 | } while(++i <= high); |
314 | } |
315 | |
316 | spin_unlock_irqrestore(&cross_call_lock, flags); |
317 | } |
318 | } |
319 | |
320 | /* Running cross calls. */ |
321 | void smp4d_cross_call_irq(void) |
322 | { |
323 | int i = hard_smp4d_processor_id(); |
324 | |
325 | ccall_info.processors_in[i] = 1; |
326 | ccall_info.func(ccall_info.arg1, ccall_info.arg2, ccall_info.arg3, |
327 | ccall_info.arg4, ccall_info.arg5); |
328 | ccall_info.processors_out[i] = 1; |
329 | } |
330 | |
331 | void smp4d_percpu_timer_interrupt(struct pt_regs *regs) |
332 | { |
333 | struct pt_regs *old_regs; |
334 | int cpu = hard_smp4d_processor_id(); |
335 | static int cpu_tick[NR_CPUS]; |
336 | static char led_mask[] = { 0xe, 0xd, 0xb, 0x7, 0xb, 0xd }; |
337 | |
338 | old_regs = set_irq_regs(regs); |
339 | bw_get_prof_limit(cpu); |
340 | bw_clear_intr_mask(0, 1); /* INTR_TABLE[0] & 1 is Profile IRQ */ |
341 | |
342 | cpu_tick[cpu]++; |
343 | if (!(cpu_tick[cpu] & 15)) { |
344 | if (cpu_tick[cpu] == 0x60) |
345 | cpu_tick[cpu] = 0; |
346 | cpu_leds[cpu] = led_mask[cpu_tick[cpu] >> 4]; |
347 | show_leds(cpu); |
348 | } |
349 | |
350 | profile_tick(CPU_PROFILING); |
351 | |
352 | if(!--prof_counter(cpu)) { |
353 | int user = user_mode(regs); |
354 | |
355 | irq_enter(); |
356 | update_process_times(user); |
357 | irq_exit(); |
358 | |
359 | prof_counter(cpu) = prof_multiplier(cpu); |
360 | } |
361 | set_irq_regs(old_regs); |
362 | } |
363 | |
364 | extern unsigned int lvl14_resolution; |
365 | |
366 | static void __cpuinit smp_setup_percpu_timer(void) |
367 | { |
368 | int cpu = hard_smp4d_processor_id(); |
369 | |
370 | prof_counter(cpu) = prof_multiplier(cpu) = 1; |
371 | load_profile_irq(cpu, lvl14_resolution); |
372 | } |
373 | |
374 | void __init smp4d_blackbox_id(unsigned *addr) |
375 | { |
376 | int rd = *addr & 0x3e000000; |
377 | |
378 | addr[0] = 0xc0800800 | rd; /* lda [%g0] ASI_M_VIKING_TMP1, reg */ |
379 | addr[1] = 0x01000000; /* nop */ |
380 | addr[2] = 0x01000000; /* nop */ |
381 | } |
382 | |
383 | void __init smp4d_blackbox_current(unsigned *addr) |
384 | { |
385 | int rd = *addr & 0x3e000000; |
386 | |
387 | addr[0] = 0xc0800800 | rd; /* lda [%g0] ASI_M_VIKING_TMP1, reg */ |
388 | addr[2] = 0x81282002 | rd | (rd >> 11); /* sll reg, 2, reg */ |
389 | addr[4] = 0x01000000; /* nop */ |
390 | } |
391 | |
392 | void __init sun4d_init_smp(void) |
393 | { |
394 | int i; |
395 | extern unsigned int t_nmi[], linux_trap_ipi15_sun4d[], linux_trap_ipi15_sun4m[]; |
396 | |
397 | /* Patch ipi15 trap table */ |
398 | t_nmi[1] = t_nmi[1] + (linux_trap_ipi15_sun4d - linux_trap_ipi15_sun4m); |
399 | |
400 | /* And set btfixup... */ |
401 | BTFIXUPSET_BLACKBOX(hard_smp_processor_id, smp4d_blackbox_id); |
402 | BTFIXUPSET_BLACKBOX(load_current, smp4d_blackbox_current); |
403 | BTFIXUPSET_CALL(smp_cross_call, smp4d_cross_call, BTFIXUPCALL_NORM); |
404 | BTFIXUPSET_CALL(__hard_smp_processor_id, __smp4d_processor_id, BTFIXUPCALL_NORM); |
405 | |
406 | for (i = 0; i < NR_CPUS; i++) { |
407 | ccall_info.processors_in[i] = 1; |
408 | ccall_info.processors_out[i] = 1; |
409 | } |
410 | } |
411 |
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