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1 | #ifndef _SERIAL_MFD_H_ |
2 | #define _SERIAL_MFD_H_ |
3 | |
4 | /* HW register offset definition */ |
5 | #define UART_FOR 0x08 |
6 | #define UART_PS 0x0C |
7 | #define UART_MUL 0x0D |
8 | #define UART_DIV 0x0E |
9 | |
10 | #define HSU_GBL_IEN 0x0 |
11 | #define HSU_GBL_IST 0x4 |
12 | |
13 | #define HSU_GBL_INT_BIT_PORT0 0x0 |
14 | #define HSU_GBL_INT_BIT_PORT1 0x1 |
15 | #define HSU_GBL_INT_BIT_PORT2 0x2 |
16 | #define HSU_GBL_INT_BIT_IRI 0x3 |
17 | #define HSU_GBL_INT_BIT_HDLC 0x4 |
18 | #define HSU_GBL_INT_BIT_DMA 0x5 |
19 | |
20 | #define HSU_GBL_ISR 0x8 |
21 | #define HSU_GBL_DMASR 0x400 |
22 | #define HSU_GBL_DMAISR 0x404 |
23 | |
24 | #define HSU_PORT_REG_OFFSET 0x80 |
25 | #define HSU_PORT0_REG_OFFSET 0x80 |
26 | #define HSU_PORT1_REG_OFFSET 0x100 |
27 | #define HSU_PORT2_REG_OFFSET 0x180 |
28 | #define HSU_PORT_REG_LENGTH 0x80 |
29 | |
30 | #define HSU_DMA_CHANS_REG_OFFSET 0x500 |
31 | #define HSU_DMA_CHANS_REG_LENGTH 0x40 |
32 | |
33 | #define HSU_CH_SR 0x0 /* channel status reg */ |
34 | #define HSU_CH_CR 0x4 /* control reg */ |
35 | #define HSU_CH_DCR 0x8 /* descriptor control reg */ |
36 | #define HSU_CH_BSR 0x10 /* max fifo buffer size reg */ |
37 | #define HSU_CH_MOTSR 0x14 /* minimum ocp transfer size */ |
38 | #define HSU_CH_D0SAR 0x20 /* desc 0 start addr */ |
39 | #define HSU_CH_D0TSR 0x24 /* desc 0 transfer size */ |
40 | #define HSU_CH_D1SAR 0x28 |
41 | #define HSU_CH_D1TSR 0x2C |
42 | #define HSU_CH_D2SAR 0x30 |
43 | #define HSU_CH_D2TSR 0x34 |
44 | #define HSU_CH_D3SAR 0x38 |
45 | #define HSU_CH_D3TSR 0x3C |
46 | |
47 | #endif |
48 |
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javiroman/ks7010
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Tags:
od-2011-09-04
od-2011-09-18
v2.6.34-rc5
v2.6.34-rc6
v2.6.34-rc7
v3.9