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1 | /* |
2 | * Driver for PowerMac AWACS onboard soundchips |
3 | * Copyright (c) 2001 by Takashi Iwai <tiwai@suse.de> |
4 | * based on dmasound.c. |
5 | * |
6 | * This program is free software; you can redistribute it and/or modify |
7 | * it under the terms of the GNU General Public License as published by |
8 | * the Free Software Foundation; either version 2 of the License, or |
9 | * (at your option) any later version. |
10 | * |
11 | * This program is distributed in the hope that it will be useful, |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
14 | * GNU General Public License for more details. |
15 | * |
16 | * You should have received a copy of the GNU General Public License |
17 | * along with this program; if not, write to the Free Software |
18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
19 | */ |
20 | |
21 | |
22 | #ifndef __AWACS_H |
23 | #define __AWACS_H |
24 | |
25 | /*******************************/ |
26 | /* AWACs Audio Register Layout */ |
27 | /*******************************/ |
28 | |
29 | struct awacs_regs { |
30 | unsigned control; /* Audio control register */ |
31 | unsigned pad0[3]; |
32 | unsigned codec_ctrl; /* Codec control register */ |
33 | unsigned pad1[3]; |
34 | unsigned codec_stat; /* Codec status register */ |
35 | unsigned pad2[3]; |
36 | unsigned clip_count; /* Clipping count register */ |
37 | unsigned pad3[3]; |
38 | unsigned byteswap; /* Data is little-endian if 1 */ |
39 | }; |
40 | |
41 | /*******************/ |
42 | /* Audio Bit Masks */ |
43 | /*******************/ |
44 | |
45 | /* Audio Control Reg Bit Masks */ |
46 | /* ----- ------- --- --- ----- */ |
47 | #define MASK_ISFSEL (0xf) /* Input SubFrame Select */ |
48 | #define MASK_OSFSEL (0xf << 4) /* Output SubFrame Select */ |
49 | #define MASK_RATE (0x7 << 8) /* Sound Rate */ |
50 | #define MASK_CNTLERR (0x1 << 11) /* Error */ |
51 | #define MASK_PORTCHG (0x1 << 12) /* Port Change */ |
52 | #define MASK_IEE (0x1 << 13) /* Enable Interrupt on Error */ |
53 | #define MASK_IEPC (0x1 << 14) /* Enable Interrupt on Port Change */ |
54 | #define MASK_SSFSEL (0x3 << 15) /* Status SubFrame Select */ |
55 | |
56 | /* Audio Codec Control Reg Bit Masks */ |
57 | /* ----- ----- ------- --- --- ----- */ |
58 | #define MASK_NEWECMD (0x1 << 24) /* Lock: don't write to reg when 1 */ |
59 | #define MASK_EMODESEL (0x3 << 22) /* Send info out on which frame? */ |
60 | #define MASK_EXMODEADDR (0x3ff << 12) /* Extended Mode Address -- 10 bits */ |
61 | #define MASK_EXMODEDATA (0xfff) /* Extended Mode Data -- 12 bits */ |
62 | |
63 | /* Audio Codec Control Address Values / Masks */ |
64 | /* ----- ----- ------- ------- ------ - ----- */ |
65 | #define MASK_ADDR0 (0x0 << 12) /* Expanded Data Mode Address 0 */ |
66 | #define MASK_ADDR_MUX MASK_ADDR0 /* Mux Control */ |
67 | #define MASK_ADDR_GAIN MASK_ADDR0 |
68 | |
69 | #define MASK_ADDR1 (0x1 << 12) /* Expanded Data Mode Address 1 */ |
70 | #define MASK_ADDR_MUTE MASK_ADDR1 |
71 | #define MASK_ADDR_RATE MASK_ADDR1 |
72 | |
73 | #define MASK_ADDR2 (0x2 << 12) /* Expanded Data Mode Address 2 */ |
74 | #define MASK_ADDR_VOLA MASK_ADDR2 /* Volume Control A -- Headphones */ |
75 | #define MASK_ADDR_VOLHD MASK_ADDR2 |
76 | |
77 | #define MASK_ADDR4 (0x4 << 12) /* Expanded Data Mode Address 4 */ |
78 | #define MASK_ADDR_VOLC MASK_ADDR4 /* Volume Control C -- Speaker */ |
79 | #define MASK_ADDR_VOLSPK MASK_ADDR4 |
80 | |
81 | /* additional registers of screamer */ |
82 | #define MASK_ADDR5 (0x5 << 12) /* Expanded Data Mode Address 5 */ |
83 | #define MASK_ADDR6 (0x6 << 12) /* Expanded Data Mode Address 6 */ |
84 | #define MASK_ADDR7 (0x7 << 12) /* Expanded Data Mode Address 7 */ |
85 | |
86 | /* Address 0 Bit Masks & Macros */ |
87 | /* ------- - --- ----- - ------ */ |
88 | #define MASK_GAINRIGHT (0xf) /* Gain Right Mask */ |
89 | #define MASK_GAINLEFT (0xf << 4) /* Gain Left Mask */ |
90 | #define MASK_GAINLINE (0x1 << 8) /* Disable Mic preamp */ |
91 | #define MASK_GAINMIC (0x0 << 8) /* Enable Mic preamp */ |
92 | #define MASK_MUX_CD (0x1 << 9) /* Select CD in MUX */ |
93 | #define MASK_MUX_MIC (0x1 << 10) /* Select Mic in MUX */ |
94 | #define MASK_MUX_AUDIN (0x1 << 11) /* Select Audio In in MUX */ |
95 | #define MASK_MUX_LINE MASK_MUX_AUDIN |
96 | #define SHIFT_GAINLINE 8 |
97 | #define SHIFT_MUX_CD 9 |
98 | #define SHIFT_MUX_MIC 10 |
99 | #define SHIFT_MUX_LINE 11 |
100 | |
101 | #define GAINRIGHT(x) ((x) & MASK_GAINRIGHT) |
102 | #define GAINLEFT(x) (((x) << 4) & MASK_GAINLEFT) |
103 | |
104 | /* Address 1 Bit Masks */ |
105 | /* ------- - --- ----- */ |
106 | #define MASK_ADDR1RES1 (0x3) /* Reserved */ |
107 | #define MASK_RECALIBRATE (0x1 << 2) /* Recalibrate */ |
108 | #define MASK_SAMPLERATE (0x7 << 3) /* Sample Rate: */ |
109 | #define MASK_LOOPTHRU (0x1 << 6) /* Loopthrough Enable */ |
110 | #define SHIFT_LOOPTHRU 6 |
111 | #define MASK_CMUTE (0x1 << 7) /* Output C (Speaker) Mute when 1 */ |
112 | #define MASK_SPKMUTE MASK_CMUTE |
113 | #define SHIFT_SPKMUTE 7 |
114 | #define MASK_ADDR1RES2 (0x1 << 8) /* Reserved */ |
115 | #define MASK_AMUTE (0x1 << 9) /* Output A (Headphone) Mute when 1 */ |
116 | #define MASK_HDMUTE MASK_AMUTE |
117 | #define SHIFT_HDMUTE 9 |
118 | #define MASK_PAROUT (0x3 << 10) /* Parallel Out (???) */ |
119 | #define MASK_PAROUT0 (0x1 << 10) /* Parallel Out (???) */ |
120 | #define MASK_PAROUT1 (0x1 << 11) /* Parallel Out (enable speaker) */ |
121 | #define SHIFT_PAROUT 10 |
122 | #define SHIFT_PAROUT0 10 |
123 | #define SHIFT_PAROUT1 11 |
124 | |
125 | #define SAMPLERATE_48000 (0x0 << 3) /* 48 or 44.1 kHz */ |
126 | #define SAMPLERATE_32000 (0x1 << 3) /* 32 or 29.4 kHz */ |
127 | #define SAMPLERATE_24000 (0x2 << 3) /* 24 or 22.05 kHz */ |
128 | #define SAMPLERATE_19200 (0x3 << 3) /* 19.2 or 17.64 kHz */ |
129 | #define SAMPLERATE_16000 (0x4 << 3) /* 16 or 14.7 kHz */ |
130 | #define SAMPLERATE_12000 (0x5 << 3) /* 12 or 11.025 kHz */ |
131 | #define SAMPLERATE_9600 (0x6 << 3) /* 9.6 or 8.82 kHz */ |
132 | #define SAMPLERATE_8000 (0x7 << 3) /* 8 or 7.35 kHz */ |
133 | |
134 | /* Address 2 & 4 Bit Masks & Macros */ |
135 | /* ------- - - - --- ----- - ------ */ |
136 | #define MASK_OUTVOLRIGHT (0xf) /* Output Right Volume */ |
137 | #define MASK_ADDR2RES1 (0x2 << 4) /* Reserved */ |
138 | #define MASK_ADDR4RES1 MASK_ADDR2RES1 |
139 | #define MASK_OUTVOLLEFT (0xf << 6) /* Output Left Volume */ |
140 | #define MASK_ADDR2RES2 (0x2 << 10) /* Reserved */ |
141 | #define MASK_ADDR4RES2 MASK_ADDR2RES2 |
142 | |
143 | #define VOLRIGHT(x) (((~(x)) & MASK_OUTVOLRIGHT)) |
144 | #define VOLLEFT(x) (((~(x)) << 6) & MASK_OUTVOLLEFT) |
145 | |
146 | /* address 6 */ |
147 | #define MASK_MIC_BOOST (0x4) /* screamer mic boost */ |
148 | #define SHIFT_MIC_BOOST 2 |
149 | |
150 | /* Audio Codec Status Reg Bit Masks */ |
151 | /* ----- ----- ------ --- --- ----- */ |
152 | #define MASK_EXTEND (0x1 << 23) /* Extend */ |
153 | #define MASK_VALID (0x1 << 22) /* Valid Data? */ |
154 | #define MASK_OFLEFT (0x1 << 21) /* Overflow Left */ |
155 | #define MASK_OFRIGHT (0x1 << 20) /* Overflow Right */ |
156 | #define MASK_ERRCODE (0xf << 16) /* Error Code */ |
157 | #define MASK_REVISION (0xf << 12) /* Revision Number */ |
158 | #define MASK_MFGID (0xf << 8) /* Mfg. ID */ |
159 | #define MASK_CODSTATRES (0xf << 4) /* bits 4 - 7 reserved */ |
160 | #define MASK_INSENSE (0xf) /* port sense bits: */ |
161 | #define MASK_HDPCONN 8 /* headphone plugged in */ |
162 | #define MASK_LOCONN 4 /* line-out plugged in */ |
163 | #define MASK_LICONN 2 /* line-in plugged in */ |
164 | #define MASK_MICCONN 1 /* microphone plugged in */ |
165 | #define MASK_LICONN_IMAC 8 /* line-in plugged in */ |
166 | #define MASK_HDPRCONN_IMAC 4 /* headphone right plugged in */ |
167 | #define MASK_HDPLCONN_IMAC 2 /* headphone left plugged in */ |
168 | #define MASK_LOCONN_IMAC 1 /* line-out plugged in */ |
169 | |
170 | /* Clipping Count Reg Bit Masks */ |
171 | /* -------- ----- --- --- ----- */ |
172 | #define MASK_CLIPLEFT (0xff << 7) /* Clipping Count, Left Channel */ |
173 | #define MASK_CLIPRIGHT (0xff) /* Clipping Count, Right Channel */ |
174 | |
175 | /* DBDMA ChannelStatus Bit Masks */ |
176 | /* ----- ------------- --- ----- */ |
177 | #define MASK_CSERR (0x1 << 7) /* Error */ |
178 | #define MASK_EOI (0x1 << 6) /* End of Input -- |
179 | only for Input Channel */ |
180 | #define MASK_CSUNUSED (0x1f << 1) /* bits 1-5 not used */ |
181 | #define MASK_WAIT (0x1) /* Wait */ |
182 | |
183 | /* Various Rates */ |
184 | /* ------- ----- */ |
185 | #define RATE_48000 (0x0 << 8) /* 48 kHz */ |
186 | #define RATE_44100 (0x0 << 8) /* 44.1 kHz */ |
187 | #define RATE_32000 (0x1 << 8) /* 32 kHz */ |
188 | #define RATE_29400 (0x1 << 8) /* 29.4 kHz */ |
189 | #define RATE_24000 (0x2 << 8) /* 24 kHz */ |
190 | #define RATE_22050 (0x2 << 8) /* 22.05 kHz */ |
191 | #define RATE_19200 (0x3 << 8) /* 19.2 kHz */ |
192 | #define RATE_17640 (0x3 << 8) /* 17.64 kHz */ |
193 | #define RATE_16000 (0x4 << 8) /* 16 kHz */ |
194 | #define RATE_14700 (0x4 << 8) /* 14.7 kHz */ |
195 | #define RATE_12000 (0x5 << 8) /* 12 kHz */ |
196 | #define RATE_11025 (0x5 << 8) /* 11.025 kHz */ |
197 | #define RATE_9600 (0x6 << 8) /* 9.6 kHz */ |
198 | #define RATE_8820 (0x6 << 8) /* 8.82 kHz */ |
199 | #define RATE_8000 (0x7 << 8) /* 8 kHz */ |
200 | #define RATE_7350 (0x7 << 8) /* 7.35 kHz */ |
201 | |
202 | #define RATE_LOW 1 /* HIGH = 48kHz, etc; LOW = 44.1kHz, etc. */ |
203 | |
204 | |
205 | #endif /* __AWACS_H */ |
206 |
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