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1 | PXA2xx SPI on SSP driver HOWTO |
2 | =================================================== |
3 | This a mini howto on the pxa2xx_spi driver. The driver turns a PXA2xx |
4 | synchronous serial port into a SPI master controller |
5 | (see Documentation/spi/spi_summary). The driver has the following features |
6 | |
7 | - Support for any PXA2xx SSP |
8 | - SSP PIO and SSP DMA data transfers. |
9 | - External and Internal (SSPFRM) chip selects. |
10 | - Per slave device (chip) configuration. |
11 | - Full suspend, freeze, resume support. |
12 | |
13 | The driver is built around a "spi_message" fifo serviced by workqueue and a |
14 | tasklet. The workqueue, "pump_messages", drives message fifo and the tasklet |
15 | (pump_transfer) is responsible for queuing SPI transactions and setting up and |
16 | launching the dma/interrupt driven transfers. |
17 | |
18 | Declaring PXA2xx Master Controllers |
19 | ----------------------------------- |
20 | Typically a SPI master is defined in the arch/.../mach-*/board-*.c as a |
21 | "platform device". The master configuration is passed to the driver via a table |
22 | found in include/linux/spi/pxa2xx_spi.h: |
23 | |
24 | struct pxa2xx_spi_master { |
25 | u32 clock_enable; |
26 | u16 num_chipselect; |
27 | u8 enable_dma; |
28 | }; |
29 | |
30 | The "pxa2xx_spi_master.clock_enable" field is used to enable/disable the |
31 | corresponding SSP peripheral block in the "Clock Enable Register (CKEN"). See |
32 | the "PXA2xx Developer Manual" section "Clocks and Power Management". |
33 | |
34 | The "pxa2xx_spi_master.num_chipselect" field is used to determine the number of |
35 | slave device (chips) attached to this SPI master. |
36 | |
37 | The "pxa2xx_spi_master.enable_dma" field informs the driver that SSP DMA should |
38 | be used. This caused the driver to acquire two DMA channels: rx_channel and |
39 | tx_channel. The rx_channel has a higher DMA service priority the tx_channel. |
40 | See the "PXA2xx Developer Manual" section "DMA Controller". |
41 | |
42 | NSSP MASTER SAMPLE |
43 | ------------------ |
44 | Below is a sample configuration using the PXA255 NSSP. |
45 | |
46 | static struct resource pxa_spi_nssp_resources[] = { |
47 | [0] = { |
48 | .start = __PREG(SSCR0_P(2)), /* Start address of NSSP */ |
49 | .end = __PREG(SSCR0_P(2)) + 0x2c, /* Range of registers */ |
50 | .flags = IORESOURCE_MEM, |
51 | }, |
52 | [1] = { |
53 | .start = IRQ_NSSP, /* NSSP IRQ */ |
54 | .end = IRQ_NSSP, |
55 | .flags = IORESOURCE_IRQ, |
56 | }, |
57 | }; |
58 | |
59 | static struct pxa2xx_spi_master pxa_nssp_master_info = { |
60 | .clock_enable = CKEN_NSSP, /* NSSP Peripheral clock */ |
61 | .num_chipselect = 1, /* Matches the number of chips attached to NSSP */ |
62 | .enable_dma = 1, /* Enables NSSP DMA */ |
63 | }; |
64 | |
65 | static struct platform_device pxa_spi_nssp = { |
66 | .name = "pxa2xx-spi", /* MUST BE THIS VALUE, so device match driver */ |
67 | .id = 2, /* Bus number, MUST MATCH SSP number 1..n */ |
68 | .resource = pxa_spi_nssp_resources, |
69 | .num_resources = ARRAY_SIZE(pxa_spi_nssp_resources), |
70 | .dev = { |
71 | .platform_data = &pxa_nssp_master_info, /* Passed to driver */ |
72 | }, |
73 | }; |
74 | |
75 | static struct platform_device *devices[] __initdata = { |
76 | &pxa_spi_nssp, |
77 | }; |
78 | |
79 | static void __init board_init(void) |
80 | { |
81 | (void)platform_add_device(devices, ARRAY_SIZE(devices)); |
82 | } |
83 | |
84 | Declaring Slave Devices |
85 | ----------------------- |
86 | Typically each SPI slave (chip) is defined in the arch/.../mach-*/board-*.c |
87 | using the "spi_board_info" structure found in "linux/spi/spi.h". See |
88 | "Documentation/spi/spi_summary" for additional information. |
89 | |
90 | Each slave device attached to the PXA must provide slave specific configuration |
91 | information via the structure "pxa2xx_spi_chip" found in |
92 | "include/linux/spi/pxa2xx_spi.h". The pxa2xx_spi master controller driver |
93 | will uses the configuration whenever the driver communicates with the slave |
94 | device. All fields are optional. |
95 | |
96 | struct pxa2xx_spi_chip { |
97 | u8 tx_threshold; |
98 | u8 rx_threshold; |
99 | u8 dma_burst_size; |
100 | u32 timeout; |
101 | u8 enable_loopback; |
102 | void (*cs_control)(u32 command); |
103 | }; |
104 | |
105 | The "pxa2xx_spi_chip.tx_threshold" and "pxa2xx_spi_chip.rx_threshold" fields are |
106 | used to configure the SSP hardware fifo. These fields are critical to the |
107 | performance of pxa2xx_spi driver and misconfiguration will result in rx |
108 | fifo overruns (especially in PIO mode transfers). Good default values are |
109 | |
110 | .tx_threshold = 8, |
111 | .rx_threshold = 8, |
112 | |
113 | The range is 1 to 16 where zero indicates "use default". |
114 | |
115 | The "pxa2xx_spi_chip.dma_burst_size" field is used to configure PXA2xx DMA |
116 | engine and is related the "spi_device.bits_per_word" field. Read and understand |
117 | the PXA2xx "Developer Manual" sections on the DMA controller and SSP Controllers |
118 | to determine the correct value. An SSP configured for byte-wide transfers would |
119 | use a value of 8. The driver will determine a reasonable default if |
120 | dma_burst_size == 0. |
121 | |
122 | The "pxa2xx_spi_chip.timeout" fields is used to efficiently handle |
123 | trailing bytes in the SSP receiver fifo. The correct value for this field is |
124 | dependent on the SPI bus speed ("spi_board_info.max_speed_hz") and the specific |
125 | slave device. Please note that the PXA2xx SSP 1 does not support trailing byte |
126 | timeouts and must busy-wait any trailing bytes. |
127 | |
128 | The "pxa2xx_spi_chip.enable_loopback" field is used to place the SSP porting |
129 | into internal loopback mode. In this mode the SSP controller internally |
130 | connects the SSPTX pin to the SSPRX pin. This is useful for initial setup |
131 | testing. |
132 | |
133 | The "pxa2xx_spi_chip.cs_control" field is used to point to a board specific |
134 | function for asserting/deasserting a slave device chip select. If the field is |
135 | NULL, the pxa2xx_spi master controller driver assumes that the SSP port is |
136 | configured to use SSPFRM instead. |
137 | |
138 | NOTE: the SPI driver cannot control the chip select if SSPFRM is used, so the |
139 | chipselect is dropped after each spi_transfer. Most devices need chip select |
140 | asserted around the complete message. Use SSPFRM as a GPIO (through cs_control) |
141 | to accommodate these chips. |
142 | |
143 | |
144 | NSSP SLAVE SAMPLE |
145 | ----------------- |
146 | The pxa2xx_spi_chip structure is passed to the pxa2xx_spi driver in the |
147 | "spi_board_info.controller_data" field. Below is a sample configuration using |
148 | the PXA255 NSSP. |
149 | |
150 | /* Chip Select control for the CS8415A SPI slave device */ |
151 | static void cs8415a_cs_control(u32 command) |
152 | { |
153 | if (command & PXA2XX_CS_ASSERT) |
154 | GPCR(2) = GPIO_bit(2); |
155 | else |
156 | GPSR(2) = GPIO_bit(2); |
157 | } |
158 | |
159 | /* Chip Select control for the CS8405A SPI slave device */ |
160 | static void cs8405a_cs_control(u32 command) |
161 | { |
162 | if (command & PXA2XX_CS_ASSERT) |
163 | GPCR(3) = GPIO_bit(3); |
164 | else |
165 | GPSR(3) = GPIO_bit(3); |
166 | } |
167 | |
168 | static struct pxa2xx_spi_chip cs8415a_chip_info = { |
169 | .tx_threshold = 8, /* SSP hardward FIFO threshold */ |
170 | .rx_threshold = 8, /* SSP hardward FIFO threshold */ |
171 | .dma_burst_size = 8, /* Byte wide transfers used so 8 byte bursts */ |
172 | .timeout = 235, /* See Intel documentation */ |
173 | .cs_control = cs8415a_cs_control, /* Use external chip select */ |
174 | }; |
175 | |
176 | static struct pxa2xx_spi_chip cs8405a_chip_info = { |
177 | .tx_threshold = 8, /* SSP hardward FIFO threshold */ |
178 | .rx_threshold = 8, /* SSP hardward FIFO threshold */ |
179 | .dma_burst_size = 8, /* Byte wide transfers used so 8 byte bursts */ |
180 | .timeout = 235, /* See Intel documentation */ |
181 | .cs_control = cs8405a_cs_control, /* Use external chip select */ |
182 | }; |
183 | |
184 | static struct spi_board_info streetracer_spi_board_info[] __initdata = { |
185 | { |
186 | .modalias = "cs8415a", /* Name of spi_driver for this device */ |
187 | .max_speed_hz = 3686400, /* Run SSP as fast a possbile */ |
188 | .bus_num = 2, /* Framework bus number */ |
189 | .chip_select = 0, /* Framework chip select */ |
190 | .platform_data = NULL; /* No spi_driver specific config */ |
191 | .controller_data = &cs8415a_chip_info, /* Master chip config */ |
192 | .irq = STREETRACER_APCI_IRQ, /* Slave device interrupt */ |
193 | }, |
194 | { |
195 | .modalias = "cs8405a", /* Name of spi_driver for this device */ |
196 | .max_speed_hz = 3686400, /* Run SSP as fast a possbile */ |
197 | .bus_num = 2, /* Framework bus number */ |
198 | .chip_select = 1, /* Framework chip select */ |
199 | .controller_data = &cs8405a_chip_info, /* Master chip config */ |
200 | .irq = STREETRACER_APCI_IRQ, /* Slave device interrupt */ |
201 | }, |
202 | }; |
203 | |
204 | static void __init streetracer_init(void) |
205 | { |
206 | spi_register_board_info(streetracer_spi_board_info, |
207 | ARRAY_SIZE(streetracer_spi_board_info)); |
208 | } |
209 | |
210 | |
211 | DMA and PIO I/O Support |
212 | ----------------------- |
213 | The pxa2xx_spi driver supports both DMA and interrupt driven PIO message |
214 | transfers. The driver defaults to PIO mode and DMA transfers must be enabled |
215 | by setting the "enable_dma" flag in the "pxa2xx_spi_master" structure. The DMA |
216 | mode supports both coherent and stream based DMA mappings. |
217 | |
218 | The following logic is used to determine the type of I/O to be used on |
219 | a per "spi_transfer" basis: |
220 | |
221 | if !enable_dma then |
222 | always use PIO transfers |
223 | |
224 | if spi_message.len > 8191 then |
225 | print "rate limited" warning |
226 | use PIO transfers |
227 | |
228 | if spi_message.is_dma_mapped and rx_dma_buf != 0 and tx_dma_buf != 0 then |
229 | use coherent DMA mode |
230 | |
231 | if rx_buf and tx_buf are aligned on 8 byte boundary then |
232 | use streaming DMA mode |
233 | |
234 | otherwise |
235 | use PIO transfer |
236 | |
237 | THANKS TO |
238 | --------- |
239 | |
240 | David Brownell and others for mentoring the development of this driver. |
241 | |
242 |
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