Root/
1 | config MMU |
2 | def_bool n |
3 | |
4 | config FPU |
5 | def_bool n |
6 | |
7 | config RWSEM_GENERIC_SPINLOCK |
8 | def_bool y |
9 | |
10 | config RWSEM_XCHGADD_ALGORITHM |
11 | def_bool n |
12 | |
13 | config BLACKFIN |
14 | def_bool y |
15 | select HAVE_ARCH_KGDB |
16 | select HAVE_ARCH_TRACEHOOK |
17 | select HAVE_DYNAMIC_FTRACE |
18 | select HAVE_FTRACE_MCOUNT_RECORD |
19 | select HAVE_FUNCTION_GRAPH_TRACER |
20 | select HAVE_FUNCTION_TRACER |
21 | select HAVE_FUNCTION_TRACE_MCOUNT_TEST |
22 | select HAVE_IDE |
23 | select HAVE_KERNEL_GZIP if RAMKERNEL |
24 | select HAVE_KERNEL_BZIP2 if RAMKERNEL |
25 | select HAVE_KERNEL_LZMA if RAMKERNEL |
26 | select HAVE_KERNEL_LZO if RAMKERNEL |
27 | select HAVE_OPROFILE |
28 | select HAVE_PERF_EVENTS |
29 | select ARCH_HAVE_CUSTOM_GPIO_H |
30 | select ARCH_REQUIRE_GPIOLIB |
31 | select HAVE_UID16 |
32 | select HAVE_UNDERSCORE_SYMBOL_PREFIX |
33 | select VIRT_TO_BUS |
34 | select ARCH_WANT_IPC_PARSE_VERSION |
35 | select HAVE_GENERIC_HARDIRQS |
36 | select GENERIC_ATOMIC64 |
37 | select GENERIC_IRQ_PROBE |
38 | select USE_GENERIC_SMP_HELPERS if SMP |
39 | select HAVE_NMI_WATCHDOG if NMI_WATCHDOG |
40 | select GENERIC_SMP_IDLE_THREAD |
41 | select ARCH_USES_GETTIMEOFFSET if !GENERIC_CLOCKEVENTS |
42 | select HAVE_MOD_ARCH_SPECIFIC |
43 | select MODULES_USE_ELF_RELA |
44 | select HAVE_DEBUG_STACKOVERFLOW |
45 | |
46 | config GENERIC_CSUM |
47 | def_bool y |
48 | |
49 | config GENERIC_BUG |
50 | def_bool y |
51 | depends on BUG |
52 | |
53 | config ZONE_DMA |
54 | def_bool y |
55 | |
56 | config FORCE_MAX_ZONEORDER |
57 | int |
58 | default "14" |
59 | |
60 | config GENERIC_CALIBRATE_DELAY |
61 | def_bool y |
62 | |
63 | config LOCKDEP_SUPPORT |
64 | def_bool y |
65 | |
66 | config STACKTRACE_SUPPORT |
67 | def_bool y |
68 | |
69 | config TRACE_IRQFLAGS_SUPPORT |
70 | def_bool y |
71 | |
72 | source "init/Kconfig" |
73 | |
74 | source "kernel/Kconfig.preempt" |
75 | |
76 | source "kernel/Kconfig.freezer" |
77 | |
78 | menu "Blackfin Processor Options" |
79 | |
80 | comment "Processor and Board Settings" |
81 | |
82 | choice |
83 | prompt "CPU" |
84 | default BF533 |
85 | |
86 | config BF512 |
87 | bool "BF512" |
88 | help |
89 | BF512 Processor Support. |
90 | |
91 | config BF514 |
92 | bool "BF514" |
93 | help |
94 | BF514 Processor Support. |
95 | |
96 | config BF516 |
97 | bool "BF516" |
98 | help |
99 | BF516 Processor Support. |
100 | |
101 | config BF518 |
102 | bool "BF518" |
103 | help |
104 | BF518 Processor Support. |
105 | |
106 | config BF522 |
107 | bool "BF522" |
108 | help |
109 | BF522 Processor Support. |
110 | |
111 | config BF523 |
112 | bool "BF523" |
113 | help |
114 | BF523 Processor Support. |
115 | |
116 | config BF524 |
117 | bool "BF524" |
118 | help |
119 | BF524 Processor Support. |
120 | |
121 | config BF525 |
122 | bool "BF525" |
123 | help |
124 | BF525 Processor Support. |
125 | |
126 | config BF526 |
127 | bool "BF526" |
128 | help |
129 | BF526 Processor Support. |
130 | |
131 | config BF527 |
132 | bool "BF527" |
133 | help |
134 | BF527 Processor Support. |
135 | |
136 | config BF531 |
137 | bool "BF531" |
138 | help |
139 | BF531 Processor Support. |
140 | |
141 | config BF532 |
142 | bool "BF532" |
143 | help |
144 | BF532 Processor Support. |
145 | |
146 | config BF533 |
147 | bool "BF533" |
148 | help |
149 | BF533 Processor Support. |
150 | |
151 | config BF534 |
152 | bool "BF534" |
153 | help |
154 | BF534 Processor Support. |
155 | |
156 | config BF536 |
157 | bool "BF536" |
158 | help |
159 | BF536 Processor Support. |
160 | |
161 | config BF537 |
162 | bool "BF537" |
163 | help |
164 | BF537 Processor Support. |
165 | |
166 | config BF538 |
167 | bool "BF538" |
168 | help |
169 | BF538 Processor Support. |
170 | |
171 | config BF539 |
172 | bool "BF539" |
173 | help |
174 | BF539 Processor Support. |
175 | |
176 | config BF542_std |
177 | bool "BF542" |
178 | help |
179 | BF542 Processor Support. |
180 | |
181 | config BF542M |
182 | bool "BF542m" |
183 | help |
184 | BF542 Processor Support. |
185 | |
186 | config BF544_std |
187 | bool "BF544" |
188 | help |
189 | BF544 Processor Support. |
190 | |
191 | config BF544M |
192 | bool "BF544m" |
193 | help |
194 | BF544 Processor Support. |
195 | |
196 | config BF547_std |
197 | bool "BF547" |
198 | help |
199 | BF547 Processor Support. |
200 | |
201 | config BF547M |
202 | bool "BF547m" |
203 | help |
204 | BF547 Processor Support. |
205 | |
206 | config BF548_std |
207 | bool "BF548" |
208 | help |
209 | BF548 Processor Support. |
210 | |
211 | config BF548M |
212 | bool "BF548m" |
213 | help |
214 | BF548 Processor Support. |
215 | |
216 | config BF549_std |
217 | bool "BF549" |
218 | help |
219 | BF549 Processor Support. |
220 | |
221 | config BF549M |
222 | bool "BF549m" |
223 | help |
224 | BF549 Processor Support. |
225 | |
226 | config BF561 |
227 | bool "BF561" |
228 | help |
229 | BF561 Processor Support. |
230 | |
231 | config BF609 |
232 | bool "BF609" |
233 | select CLKDEV_LOOKUP |
234 | help |
235 | BF609 Processor Support. |
236 | |
237 | endchoice |
238 | |
239 | config SMP |
240 | depends on BF561 |
241 | select TICKSOURCE_CORETMR |
242 | bool "Symmetric multi-processing support" |
243 | ---help--- |
244 | This enables support for systems with more than one CPU, |
245 | like the dual core BF561. If you have a system with only one |
246 | CPU, say N. If you have a system with more than one CPU, say Y. |
247 | |
248 | If you don't know what to do here, say N. |
249 | |
250 | config NR_CPUS |
251 | int |
252 | depends on SMP |
253 | default 2 if BF561 |
254 | |
255 | config HOTPLUG_CPU |
256 | bool "Support for hot-pluggable CPUs" |
257 | depends on SMP |
258 | default y |
259 | |
260 | config BF_REV_MIN |
261 | int |
262 | default 0 if (BF51x || BF52x || (BF54x && !BF54xM)) || BF60x |
263 | default 2 if (BF537 || BF536 || BF534) |
264 | default 3 if (BF561 || BF533 || BF532 || BF531 || BF54xM) |
265 | default 4 if (BF538 || BF539) |
266 | |
267 | config BF_REV_MAX |
268 | int |
269 | default 2 if (BF51x || BF52x || (BF54x && !BF54xM)) || BF60x |
270 | default 3 if (BF537 || BF536 || BF534 || BF54xM) |
271 | default 5 if (BF561 || BF538 || BF539) |
272 | default 6 if (BF533 || BF532 || BF531) |
273 | |
274 | choice |
275 | prompt "Silicon Rev" |
276 | default BF_REV_0_0 if (BF51x || BF52x || BF60x) |
277 | default BF_REV_0_2 if (BF534 || BF536 || BF537 || (BF54x && !BF54xM)) |
278 | default BF_REV_0_3 if (BF531 || BF532 || BF533 || BF54xM || BF561) |
279 | |
280 | config BF_REV_0_0 |
281 | bool "0.0" |
282 | depends on (BF51x || BF52x || (BF54x && !BF54xM) || BF60x) |
283 | |
284 | config BF_REV_0_1 |
285 | bool "0.1" |
286 | depends on (BF51x || BF52x || (BF54x && !BF54xM) || BF60x) |
287 | |
288 | config BF_REV_0_2 |
289 | bool "0.2" |
290 | depends on (BF51x || BF52x || BF537 || BF536 || BF534 || (BF54x && !BF54xM)) |
291 | |
292 | config BF_REV_0_3 |
293 | bool "0.3" |
294 | depends on (BF54xM || BF561 || BF537 || BF536 || BF534 || BF533 || BF532 || BF531) |
295 | |
296 | config BF_REV_0_4 |
297 | bool "0.4" |
298 | depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539 || BF54x) |
299 | |
300 | config BF_REV_0_5 |
301 | bool "0.5" |
302 | depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539) |
303 | |
304 | config BF_REV_0_6 |
305 | bool "0.6" |
306 | depends on (BF533 || BF532 || BF531) |
307 | |
308 | config BF_REV_ANY |
309 | bool "any" |
310 | |
311 | config BF_REV_NONE |
312 | bool "none" |
313 | |
314 | endchoice |
315 | |
316 | config BF53x |
317 | bool |
318 | depends on (BF531 || BF532 || BF533 || BF534 || BF536 || BF537) |
319 | default y |
320 | |
321 | config MEM_MT48LC64M4A2FB_7E |
322 | bool |
323 | depends on (BFIN533_STAMP) |
324 | default y |
325 | |
326 | config MEM_MT48LC16M16A2TG_75 |
327 | bool |
328 | depends on (BFIN533_EZKIT || BFIN561_EZKIT \ |
329 | || BFIN533_BLUETECHNIX_CM || BFIN537_BLUETECHNIX_CM_E \ |
330 | || BFIN537_BLUETECHNIX_CM_U || H8606_HVSISTEMAS \ |
331 | || BFIN527_BLUETECHNIX_CM) |
332 | default y |
333 | |
334 | config MEM_MT48LC32M8A2_75 |
335 | bool |
336 | depends on (BFIN518F_EZBRD || BFIN537_STAMP || PNAV10 || BFIN538_EZKIT) |
337 | default y |
338 | |
339 | config MEM_MT48LC8M32B2B5_7 |
340 | bool |
341 | depends on (BFIN561_BLUETECHNIX_CM) |
342 | default y |
343 | |
344 | config MEM_MT48LC32M16A2TG_75 |
345 | bool |
346 | depends on (BFIN527_EZKIT || BFIN527_EZKIT_V2 || BFIN532_IP0X || BLACKSTAMP || BFIN527_AD7160EVAL) |
347 | default y |
348 | |
349 | config MEM_MT48H32M16LFCJ_75 |
350 | bool |
351 | depends on (BFIN526_EZBRD) |
352 | default y |
353 | |
354 | config MEM_MT47H64M16 |
355 | bool |
356 | depends on (BFIN609_EZKIT) |
357 | default y |
358 | |
359 | source "arch/blackfin/mach-bf518/Kconfig" |
360 | source "arch/blackfin/mach-bf527/Kconfig" |
361 | source "arch/blackfin/mach-bf533/Kconfig" |
362 | source "arch/blackfin/mach-bf561/Kconfig" |
363 | source "arch/blackfin/mach-bf537/Kconfig" |
364 | source "arch/blackfin/mach-bf538/Kconfig" |
365 | source "arch/blackfin/mach-bf548/Kconfig" |
366 | source "arch/blackfin/mach-bf609/Kconfig" |
367 | |
368 | menu "Board customizations" |
369 | |
370 | config CMDLINE_BOOL |
371 | bool "Default bootloader kernel arguments" |
372 | |
373 | config CMDLINE |
374 | string "Initial kernel command string" |
375 | depends on CMDLINE_BOOL |
376 | default "console=ttyBF0,57600" |
377 | help |
378 | If you don't have a boot loader capable of passing a command line string |
379 | to the kernel, you may specify one here. As a minimum, you should specify |
380 | the memory size and the root device (e.g., mem=8M, root=/dev/nfs). |
381 | |
382 | config BOOT_LOAD |
383 | hex "Kernel load address for booting" |
384 | default "0x1000" |
385 | range 0x1000 0x20000000 |
386 | help |
387 | This option allows you to set the load address of the kernel. |
388 | This can be useful if you are on a board which has a small amount |
389 | of memory or you wish to reserve some memory at the beginning of |
390 | the address space. |
391 | |
392 | Note that you need to keep this value above 4k (0x1000) as this |
393 | memory region is used to capture NULL pointer references as well |
394 | as some core kernel functions. |
395 | |
396 | config PHY_RAM_BASE_ADDRESS |
397 | hex "Physical RAM Base" |
398 | default 0x0 |
399 | help |
400 | set BF609 FPGA physical SRAM base address |
401 | |
402 | config ROM_BASE |
403 | hex "Kernel ROM Base" |
404 | depends on ROMKERNEL |
405 | default "0x20040040" |
406 | range 0x20000000 0x20400000 if !(BF54x || BF561 || BF60x) |
407 | range 0x20000000 0x30000000 if (BF54x || BF561) |
408 | range 0xB0000000 0xC0000000 if (BF60x) |
409 | help |
410 | Make sure your ROM base does not include any file-header |
411 | information that is prepended to the kernel. |
412 | |
413 | For example, the bootable U-Boot format (created with |
414 | mkimage) has a 64 byte header (0x40). So while the image |
415 | you write to flash might start at say 0x20080000, you have |
416 | to add 0x40 to get the kernel's ROM base as it will come |
417 | after the header. |
418 | |
419 | comment "Clock/PLL Setup" |
420 | |
421 | config CLKIN_HZ |
422 | int "Frequency of the crystal on the board in Hz" |
423 | default "10000000" if BFIN532_IP0X |
424 | default "11059200" if BFIN533_STAMP |
425 | default "24576000" if PNAV10 |
426 | default "25000000" # most people use this |
427 | default "27000000" if BFIN533_EZKIT |
428 | default "30000000" if BFIN561_EZKIT |
429 | default "24000000" if BFIN527_AD7160EVAL |
430 | help |
431 | The frequency of CLKIN crystal oscillator on the board in Hz. |
432 | Warning: This value should match the crystal on the board. Otherwise, |
433 | peripherals won't work properly. |
434 | |
435 | config BFIN_KERNEL_CLOCK |
436 | bool "Re-program Clocks while Kernel boots?" |
437 | default n |
438 | help |
439 | This option decides if kernel clocks are re-programed from the |
440 | bootloader settings. If the clocks are not set, the SDRAM settings |
441 | are also not changed, and the Bootloader does 100% of the hardware |
442 | configuration. |
443 | |
444 | config PLL_BYPASS |
445 | bool "Bypass PLL" |
446 | depends on BFIN_KERNEL_CLOCK && (!BF60x) |
447 | default n |
448 | |
449 | config CLKIN_HALF |
450 | bool "Half Clock In" |
451 | depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS) |
452 | default n |
453 | help |
454 | If this is set the clock will be divided by 2, before it goes to the PLL. |
455 | |
456 | config VCO_MULT |
457 | int "VCO Multiplier" |
458 | depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS) |
459 | range 1 64 |
460 | default "22" if BFIN533_EZKIT |
461 | default "45" if BFIN533_STAMP |
462 | default "20" if (BFIN537_STAMP || BFIN527_EZKIT || BFIN527_EZKIT_V2 || BFIN548_EZKIT || BFIN548_BLUETECHNIX_CM || BFIN538_EZKIT) |
463 | default "22" if BFIN533_BLUETECHNIX_CM |
464 | default "20" if (BFIN537_BLUETECHNIX_CM_E || BFIN537_BLUETECHNIX_CM_U || BFIN527_BLUETECHNIX_CM || BFIN561_BLUETECHNIX_CM) |
465 | default "20" if (BFIN561_EZKIT || BF609) |
466 | default "16" if (H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD || BFIN518F_EZBRD) |
467 | default "25" if BFIN527_AD7160EVAL |
468 | help |
469 | This controls the frequency of the on-chip PLL. This can be between 1 and 64. |
470 | PLL Frequency = (Crystal Frequency) * (this setting) |
471 | |
472 | choice |
473 | prompt "Core Clock Divider" |
474 | depends on BFIN_KERNEL_CLOCK |
475 | default CCLK_DIV_1 |
476 | help |
477 | This sets the frequency of the core. It can be 1, 2, 4 or 8 |
478 | Core Frequency = (PLL frequency) / (this setting) |
479 | |
480 | config CCLK_DIV_1 |
481 | bool "1" |
482 | |
483 | config CCLK_DIV_2 |
484 | bool "2" |
485 | |
486 | config CCLK_DIV_4 |
487 | bool "4" |
488 | |
489 | config CCLK_DIV_8 |
490 | bool "8" |
491 | endchoice |
492 | |
493 | config SCLK_DIV |
494 | int "System Clock Divider" |
495 | depends on BFIN_KERNEL_CLOCK |
496 | range 1 15 |
497 | default 4 |
498 | help |
499 | This sets the frequency of the system clock (including SDRAM or DDR) on |
500 | !BF60x else it set the clock for system buses and provides the |
501 | source from which SCLK0 and SCLK1 are derived. |
502 | This can be between 1 and 15 |
503 | System Clock = (PLL frequency) / (this setting) |
504 | |
505 | config SCLK0_DIV |
506 | int "System Clock0 Divider" |
507 | depends on BFIN_KERNEL_CLOCK && BF60x |
508 | range 1 15 |
509 | default 1 |
510 | help |
511 | This sets the frequency of the system clock0 for PVP and all other |
512 | peripherals not clocked by SCLK1. |
513 | This can be between 1 and 15 |
514 | System Clock0 = (System Clock) / (this setting) |
515 | |
516 | config SCLK1_DIV |
517 | int "System Clock1 Divider" |
518 | depends on BFIN_KERNEL_CLOCK && BF60x |
519 | range 1 15 |
520 | default 1 |
521 | help |
522 | This sets the frequency of the system clock1 (including SPORT, SPI and ACM). |
523 | This can be between 1 and 15 |
524 | System Clock1 = (System Clock) / (this setting) |
525 | |
526 | config DCLK_DIV |
527 | int "DDR Clock Divider" |
528 | depends on BFIN_KERNEL_CLOCK && BF60x |
529 | range 1 15 |
530 | default 2 |
531 | help |
532 | This sets the frequency of the DDR memory. |
533 | This can be between 1 and 15 |
534 | DDR Clock = (PLL frequency) / (this setting) |
535 | |
536 | choice |
537 | prompt "DDR SDRAM Chip Type" |
538 | depends on BFIN_KERNEL_CLOCK |
539 | depends on BF54x |
540 | default MEM_MT46V32M16_5B |
541 | |
542 | config MEM_MT46V32M16_6T |
543 | bool "MT46V32M16_6T" |
544 | |
545 | config MEM_MT46V32M16_5B |
546 | bool "MT46V32M16_5B" |
547 | endchoice |
548 | |
549 | choice |
550 | prompt "DDR/SDRAM Timing" |
551 | depends on BFIN_KERNEL_CLOCK && !BF60x |
552 | default BFIN_KERNEL_CLOCK_MEMINIT_CALC |
553 | help |
554 | This option allows you to specify Blackfin SDRAM/DDR Timing parameters |
555 | The calculated SDRAM timing parameters may not be 100% |
556 | accurate - This option is therefore marked experimental. |
557 | |
558 | config BFIN_KERNEL_CLOCK_MEMINIT_CALC |
559 | bool "Calculate Timings" |
560 | |
561 | config BFIN_KERNEL_CLOCK_MEMINIT_SPEC |
562 | bool "Provide accurate Timings based on target SCLK" |
563 | help |
564 | Please consult the Blackfin Hardware Reference Manuals as well |
565 | as the memory device datasheet. |
566 | http://docs.blackfin.uclinux.org/doku.php?id=bfin:sdram |
567 | endchoice |
568 | |
569 | menu "Memory Init Control" |
570 | depends on BFIN_KERNEL_CLOCK_MEMINIT_SPEC |
571 | |
572 | config MEM_DDRCTL0 |
573 | depends on BF54x |
574 | hex "DDRCTL0" |
575 | default 0x0 |
576 | |
577 | config MEM_DDRCTL1 |
578 | depends on BF54x |
579 | hex "DDRCTL1" |
580 | default 0x0 |
581 | |
582 | config MEM_DDRCTL2 |
583 | depends on BF54x |
584 | hex "DDRCTL2" |
585 | default 0x0 |
586 | |
587 | config MEM_EBIU_DDRQUE |
588 | depends on BF54x |
589 | hex "DDRQUE" |
590 | default 0x0 |
591 | |
592 | config MEM_SDRRC |
593 | depends on !BF54x |
594 | hex "SDRRC" |
595 | default 0x0 |
596 | |
597 | config MEM_SDGCTL |
598 | depends on !BF54x |
599 | hex "SDGCTL" |
600 | default 0x0 |
601 | endmenu |
602 | |
603 | # |
604 | # Max & Min Speeds for various Chips |
605 | # |
606 | config MAX_VCO_HZ |
607 | int |
608 | default 400000000 if BF512 |
609 | default 400000000 if BF514 |
610 | default 400000000 if BF516 |
611 | default 400000000 if BF518 |
612 | default 400000000 if BF522 |
613 | default 600000000 if BF523 |
614 | default 400000000 if BF524 |
615 | default 600000000 if BF525 |
616 | default 400000000 if BF526 |
617 | default 600000000 if BF527 |
618 | default 400000000 if BF531 |
619 | default 400000000 if BF532 |
620 | default 750000000 if BF533 |
621 | default 500000000 if BF534 |
622 | default 400000000 if BF536 |
623 | default 600000000 if BF537 |
624 | default 533333333 if BF538 |
625 | default 533333333 if BF539 |
626 | default 600000000 if BF542 |
627 | default 533333333 if BF544 |
628 | default 600000000 if BF547 |
629 | default 600000000 if BF548 |
630 | default 533333333 if BF549 |
631 | default 600000000 if BF561 |
632 | default 800000000 if BF609 |
633 | |
634 | config MIN_VCO_HZ |
635 | int |
636 | default 50000000 |
637 | |
638 | config MAX_SCLK_HZ |
639 | int |
640 | default 200000000 if BF609 |
641 | default 133333333 |
642 | |
643 | config MIN_SCLK_HZ |
644 | int |
645 | default 27000000 |
646 | |
647 | comment "Kernel Timer/Scheduler" |
648 | |
649 | source kernel/Kconfig.hz |
650 | |
651 | config SET_GENERIC_CLOCKEVENTS |
652 | bool "Generic clock events" |
653 | default y |
654 | select GENERIC_CLOCKEVENTS |
655 | |
656 | menu "Clock event device" |
657 | depends on GENERIC_CLOCKEVENTS |
658 | config TICKSOURCE_GPTMR0 |
659 | bool "GPTimer0" |
660 | depends on !SMP |
661 | select BFIN_GPTIMERS |
662 | |
663 | config TICKSOURCE_CORETMR |
664 | bool "Core timer" |
665 | default y |
666 | endmenu |
667 | |
668 | menu "Clock souce" |
669 | depends on GENERIC_CLOCKEVENTS |
670 | config CYCLES_CLOCKSOURCE |
671 | bool "CYCLES" |
672 | default y |
673 | depends on !BFIN_SCRATCH_REG_CYCLES |
674 | depends on !SMP |
675 | help |
676 | If you say Y here, you will enable support for using the 'cycles' |
677 | registers as a clock source. Doing so means you will be unable to |
678 | safely write to the 'cycles' register during runtime. You will |
679 | still be able to read it (such as for performance monitoring), but |
680 | writing the registers will most likely crash the kernel. |
681 | |
682 | config GPTMR0_CLOCKSOURCE |
683 | bool "GPTimer0" |
684 | select BFIN_GPTIMERS |
685 | depends on !TICKSOURCE_GPTMR0 |
686 | endmenu |
687 | |
688 | comment "Misc" |
689 | |
690 | choice |
691 | prompt "Blackfin Exception Scratch Register" |
692 | default BFIN_SCRATCH_REG_RETN |
693 | help |
694 | Select the resource to reserve for the Exception handler: |
695 | - RETN: Non-Maskable Interrupt (NMI) |
696 | - RETE: Exception Return (JTAG/ICE) |
697 | - CYCLES: Performance counter |
698 | |
699 | If you are unsure, please select "RETN". |
700 | |
701 | config BFIN_SCRATCH_REG_RETN |
702 | bool "RETN" |
703 | help |
704 | Use the RETN register in the Blackfin exception handler |
705 | as a stack scratch register. This means you cannot |
706 | safely use NMI on the Blackfin while running Linux, but |
707 | you can debug the system with a JTAG ICE and use the |
708 | CYCLES performance registers. |
709 | |
710 | If you are unsure, please select "RETN". |
711 | |
712 | config BFIN_SCRATCH_REG_RETE |
713 | bool "RETE" |
714 | help |
715 | Use the RETE register in the Blackfin exception handler |
716 | as a stack scratch register. This means you cannot |
717 | safely use a JTAG ICE while debugging a Blackfin board, |
718 | but you can safely use the CYCLES performance registers |
719 | and the NMI. |
720 | |
721 | If you are unsure, please select "RETN". |
722 | |
723 | config BFIN_SCRATCH_REG_CYCLES |
724 | bool "CYCLES" |
725 | help |
726 | Use the CYCLES register in the Blackfin exception handler |
727 | as a stack scratch register. This means you cannot |
728 | safely use the CYCLES performance registers on a Blackfin |
729 | board at anytime, but you can debug the system with a JTAG |
730 | ICE and use the NMI. |
731 | |
732 | If you are unsure, please select "RETN". |
733 | |
734 | endchoice |
735 | |
736 | endmenu |
737 | |
738 | |
739 | menu "Blackfin Kernel Optimizations" |
740 | |
741 | comment "Memory Optimizations" |
742 | |
743 | config I_ENTRY_L1 |
744 | bool "Locate interrupt entry code in L1 Memory" |
745 | default y |
746 | depends on !SMP |
747 | help |
748 | If enabled, interrupt entry code (STORE/RESTORE CONTEXT) is linked |
749 | into L1 instruction memory. (less latency) |
750 | |
751 | config EXCPT_IRQ_SYSC_L1 |
752 | bool "Locate entire ASM lowlevel exception / interrupt - Syscall and CPLB handler code in L1 Memory" |
753 | default y |
754 | depends on !SMP |
755 | help |
756 | If enabled, the entire ASM lowlevel exception and interrupt entry code |
757 | (STORE/RESTORE CONTEXT) is linked into L1 instruction memory. |
758 | (less latency) |
759 | |
760 | config DO_IRQ_L1 |
761 | bool "Locate frequently called do_irq dispatcher function in L1 Memory" |
762 | default y |
763 | depends on !SMP |
764 | help |
765 | If enabled, the frequently called do_irq dispatcher function is linked |
766 | into L1 instruction memory. (less latency) |
767 | |
768 | config CORE_TIMER_IRQ_L1 |
769 | bool "Locate frequently called timer_interrupt() function in L1 Memory" |
770 | default y |
771 | depends on !SMP |
772 | help |
773 | If enabled, the frequently called timer_interrupt() function is linked |
774 | into L1 instruction memory. (less latency) |
775 | |
776 | config IDLE_L1 |
777 | bool "Locate frequently idle function in L1 Memory" |
778 | default y |
779 | depends on !SMP |
780 | help |
781 | If enabled, the frequently called idle function is linked |
782 | into L1 instruction memory. (less latency) |
783 | |
784 | config SCHEDULE_L1 |
785 | bool "Locate kernel schedule function in L1 Memory" |
786 | default y |
787 | depends on !SMP |
788 | help |
789 | If enabled, the frequently called kernel schedule is linked |
790 | into L1 instruction memory. (less latency) |
791 | |
792 | config ARITHMETIC_OPS_L1 |
793 | bool "Locate kernel owned arithmetic functions in L1 Memory" |
794 | default y |
795 | depends on !SMP |
796 | help |
797 | If enabled, arithmetic functions are linked |
798 | into L1 instruction memory. (less latency) |
799 | |
800 | config ACCESS_OK_L1 |
801 | bool "Locate access_ok function in L1 Memory" |
802 | default y |
803 | depends on !SMP |
804 | help |
805 | If enabled, the access_ok function is linked |
806 | into L1 instruction memory. (less latency) |
807 | |
808 | config MEMSET_L1 |
809 | bool "Locate memset function in L1 Memory" |
810 | default y |
811 | depends on !SMP |
812 | help |
813 | If enabled, the memset function is linked |
814 | into L1 instruction memory. (less latency) |
815 | |
816 | config MEMCPY_L1 |
817 | bool "Locate memcpy function in L1 Memory" |
818 | default y |
819 | depends on !SMP |
820 | help |
821 | If enabled, the memcpy function is linked |
822 | into L1 instruction memory. (less latency) |
823 | |
824 | config STRCMP_L1 |
825 | bool "locate strcmp function in L1 Memory" |
826 | default y |
827 | depends on !SMP |
828 | help |
829 | If enabled, the strcmp function is linked |
830 | into L1 instruction memory (less latency). |
831 | |
832 | config STRNCMP_L1 |
833 | bool "locate strncmp function in L1 Memory" |
834 | default y |
835 | depends on !SMP |
836 | help |
837 | If enabled, the strncmp function is linked |
838 | into L1 instruction memory (less latency). |
839 | |
840 | config STRCPY_L1 |
841 | bool "locate strcpy function in L1 Memory" |
842 | default y |
843 | depends on !SMP |
844 | help |
845 | If enabled, the strcpy function is linked |
846 | into L1 instruction memory (less latency). |
847 | |
848 | config STRNCPY_L1 |
849 | bool "locate strncpy function in L1 Memory" |
850 | default y |
851 | depends on !SMP |
852 | help |
853 | If enabled, the strncpy function is linked |
854 | into L1 instruction memory (less latency). |
855 | |
856 | config SYS_BFIN_SPINLOCK_L1 |
857 | bool "Locate sys_bfin_spinlock function in L1 Memory" |
858 | default y |
859 | depends on !SMP |
860 | help |
861 | If enabled, sys_bfin_spinlock function is linked |
862 | into L1 instruction memory. (less latency) |
863 | |
864 | config IP_CHECKSUM_L1 |
865 | bool "Locate IP Checksum function in L1 Memory" |
866 | default n |
867 | depends on !SMP |
868 | help |
869 | If enabled, the IP Checksum function is linked |
870 | into L1 instruction memory. (less latency) |
871 | |
872 | config CACHELINE_ALIGNED_L1 |
873 | bool "Locate cacheline_aligned data to L1 Data Memory" |
874 | default y if !BF54x |
875 | default n if BF54x |
876 | depends on !SMP && !BF531 && !CRC32 |
877 | help |
878 | If enabled, cacheline_aligned data is linked |
879 | into L1 data memory. (less latency) |
880 | |
881 | config SYSCALL_TAB_L1 |
882 | bool "Locate Syscall Table L1 Data Memory" |
883 | default n |
884 | depends on !SMP && !BF531 |
885 | help |
886 | If enabled, the Syscall LUT is linked |
887 | into L1 data memory. (less latency) |
888 | |
889 | config CPLB_SWITCH_TAB_L1 |
890 | bool "Locate CPLB Switch Tables L1 Data Memory" |
891 | default n |
892 | depends on !SMP && !BF531 |
893 | help |
894 | If enabled, the CPLB Switch Tables are linked |
895 | into L1 data memory. (less latency) |
896 | |
897 | config ICACHE_FLUSH_L1 |
898 | bool "Locate icache flush funcs in L1 Inst Memory" |
899 | default y |
900 | help |
901 | If enabled, the Blackfin icache flushing functions are linked |
902 | into L1 instruction memory. |
903 | |
904 | Note that this might be required to address anomalies, but |
905 | these functions are pretty small, so it shouldn't be too bad. |
906 | If you are using a processor affected by an anomaly, the build |
907 | system will double check for you and prevent it. |
908 | |
909 | config DCACHE_FLUSH_L1 |
910 | bool "Locate dcache flush funcs in L1 Inst Memory" |
911 | default y |
912 | depends on !SMP |
913 | help |
914 | If enabled, the Blackfin dcache flushing functions are linked |
915 | into L1 instruction memory. |
916 | |
917 | config APP_STACK_L1 |
918 | bool "Support locating application stack in L1 Scratch Memory" |
919 | default y |
920 | depends on !SMP |
921 | help |
922 | If enabled the application stack can be located in L1 |
923 | scratch memory (less latency). |
924 | |
925 | Currently only works with FLAT binaries. |
926 | |
927 | config EXCEPTION_L1_SCRATCH |
928 | bool "Locate exception stack in L1 Scratch Memory" |
929 | default n |
930 | depends on !SMP && !APP_STACK_L1 |
931 | help |
932 | Whenever an exception occurs, use the L1 Scratch memory for |
933 | stack storage. You cannot place the stacks of FLAT binaries |
934 | in L1 when using this option. |
935 | |
936 | If you don't use L1 Scratch, then you should say Y here. |
937 | |
938 | comment "Speed Optimizations" |
939 | config BFIN_INS_LOWOVERHEAD |
940 | bool "ins[bwl] low overhead, higher interrupt latency" |
941 | default y |
942 | depends on !SMP |
943 | help |
944 | Reads on the Blackfin are speculative. In Blackfin terms, this means |
945 | they can be interrupted at any time (even after they have been issued |
946 | on to the external bus), and re-issued after the interrupt occurs. |
947 | For memory - this is not a big deal, since memory does not change if |
948 | it sees a read. |
949 | |
950 | If a FIFO is sitting on the end of the read, it will see two reads, |
951 | when the core only sees one since the FIFO receives both the read |
952 | which is cancelled (and not delivered to the core) and the one which |
953 | is re-issued (which is delivered to the core). |
954 | |
955 | To solve this, interrupts are turned off before reads occur to |
956 | I/O space. This option controls which the overhead/latency of |
957 | controlling interrupts during this time |
958 | "n" turns interrupts off every read |
959 | (higher overhead, but lower interrupt latency) |
960 | "y" turns interrupts off every loop |
961 | (low overhead, but longer interrupt latency) |
962 | |
963 | default behavior is to leave this set to on (type "Y"). If you are experiencing |
964 | interrupt latency issues, it is safe and OK to turn this off. |
965 | |
966 | endmenu |
967 | |
968 | choice |
969 | prompt "Kernel executes from" |
970 | help |
971 | Choose the memory type that the kernel will be running in. |
972 | |
973 | config RAMKERNEL |
974 | bool "RAM" |
975 | help |
976 | The kernel will be resident in RAM when running. |
977 | |
978 | config ROMKERNEL |
979 | bool "ROM" |
980 | help |
981 | The kernel will be resident in FLASH/ROM when running. |
982 | |
983 | endchoice |
984 | |
985 | # Common code uses "ROMKERNEL" or "XIP_KERNEL", so define both |
986 | config XIP_KERNEL |
987 | bool |
988 | default y |
989 | depends on ROMKERNEL |
990 | |
991 | source "mm/Kconfig" |
992 | |
993 | config BFIN_GPTIMERS |
994 | tristate "Enable Blackfin General Purpose Timers API" |
995 | default n |
996 | help |
997 | Enable support for the General Purpose Timers API. If you |
998 | are unsure, say N. |
999 | |
1000 | To compile this driver as a module, choose M here: the module |
1001 | will be called gptimers. |
1002 | |
1003 | choice |
1004 | prompt "Uncached DMA region" |
1005 | default DMA_UNCACHED_1M |
1006 | config DMA_UNCACHED_32M |
1007 | bool "Enable 32M DMA region" |
1008 | config DMA_UNCACHED_16M |
1009 | bool "Enable 16M DMA region" |
1010 | config DMA_UNCACHED_8M |
1011 | bool "Enable 8M DMA region" |
1012 | config DMA_UNCACHED_4M |
1013 | bool "Enable 4M DMA region" |
1014 | config DMA_UNCACHED_2M |
1015 | bool "Enable 2M DMA region" |
1016 | config DMA_UNCACHED_1M |
1017 | bool "Enable 1M DMA region" |
1018 | config DMA_UNCACHED_512K |
1019 | bool "Enable 512K DMA region" |
1020 | config DMA_UNCACHED_256K |
1021 | bool "Enable 256K DMA region" |
1022 | config DMA_UNCACHED_128K |
1023 | bool "Enable 128K DMA region" |
1024 | config DMA_UNCACHED_NONE |
1025 | bool "Disable DMA region" |
1026 | endchoice |
1027 | |
1028 | |
1029 | comment "Cache Support" |
1030 | |
1031 | config BFIN_ICACHE |
1032 | bool "Enable ICACHE" |
1033 | default y |
1034 | config BFIN_EXTMEM_ICACHEABLE |
1035 | bool "Enable ICACHE for external memory" |
1036 | depends on BFIN_ICACHE |
1037 | default y |
1038 | config BFIN_L2_ICACHEABLE |
1039 | bool "Enable ICACHE for L2 SRAM" |
1040 | depends on BFIN_ICACHE |
1041 | depends on (BF54x || BF561 || BF60x) && !SMP |
1042 | default n |
1043 | |
1044 | config BFIN_DCACHE |
1045 | bool "Enable DCACHE" |
1046 | default y |
1047 | config BFIN_DCACHE_BANKA |
1048 | bool "Enable only 16k BankA DCACHE - BankB is SRAM" |
1049 | depends on BFIN_DCACHE && !BF531 |
1050 | default n |
1051 | config BFIN_EXTMEM_DCACHEABLE |
1052 | bool "Enable DCACHE for external memory" |
1053 | depends on BFIN_DCACHE |
1054 | default y |
1055 | choice |
1056 | prompt "External memory DCACHE policy" |
1057 | depends on BFIN_EXTMEM_DCACHEABLE |
1058 | default BFIN_EXTMEM_WRITEBACK if !SMP |
1059 | default BFIN_EXTMEM_WRITETHROUGH if SMP |
1060 | config BFIN_EXTMEM_WRITEBACK |
1061 | bool "Write back" |
1062 | depends on !SMP |
1063 | help |
1064 | Write Back Policy: |
1065 | Cached data will be written back to SDRAM only when needed. |
1066 | This can give a nice increase in performance, but beware of |
1067 | broken drivers that do not properly invalidate/flush their |
1068 | cache. |
1069 | |
1070 | Write Through Policy: |
1071 | Cached data will always be written back to SDRAM when the |
1072 | cache is updated. This is a completely safe setting, but |
1073 | performance is worse than Write Back. |
1074 | |
1075 | If you are unsure of the options and you want to be safe, |
1076 | then go with Write Through. |
1077 | |
1078 | config BFIN_EXTMEM_WRITETHROUGH |
1079 | bool "Write through" |
1080 | help |
1081 | Write Back Policy: |
1082 | Cached data will be written back to SDRAM only when needed. |
1083 | This can give a nice increase in performance, but beware of |
1084 | broken drivers that do not properly invalidate/flush their |
1085 | cache. |
1086 | |
1087 | Write Through Policy: |
1088 | Cached data will always be written back to SDRAM when the |
1089 | cache is updated. This is a completely safe setting, but |
1090 | performance is worse than Write Back. |
1091 | |
1092 | If you are unsure of the options and you want to be safe, |
1093 | then go with Write Through. |
1094 | |
1095 | endchoice |
1096 | |
1097 | config BFIN_L2_DCACHEABLE |
1098 | bool "Enable DCACHE for L2 SRAM" |
1099 | depends on BFIN_DCACHE |
1100 | depends on (BF54x || BF561 || BF60x) && !SMP |
1101 | default n |
1102 | choice |
1103 | prompt "L2 SRAM DCACHE policy" |
1104 | depends on BFIN_L2_DCACHEABLE |
1105 | default BFIN_L2_WRITEBACK |
1106 | config BFIN_L2_WRITEBACK |
1107 | bool "Write back" |
1108 | |
1109 | config BFIN_L2_WRITETHROUGH |
1110 | bool "Write through" |
1111 | endchoice |
1112 | |
1113 | |
1114 | comment "Memory Protection Unit" |
1115 | config MPU |
1116 | bool "Enable the memory protection unit" |
1117 | default n |
1118 | help |
1119 | Use the processor's MPU to protect applications from accessing |
1120 | memory they do not own. This comes at a performance penalty |
1121 | and is recommended only for debugging. |
1122 | |
1123 | comment "Asynchronous Memory Configuration" |
1124 | |
1125 | menu "EBIU_AMGCTL Global Control" |
1126 | depends on !BF60x |
1127 | config C_AMCKEN |
1128 | bool "Enable CLKOUT" |
1129 | default y |
1130 | |
1131 | config C_CDPRIO |
1132 | bool "DMA has priority over core for ext. accesses" |
1133 | default n |
1134 | |
1135 | config C_B0PEN |
1136 | depends on BF561 |
1137 | bool "Bank 0 16 bit packing enable" |
1138 | default y |
1139 | |
1140 | config C_B1PEN |
1141 | depends on BF561 |
1142 | bool "Bank 1 16 bit packing enable" |
1143 | default y |
1144 | |
1145 | config C_B2PEN |
1146 | depends on BF561 |
1147 | bool "Bank 2 16 bit packing enable" |
1148 | default y |
1149 | |
1150 | config C_B3PEN |
1151 | depends on BF561 |
1152 | bool "Bank 3 16 bit packing enable" |
1153 | default n |
1154 | |
1155 | choice |
1156 | prompt "Enable Asynchronous Memory Banks" |
1157 | default C_AMBEN_ALL |
1158 | |
1159 | config C_AMBEN |
1160 | bool "Disable All Banks" |
1161 | |
1162 | config C_AMBEN_B0 |
1163 | bool "Enable Bank 0" |
1164 | |
1165 | config C_AMBEN_B0_B1 |
1166 | bool "Enable Bank 0 & 1" |
1167 | |
1168 | config C_AMBEN_B0_B1_B2 |
1169 | bool "Enable Bank 0 & 1 & 2" |
1170 | |
1171 | config C_AMBEN_ALL |
1172 | bool "Enable All Banks" |
1173 | endchoice |
1174 | endmenu |
1175 | |
1176 | menu "EBIU_AMBCTL Control" |
1177 | depends on !BF60x |
1178 | config BANK_0 |
1179 | hex "Bank 0 (AMBCTL0.L)" |
1180 | default 0x7BB0 |
1181 | help |
1182 | These are the low 16 bits of the EBIU_AMBCTL0 MMR which are |
1183 | used to control the Asynchronous Memory Bank 0 settings. |
1184 | |
1185 | config BANK_1 |
1186 | hex "Bank 1 (AMBCTL0.H)" |
1187 | default 0x7BB0 |
1188 | default 0x5558 if BF54x |
1189 | help |
1190 | These are the high 16 bits of the EBIU_AMBCTL0 MMR which are |
1191 | used to control the Asynchronous Memory Bank 1 settings. |
1192 | |
1193 | config BANK_2 |
1194 | hex "Bank 2 (AMBCTL1.L)" |
1195 | default 0x7BB0 |
1196 | help |
1197 | These are the low 16 bits of the EBIU_AMBCTL1 MMR which are |
1198 | used to control the Asynchronous Memory Bank 2 settings. |
1199 | |
1200 | config BANK_3 |
1201 | hex "Bank 3 (AMBCTL1.H)" |
1202 | default 0x99B3 |
1203 | help |
1204 | These are the high 16 bits of the EBIU_AMBCTL1 MMR which are |
1205 | used to control the Asynchronous Memory Bank 3 settings. |
1206 | |
1207 | endmenu |
1208 | |
1209 | config EBIU_MBSCTLVAL |
1210 | hex "EBIU Bank Select Control Register" |
1211 | depends on BF54x |
1212 | default 0 |
1213 | |
1214 | config EBIU_MODEVAL |
1215 | hex "Flash Memory Mode Control Register" |
1216 | depends on BF54x |
1217 | default 1 |
1218 | |
1219 | config EBIU_FCTLVAL |
1220 | hex "Flash Memory Bank Control Register" |
1221 | depends on BF54x |
1222 | default 6 |
1223 | endmenu |
1224 | |
1225 | ############################################################################# |
1226 | menu "Bus options (PCI, PCMCIA, EISA, MCA, ISA)" |
1227 | |
1228 | config PCI |
1229 | bool "PCI support" |
1230 | depends on BROKEN |
1231 | help |
1232 | Support for PCI bus. |
1233 | |
1234 | source "drivers/pci/Kconfig" |
1235 | |
1236 | source "drivers/pcmcia/Kconfig" |
1237 | |
1238 | source "drivers/pci/hotplug/Kconfig" |
1239 | |
1240 | endmenu |
1241 | |
1242 | menu "Executable file formats" |
1243 | |
1244 | source "fs/Kconfig.binfmt" |
1245 | |
1246 | endmenu |
1247 | |
1248 | menu "Power management options" |
1249 | |
1250 | source "kernel/power/Kconfig" |
1251 | |
1252 | config ARCH_SUSPEND_POSSIBLE |
1253 | def_bool y |
1254 | |
1255 | choice |
1256 | prompt "Standby Power Saving Mode" |
1257 | depends on PM && !BF60x |
1258 | default PM_BFIN_SLEEP_DEEPER |
1259 | config PM_BFIN_SLEEP_DEEPER |
1260 | bool "Sleep Deeper" |
1261 | help |
1262 | Sleep "Deeper" Mode (High Power Savings) - This mode reduces dynamic |
1263 | power dissipation by disabling the clock to the processor core (CCLK). |
1264 | Furthermore, Standby sets the internal power supply voltage (VDDINT) |
1265 | to 0.85 V to provide the greatest power savings, while preserving the |
1266 | processor state. |
1267 | The PLL and system clock (SCLK) continue to operate at a very low |
1268 | frequency of about 3.3 MHz. To preserve data integrity in the SDRAM, |
1269 | the SDRAM is put into Self Refresh Mode. Typically an external event |
1270 | such as GPIO interrupt or RTC activity wakes up the processor. |
1271 | Various Peripherals such as UART, SPORT, PPI may not function as |
1272 | normal during Sleep Deeper, due to the reduced SCLK frequency. |
1273 | When in the sleep mode, system DMA access to L1 memory is not supported. |
1274 | |
1275 | If unsure, select "Sleep Deeper". |
1276 | |
1277 | config PM_BFIN_SLEEP |
1278 | bool "Sleep" |
1279 | help |
1280 | Sleep Mode (High Power Savings) - The sleep mode reduces power |
1281 | dissipation by disabling the clock to the processor core (CCLK). |
1282 | The PLL and system clock (SCLK), however, continue to operate in |
1283 | this mode. Typically an external event or RTC activity will wake |
1284 | up the processor. When in the sleep mode, system DMA access to L1 |
1285 | memory is not supported. |
1286 | |
1287 | If unsure, select "Sleep Deeper". |
1288 | endchoice |
1289 | |
1290 | comment "Possible Suspend Mem / Hibernate Wake-Up Sources" |
1291 | depends on PM |
1292 | |
1293 | config PM_BFIN_WAKE_PH6 |
1294 | bool "Allow Wake-Up from on-chip PHY or PH6 GP" |
1295 | depends on PM && (BF51x || BF52x || BF534 || BF536 || BF537) |
1296 | default n |
1297 | help |
1298 | Enable PHY and PH6 GP Wake-Up (Voltage Regulator Power-Up) |
1299 | |
1300 | config PM_BFIN_WAKE_GP |
1301 | bool "Allow Wake-Up from GPIOs" |
1302 | depends on PM && BF54x |
1303 | default n |
1304 | help |
1305 | Enable General-Purpose Wake-Up (Voltage Regulator Power-Up) |
1306 | (all processors, except ADSP-BF549). This option sets |
1307 | the general-purpose wake-up enable (GPWE) control bit to enable |
1308 | wake-up upon detection of an active low signal on the /GPW (PH7) pin. |
1309 | On ADSP-BF549 this option enables the same functionality on the |
1310 | /MRXON pin also PH7. |
1311 | |
1312 | config PM_BFIN_WAKE_PA15 |
1313 | bool "Allow Wake-Up from PA15" |
1314 | depends on PM && BF60x |
1315 | default n |
1316 | help |
1317 | Enable PA15 Wake-Up |
1318 | |
1319 | config PM_BFIN_WAKE_PA15_POL |
1320 | int "Wake-up priority" |
1321 | depends on PM_BFIN_WAKE_PA15 |
1322 | default 0 |
1323 | help |
1324 | Wake-Up priority 0(low) 1(high) |
1325 | |
1326 | config PM_BFIN_WAKE_PB15 |
1327 | bool "Allow Wake-Up from PB15" |
1328 | depends on PM && BF60x |
1329 | default n |
1330 | help |
1331 | Enable PB15 Wake-Up |
1332 | |
1333 | config PM_BFIN_WAKE_PB15_POL |
1334 | int "Wake-up priority" |
1335 | depends on PM_BFIN_WAKE_PB15 |
1336 | default 0 |
1337 | help |
1338 | Wake-Up priority 0(low) 1(high) |
1339 | |
1340 | config PM_BFIN_WAKE_PC15 |
1341 | bool "Allow Wake-Up from PC15" |
1342 | depends on PM && BF60x |
1343 | default n |
1344 | help |
1345 | Enable PC15 Wake-Up |
1346 | |
1347 | config PM_BFIN_WAKE_PC15_POL |
1348 | int "Wake-up priority" |
1349 | depends on PM_BFIN_WAKE_PC15 |
1350 | default 0 |
1351 | help |
1352 | Wake-Up priority 0(low) 1(high) |
1353 | |
1354 | config PM_BFIN_WAKE_PD06 |
1355 | bool "Allow Wake-Up from PD06(ETH0_PHYINT)" |
1356 | depends on PM && BF60x |
1357 | default n |
1358 | help |
1359 | Enable PD06(ETH0_PHYINT) Wake-up |
1360 | |
1361 | config PM_BFIN_WAKE_PD06_POL |
1362 | int "Wake-up priority" |
1363 | depends on PM_BFIN_WAKE_PD06 |
1364 | default 0 |
1365 | help |
1366 | Wake-Up priority 0(low) 1(high) |
1367 | |
1368 | config PM_BFIN_WAKE_PE12 |
1369 | bool "Allow Wake-Up from PE12(ETH1_PHYINT, PUSH BUTTON)" |
1370 | depends on PM && BF60x |
1371 | default n |
1372 | help |
1373 | Enable PE12(ETH1_PHYINT, PUSH BUTTON) Wake-up |
1374 | |
1375 | config PM_BFIN_WAKE_PE12_POL |
1376 | int "Wake-up priority" |
1377 | depends on PM_BFIN_WAKE_PE12 |
1378 | default 0 |
1379 | help |
1380 | Wake-Up priority 0(low) 1(high) |
1381 | |
1382 | config PM_BFIN_WAKE_PG04 |
1383 | bool "Allow Wake-Up from PG04(CAN0_RX)" |
1384 | depends on PM && BF60x |
1385 | default n |
1386 | help |
1387 | Enable PG04(CAN0_RX) Wake-up |
1388 | |
1389 | config PM_BFIN_WAKE_PG04_POL |
1390 | int "Wake-up priority" |
1391 | depends on PM_BFIN_WAKE_PG04 |
1392 | default 0 |
1393 | help |
1394 | Wake-Up priority 0(low) 1(high) |
1395 | |
1396 | config PM_BFIN_WAKE_PG13 |
1397 | bool "Allow Wake-Up from PG13" |
1398 | depends on PM && BF60x |
1399 | default n |
1400 | help |
1401 | Enable PG13 Wake-Up |
1402 | |
1403 | config PM_BFIN_WAKE_PG13_POL |
1404 | int "Wake-up priority" |
1405 | depends on PM_BFIN_WAKE_PG13 |
1406 | default 0 |
1407 | help |
1408 | Wake-Up priority 0(low) 1(high) |
1409 | |
1410 | config PM_BFIN_WAKE_USB |
1411 | bool "Allow Wake-Up from (USB)" |
1412 | depends on PM && BF60x |
1413 | default n |
1414 | help |
1415 | Enable (USB) Wake-up |
1416 | |
1417 | config PM_BFIN_WAKE_USB_POL |
1418 | int "Wake-up priority" |
1419 | depends on PM_BFIN_WAKE_USB |
1420 | default 0 |
1421 | help |
1422 | Wake-Up priority 0(low) 1(high) |
1423 | |
1424 | endmenu |
1425 | |
1426 | menu "CPU Frequency scaling" |
1427 | |
1428 | source "drivers/cpufreq/Kconfig" |
1429 | |
1430 | config BFIN_CPU_FREQ |
1431 | bool |
1432 | depends on CPU_FREQ |
1433 | select CPU_FREQ_TABLE |
1434 | default y |
1435 | |
1436 | config CPU_VOLTAGE |
1437 | bool "CPU Voltage scaling" |
1438 | depends on CPU_FREQ |
1439 | default n |
1440 | help |
1441 | Say Y here if you want CPU voltage scaling according to the CPU frequency. |
1442 | This option violates the PLL BYPASS recommendation in the Blackfin Processor |
1443 | manuals. There is a theoretical risk that during VDDINT transitions |
1444 | the PLL may unlock. |
1445 | |
1446 | endmenu |
1447 | |
1448 | source "net/Kconfig" |
1449 | |
1450 | source "drivers/Kconfig" |
1451 | |
1452 | source "drivers/firmware/Kconfig" |
1453 | |
1454 | source "fs/Kconfig" |
1455 | |
1456 | source "arch/blackfin/Kconfig.debug" |
1457 | |
1458 | source "security/Kconfig" |
1459 | |
1460 | source "crypto/Kconfig" |
1461 | |
1462 | source "lib/Kconfig" |
1463 |
Branches:
ben-wpan
ben-wpan-stefan
javiroman/ks7010
jz-2.6.34
jz-2.6.34-rc5
jz-2.6.34-rc6
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jz-3.9-rc8
jz47xx
jz47xx-2.6.38
master
Tags:
od-2011-09-04
od-2011-09-18
v2.6.34-rc5
v2.6.34-rc6
v2.6.34-rc7
v3.9