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1 | /* |
2 | * Copyright (C) ST-Ericsson SA 2010 |
3 | * |
4 | * License Terms: GNU General Public License, version 2 |
5 | * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson |
6 | */ |
7 | |
8 | #include <linux/module.h> |
9 | #include <linux/init.h> |
10 | #include <linux/platform_device.h> |
11 | #include <linux/slab.h> |
12 | #include <linux/gpio.h> |
13 | #include <linux/irq.h> |
14 | #include <linux/irqdomain.h> |
15 | #include <linux/interrupt.h> |
16 | #include <linux/of.h> |
17 | #include <linux/mfd/stmpe.h> |
18 | |
19 | /* |
20 | * These registers are modified under the irq bus lock and cached to avoid |
21 | * unnecessary writes in bus_sync_unlock. |
22 | */ |
23 | enum { REG_RE, REG_FE, REG_IE }; |
24 | |
25 | #define CACHE_NR_REGS 3 |
26 | #define CACHE_NR_BANKS (STMPE_NR_GPIOS / 8) |
27 | |
28 | struct stmpe_gpio { |
29 | struct gpio_chip chip; |
30 | struct stmpe *stmpe; |
31 | struct device *dev; |
32 | struct mutex irq_lock; |
33 | struct irq_domain *domain; |
34 | |
35 | int irq_base; |
36 | unsigned norequest_mask; |
37 | |
38 | /* Caches of interrupt control registers for bus_lock */ |
39 | u8 regs[CACHE_NR_REGS][CACHE_NR_BANKS]; |
40 | u8 oldregs[CACHE_NR_REGS][CACHE_NR_BANKS]; |
41 | }; |
42 | |
43 | static inline struct stmpe_gpio *to_stmpe_gpio(struct gpio_chip *chip) |
44 | { |
45 | return container_of(chip, struct stmpe_gpio, chip); |
46 | } |
47 | |
48 | static int stmpe_gpio_get(struct gpio_chip *chip, unsigned offset) |
49 | { |
50 | struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip); |
51 | struct stmpe *stmpe = stmpe_gpio->stmpe; |
52 | u8 reg = stmpe->regs[STMPE_IDX_GPMR_LSB] - (offset / 8); |
53 | u8 mask = 1 << (offset % 8); |
54 | int ret; |
55 | |
56 | ret = stmpe_reg_read(stmpe, reg); |
57 | if (ret < 0) |
58 | return ret; |
59 | |
60 | return !!(ret & mask); |
61 | } |
62 | |
63 | static void stmpe_gpio_set(struct gpio_chip *chip, unsigned offset, int val) |
64 | { |
65 | struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip); |
66 | struct stmpe *stmpe = stmpe_gpio->stmpe; |
67 | int which = val ? STMPE_IDX_GPSR_LSB : STMPE_IDX_GPCR_LSB; |
68 | u8 reg = stmpe->regs[which] - (offset / 8); |
69 | u8 mask = 1 << (offset % 8); |
70 | |
71 | /* |
72 | * Some variants have single register for gpio set/clear functionality. |
73 | * For them we need to write 0 to clear and 1 to set. |
74 | */ |
75 | if (stmpe->regs[STMPE_IDX_GPSR_LSB] == stmpe->regs[STMPE_IDX_GPCR_LSB]) |
76 | stmpe_set_bits(stmpe, reg, mask, val ? mask : 0); |
77 | else |
78 | stmpe_reg_write(stmpe, reg, mask); |
79 | } |
80 | |
81 | static int stmpe_gpio_direction_output(struct gpio_chip *chip, |
82 | unsigned offset, int val) |
83 | { |
84 | struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip); |
85 | struct stmpe *stmpe = stmpe_gpio->stmpe; |
86 | u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB] - (offset / 8); |
87 | u8 mask = 1 << (offset % 8); |
88 | |
89 | stmpe_gpio_set(chip, offset, val); |
90 | |
91 | return stmpe_set_bits(stmpe, reg, mask, mask); |
92 | } |
93 | |
94 | static int stmpe_gpio_direction_input(struct gpio_chip *chip, |
95 | unsigned offset) |
96 | { |
97 | struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip); |
98 | struct stmpe *stmpe = stmpe_gpio->stmpe; |
99 | u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB] - (offset / 8); |
100 | u8 mask = 1 << (offset % 8); |
101 | |
102 | return stmpe_set_bits(stmpe, reg, mask, 0); |
103 | } |
104 | |
105 | static int stmpe_gpio_to_irq(struct gpio_chip *chip, unsigned offset) |
106 | { |
107 | struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip); |
108 | |
109 | return irq_create_mapping(stmpe_gpio->domain, offset); |
110 | } |
111 | |
112 | static int stmpe_gpio_request(struct gpio_chip *chip, unsigned offset) |
113 | { |
114 | struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip); |
115 | struct stmpe *stmpe = stmpe_gpio->stmpe; |
116 | |
117 | if (stmpe_gpio->norequest_mask & (1 << offset)) |
118 | return -EINVAL; |
119 | |
120 | return stmpe_set_altfunc(stmpe, 1 << offset, STMPE_BLOCK_GPIO); |
121 | } |
122 | |
123 | static struct gpio_chip template_chip = { |
124 | .label = "stmpe", |
125 | .owner = THIS_MODULE, |
126 | .direction_input = stmpe_gpio_direction_input, |
127 | .get = stmpe_gpio_get, |
128 | .direction_output = stmpe_gpio_direction_output, |
129 | .set = stmpe_gpio_set, |
130 | .to_irq = stmpe_gpio_to_irq, |
131 | .request = stmpe_gpio_request, |
132 | .can_sleep = 1, |
133 | }; |
134 | |
135 | static int stmpe_gpio_irq_set_type(struct irq_data *d, unsigned int type) |
136 | { |
137 | struct stmpe_gpio *stmpe_gpio = irq_data_get_irq_chip_data(d); |
138 | int offset = d->hwirq; |
139 | int regoffset = offset / 8; |
140 | int mask = 1 << (offset % 8); |
141 | |
142 | if (type == IRQ_TYPE_LEVEL_LOW || type == IRQ_TYPE_LEVEL_HIGH) |
143 | return -EINVAL; |
144 | |
145 | /* STMPE801 doesn't have RE and FE registers */ |
146 | if (stmpe_gpio->stmpe->partnum == STMPE801) |
147 | return 0; |
148 | |
149 | if (type == IRQ_TYPE_EDGE_RISING) |
150 | stmpe_gpio->regs[REG_RE][regoffset] |= mask; |
151 | else |
152 | stmpe_gpio->regs[REG_RE][regoffset] &= ~mask; |
153 | |
154 | if (type == IRQ_TYPE_EDGE_FALLING) |
155 | stmpe_gpio->regs[REG_FE][regoffset] |= mask; |
156 | else |
157 | stmpe_gpio->regs[REG_FE][regoffset] &= ~mask; |
158 | |
159 | return 0; |
160 | } |
161 | |
162 | static void stmpe_gpio_irq_lock(struct irq_data *d) |
163 | { |
164 | struct stmpe_gpio *stmpe_gpio = irq_data_get_irq_chip_data(d); |
165 | |
166 | mutex_lock(&stmpe_gpio->irq_lock); |
167 | } |
168 | |
169 | static void stmpe_gpio_irq_sync_unlock(struct irq_data *d) |
170 | { |
171 | struct stmpe_gpio *stmpe_gpio = irq_data_get_irq_chip_data(d); |
172 | struct stmpe *stmpe = stmpe_gpio->stmpe; |
173 | int num_banks = DIV_ROUND_UP(stmpe->num_gpios, 8); |
174 | static const u8 regmap[] = { |
175 | [REG_RE] = STMPE_IDX_GPRER_LSB, |
176 | [REG_FE] = STMPE_IDX_GPFER_LSB, |
177 | [REG_IE] = STMPE_IDX_IEGPIOR_LSB, |
178 | }; |
179 | int i, j; |
180 | |
181 | for (i = 0; i < CACHE_NR_REGS; i++) { |
182 | /* STMPE801 doesn't have RE and FE registers */ |
183 | if ((stmpe->partnum == STMPE801) && |
184 | (i != REG_IE)) |
185 | continue; |
186 | |
187 | for (j = 0; j < num_banks; j++) { |
188 | u8 old = stmpe_gpio->oldregs[i][j]; |
189 | u8 new = stmpe_gpio->regs[i][j]; |
190 | |
191 | if (new == old) |
192 | continue; |
193 | |
194 | stmpe_gpio->oldregs[i][j] = new; |
195 | stmpe_reg_write(stmpe, stmpe->regs[regmap[i]] - j, new); |
196 | } |
197 | } |
198 | |
199 | mutex_unlock(&stmpe_gpio->irq_lock); |
200 | } |
201 | |
202 | static void stmpe_gpio_irq_mask(struct irq_data *d) |
203 | { |
204 | struct stmpe_gpio *stmpe_gpio = irq_data_get_irq_chip_data(d); |
205 | int offset = d->hwirq; |
206 | int regoffset = offset / 8; |
207 | int mask = 1 << (offset % 8); |
208 | |
209 | stmpe_gpio->regs[REG_IE][regoffset] &= ~mask; |
210 | } |
211 | |
212 | static void stmpe_gpio_irq_unmask(struct irq_data *d) |
213 | { |
214 | struct stmpe_gpio *stmpe_gpio = irq_data_get_irq_chip_data(d); |
215 | int offset = d->hwirq; |
216 | int regoffset = offset / 8; |
217 | int mask = 1 << (offset % 8); |
218 | |
219 | stmpe_gpio->regs[REG_IE][regoffset] |= mask; |
220 | } |
221 | |
222 | static struct irq_chip stmpe_gpio_irq_chip = { |
223 | .name = "stmpe-gpio", |
224 | .irq_bus_lock = stmpe_gpio_irq_lock, |
225 | .irq_bus_sync_unlock = stmpe_gpio_irq_sync_unlock, |
226 | .irq_mask = stmpe_gpio_irq_mask, |
227 | .irq_unmask = stmpe_gpio_irq_unmask, |
228 | .irq_set_type = stmpe_gpio_irq_set_type, |
229 | }; |
230 | |
231 | static irqreturn_t stmpe_gpio_irq(int irq, void *dev) |
232 | { |
233 | struct stmpe_gpio *stmpe_gpio = dev; |
234 | struct stmpe *stmpe = stmpe_gpio->stmpe; |
235 | u8 statmsbreg = stmpe->regs[STMPE_IDX_ISGPIOR_MSB]; |
236 | int num_banks = DIV_ROUND_UP(stmpe->num_gpios, 8); |
237 | u8 status[num_banks]; |
238 | int ret; |
239 | int i; |
240 | |
241 | ret = stmpe_block_read(stmpe, statmsbreg, num_banks, status); |
242 | if (ret < 0) |
243 | return IRQ_NONE; |
244 | |
245 | for (i = 0; i < num_banks; i++) { |
246 | int bank = num_banks - i - 1; |
247 | unsigned int enabled = stmpe_gpio->regs[REG_IE][bank]; |
248 | unsigned int stat = status[i]; |
249 | |
250 | stat &= enabled; |
251 | if (!stat) |
252 | continue; |
253 | |
254 | while (stat) { |
255 | int bit = __ffs(stat); |
256 | int line = bank * 8 + bit; |
257 | int virq = irq_find_mapping(stmpe_gpio->domain, line); |
258 | |
259 | handle_nested_irq(virq); |
260 | stat &= ~(1 << bit); |
261 | } |
262 | |
263 | stmpe_reg_write(stmpe, statmsbreg + i, status[i]); |
264 | |
265 | /* Edge detect register is not present on 801 */ |
266 | if (stmpe->partnum != STMPE801) |
267 | stmpe_reg_write(stmpe, stmpe->regs[STMPE_IDX_GPEDR_MSB] |
268 | + i, status[i]); |
269 | } |
270 | |
271 | return IRQ_HANDLED; |
272 | } |
273 | |
274 | static int stmpe_gpio_irq_map(struct irq_domain *d, unsigned int virq, |
275 | irq_hw_number_t hwirq) |
276 | { |
277 | struct stmpe_gpio *stmpe_gpio = d->host_data; |
278 | |
279 | if (!stmpe_gpio) |
280 | return -EINVAL; |
281 | |
282 | irq_set_chip_data(hwirq, stmpe_gpio); |
283 | irq_set_chip_and_handler(hwirq, &stmpe_gpio_irq_chip, |
284 | handle_simple_irq); |
285 | irq_set_nested_thread(hwirq, 1); |
286 | #ifdef CONFIG_ARM |
287 | set_irq_flags(hwirq, IRQF_VALID); |
288 | #else |
289 | irq_set_noprobe(hwirq); |
290 | #endif |
291 | |
292 | return 0; |
293 | } |
294 | |
295 | static void stmpe_gpio_irq_unmap(struct irq_domain *d, unsigned int virq) |
296 | { |
297 | #ifdef CONFIG_ARM |
298 | set_irq_flags(virq, 0); |
299 | #endif |
300 | irq_set_chip_and_handler(virq, NULL, NULL); |
301 | irq_set_chip_data(virq, NULL); |
302 | } |
303 | |
304 | static const struct irq_domain_ops stmpe_gpio_irq_simple_ops = { |
305 | .unmap = stmpe_gpio_irq_unmap, |
306 | .map = stmpe_gpio_irq_map, |
307 | .xlate = irq_domain_xlate_twocell, |
308 | }; |
309 | |
310 | static int stmpe_gpio_irq_init(struct stmpe_gpio *stmpe_gpio, |
311 | struct device_node *np) |
312 | { |
313 | int base = 0; |
314 | |
315 | if (!np) |
316 | base = stmpe_gpio->irq_base; |
317 | |
318 | stmpe_gpio->domain = irq_domain_add_simple(np, |
319 | stmpe_gpio->chip.ngpio, base, |
320 | &stmpe_gpio_irq_simple_ops, stmpe_gpio); |
321 | if (!stmpe_gpio->domain) { |
322 | dev_err(stmpe_gpio->dev, "failed to create irqdomain\n"); |
323 | return -ENOSYS; |
324 | } |
325 | |
326 | return 0; |
327 | } |
328 | |
329 | static int stmpe_gpio_probe(struct platform_device *pdev) |
330 | { |
331 | struct stmpe *stmpe = dev_get_drvdata(pdev->dev.parent); |
332 | struct device_node *np = pdev->dev.of_node; |
333 | struct stmpe_gpio_platform_data *pdata; |
334 | struct stmpe_gpio *stmpe_gpio; |
335 | int ret; |
336 | int irq = 0; |
337 | |
338 | pdata = stmpe->pdata->gpio; |
339 | |
340 | irq = platform_get_irq(pdev, 0); |
341 | |
342 | stmpe_gpio = kzalloc(sizeof(struct stmpe_gpio), GFP_KERNEL); |
343 | if (!stmpe_gpio) |
344 | return -ENOMEM; |
345 | |
346 | mutex_init(&stmpe_gpio->irq_lock); |
347 | |
348 | stmpe_gpio->dev = &pdev->dev; |
349 | stmpe_gpio->stmpe = stmpe; |
350 | stmpe_gpio->chip = template_chip; |
351 | stmpe_gpio->chip.ngpio = stmpe->num_gpios; |
352 | stmpe_gpio->chip.dev = &pdev->dev; |
353 | #ifdef CONFIG_OF |
354 | stmpe_gpio->chip.of_node = np; |
355 | #endif |
356 | stmpe_gpio->chip.base = pdata ? pdata->gpio_base : -1; |
357 | |
358 | if (pdata) |
359 | stmpe_gpio->norequest_mask = pdata->norequest_mask; |
360 | else if (np) |
361 | of_property_read_u32(np, "st,norequest-mask", |
362 | &stmpe_gpio->norequest_mask); |
363 | |
364 | if (irq >= 0) |
365 | stmpe_gpio->irq_base = stmpe->irq_base + STMPE_INT_GPIO(0); |
366 | else |
367 | dev_info(&pdev->dev, |
368 | "device configured in no-irq mode; " |
369 | "irqs are not available\n"); |
370 | |
371 | ret = stmpe_enable(stmpe, STMPE_BLOCK_GPIO); |
372 | if (ret) |
373 | goto out_free; |
374 | |
375 | if (irq >= 0) { |
376 | ret = stmpe_gpio_irq_init(stmpe_gpio, np); |
377 | if (ret) |
378 | goto out_disable; |
379 | |
380 | ret = request_threaded_irq(irq, NULL, stmpe_gpio_irq, |
381 | IRQF_ONESHOT, "stmpe-gpio", stmpe_gpio); |
382 | if (ret) { |
383 | dev_err(&pdev->dev, "unable to get irq: %d\n", ret); |
384 | goto out_disable; |
385 | } |
386 | } |
387 | |
388 | ret = gpiochip_add(&stmpe_gpio->chip); |
389 | if (ret) { |
390 | dev_err(&pdev->dev, "unable to add gpiochip: %d\n", ret); |
391 | goto out_freeirq; |
392 | } |
393 | |
394 | if (pdata && pdata->setup) |
395 | pdata->setup(stmpe, stmpe_gpio->chip.base); |
396 | |
397 | platform_set_drvdata(pdev, stmpe_gpio); |
398 | |
399 | return 0; |
400 | |
401 | out_freeirq: |
402 | if (irq >= 0) |
403 | free_irq(irq, stmpe_gpio); |
404 | out_disable: |
405 | stmpe_disable(stmpe, STMPE_BLOCK_GPIO); |
406 | out_free: |
407 | kfree(stmpe_gpio); |
408 | return ret; |
409 | } |
410 | |
411 | static int stmpe_gpio_remove(struct platform_device *pdev) |
412 | { |
413 | struct stmpe_gpio *stmpe_gpio = platform_get_drvdata(pdev); |
414 | struct stmpe *stmpe = stmpe_gpio->stmpe; |
415 | struct stmpe_gpio_platform_data *pdata = stmpe->pdata->gpio; |
416 | int irq = platform_get_irq(pdev, 0); |
417 | int ret; |
418 | |
419 | if (pdata && pdata->remove) |
420 | pdata->remove(stmpe, stmpe_gpio->chip.base); |
421 | |
422 | ret = gpiochip_remove(&stmpe_gpio->chip); |
423 | if (ret < 0) { |
424 | dev_err(stmpe_gpio->dev, |
425 | "unable to remove gpiochip: %d\n", ret); |
426 | return ret; |
427 | } |
428 | |
429 | stmpe_disable(stmpe, STMPE_BLOCK_GPIO); |
430 | |
431 | if (irq >= 0) |
432 | free_irq(irq, stmpe_gpio); |
433 | |
434 | kfree(stmpe_gpio); |
435 | |
436 | return 0; |
437 | } |
438 | |
439 | static struct platform_driver stmpe_gpio_driver = { |
440 | .driver.name = "stmpe-gpio", |
441 | .driver.owner = THIS_MODULE, |
442 | .probe = stmpe_gpio_probe, |
443 | .remove = stmpe_gpio_remove, |
444 | }; |
445 | |
446 | static int __init stmpe_gpio_init(void) |
447 | { |
448 | return platform_driver_register(&stmpe_gpio_driver); |
449 | } |
450 | subsys_initcall(stmpe_gpio_init); |
451 | |
452 | static void __exit stmpe_gpio_exit(void) |
453 | { |
454 | platform_driver_unregister(&stmpe_gpio_driver); |
455 | } |
456 | module_exit(stmpe_gpio_exit); |
457 | |
458 | MODULE_LICENSE("GPL v2"); |
459 | MODULE_DESCRIPTION("STMPExxxx GPIO driver"); |
460 | MODULE_AUTHOR("Rabin Vincent <rabin.vincent@stericsson.com>"); |
461 |
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