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1 | /* |
2 | * pci.h |
3 | * |
4 | * PCI defines and function prototypes |
5 | * Copyright 1994, Drew Eckhardt |
6 | * Copyright 1997--1999 Martin Mares <mj@ucw.cz> |
7 | * |
8 | * For more information, please consult the following manuals (look at |
9 | * http://www.pcisig.com/ for how to get them): |
10 | * |
11 | * PCI BIOS Specification |
12 | * PCI Local Bus Specification |
13 | * PCI to PCI Bridge Specification |
14 | * PCI System Design Guide |
15 | */ |
16 | #ifndef LINUX_PCI_H |
17 | #define LINUX_PCI_H |
18 | |
19 | |
20 | #include <linux/mod_devicetable.h> |
21 | |
22 | #include <linux/types.h> |
23 | #include <linux/init.h> |
24 | #include <linux/ioport.h> |
25 | #include <linux/list.h> |
26 | #include <linux/compiler.h> |
27 | #include <linux/errno.h> |
28 | #include <linux/kobject.h> |
29 | #include <linux/atomic.h> |
30 | #include <linux/device.h> |
31 | #include <linux/io.h> |
32 | #include <linux/irqreturn.h> |
33 | #include <uapi/linux/pci.h> |
34 | |
35 | /* Include the ID list */ |
36 | #include <linux/pci_ids.h> |
37 | |
38 | /* |
39 | * The PCI interface treats multi-function devices as independent |
40 | * devices. The slot/function address of each device is encoded |
41 | * in a single byte as follows: |
42 | * |
43 | * 7:3 = slot |
44 | * 2:0 = function |
45 | * PCI_DEVFN(), PCI_SLOT(), and PCI_FUNC() are defined uapi/linux/pci.h |
46 | * In the interest of not exposing interfaces to user-space unnecessarily, |
47 | * the following kernel only defines are being added here. |
48 | */ |
49 | #define PCI_DEVID(bus, devfn) ((((u16)bus) << 8) | devfn) |
50 | /* return bus from PCI devid = ((u16)bus_number) << 8) | devfn */ |
51 | #define PCI_BUS_NUM(x) (((x) >> 8) & 0xff) |
52 | |
53 | /* pci_slot represents a physical slot */ |
54 | struct pci_slot { |
55 | struct pci_bus *bus; /* The bus this slot is on */ |
56 | struct list_head list; /* node in list of slots on this bus */ |
57 | struct hotplug_slot *hotplug; /* Hotplug info (migrate over time) */ |
58 | unsigned char number; /* PCI_SLOT(pci_dev->devfn) */ |
59 | struct kobject kobj; |
60 | }; |
61 | |
62 | static inline const char *pci_slot_name(const struct pci_slot *slot) |
63 | { |
64 | return kobject_name(&slot->kobj); |
65 | } |
66 | |
67 | /* File state for mmap()s on /proc/bus/pci/X/Y */ |
68 | enum pci_mmap_state { |
69 | pci_mmap_io, |
70 | pci_mmap_mem |
71 | }; |
72 | |
73 | /* This defines the direction arg to the DMA mapping routines. */ |
74 | #define PCI_DMA_BIDIRECTIONAL 0 |
75 | #define PCI_DMA_TODEVICE 1 |
76 | #define PCI_DMA_FROMDEVICE 2 |
77 | #define PCI_DMA_NONE 3 |
78 | |
79 | /* |
80 | * For PCI devices, the region numbers are assigned this way: |
81 | */ |
82 | enum { |
83 | /* #0-5: standard PCI resources */ |
84 | PCI_STD_RESOURCES, |
85 | PCI_STD_RESOURCE_END = 5, |
86 | |
87 | /* #6: expansion ROM resource */ |
88 | PCI_ROM_RESOURCE, |
89 | |
90 | /* device specific resources */ |
91 | #ifdef CONFIG_PCI_IOV |
92 | PCI_IOV_RESOURCES, |
93 | PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1, |
94 | #endif |
95 | |
96 | /* resources assigned to buses behind the bridge */ |
97 | #define PCI_BRIDGE_RESOURCE_NUM 4 |
98 | |
99 | PCI_BRIDGE_RESOURCES, |
100 | PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES + |
101 | PCI_BRIDGE_RESOURCE_NUM - 1, |
102 | |
103 | /* total resources associated with a PCI device */ |
104 | PCI_NUM_RESOURCES, |
105 | |
106 | /* preserve this for compatibility */ |
107 | DEVICE_COUNT_RESOURCE = PCI_NUM_RESOURCES, |
108 | }; |
109 | |
110 | typedef int __bitwise pci_power_t; |
111 | |
112 | #define PCI_D0 ((pci_power_t __force) 0) |
113 | #define PCI_D1 ((pci_power_t __force) 1) |
114 | #define PCI_D2 ((pci_power_t __force) 2) |
115 | #define PCI_D3hot ((pci_power_t __force) 3) |
116 | #define PCI_D3cold ((pci_power_t __force) 4) |
117 | #define PCI_UNKNOWN ((pci_power_t __force) 5) |
118 | #define PCI_POWER_ERROR ((pci_power_t __force) -1) |
119 | |
120 | /* Remember to update this when the list above changes! */ |
121 | extern const char *pci_power_names[]; |
122 | |
123 | static inline const char *pci_power_name(pci_power_t state) |
124 | { |
125 | return pci_power_names[1 + (int) state]; |
126 | } |
127 | |
128 | #define PCI_PM_D2_DELAY 200 |
129 | #define PCI_PM_D3_WAIT 10 |
130 | #define PCI_PM_D3COLD_WAIT 100 |
131 | #define PCI_PM_BUS_WAIT 50 |
132 | |
133 | /** The pci_channel state describes connectivity between the CPU and |
134 | * the pci device. If some PCI bus between here and the pci device |
135 | * has crashed or locked up, this info is reflected here. |
136 | */ |
137 | typedef unsigned int __bitwise pci_channel_state_t; |
138 | |
139 | enum pci_channel_state { |
140 | /* I/O channel is in normal state */ |
141 | pci_channel_io_normal = (__force pci_channel_state_t) 1, |
142 | |
143 | /* I/O to channel is blocked */ |
144 | pci_channel_io_frozen = (__force pci_channel_state_t) 2, |
145 | |
146 | /* PCI card is dead */ |
147 | pci_channel_io_perm_failure = (__force pci_channel_state_t) 3, |
148 | }; |
149 | |
150 | typedef unsigned int __bitwise pcie_reset_state_t; |
151 | |
152 | enum pcie_reset_state { |
153 | /* Reset is NOT asserted (Use to deassert reset) */ |
154 | pcie_deassert_reset = (__force pcie_reset_state_t) 1, |
155 | |
156 | /* Use #PERST to reset PCI-E device */ |
157 | pcie_warm_reset = (__force pcie_reset_state_t) 2, |
158 | |
159 | /* Use PCI-E Hot Reset to reset device */ |
160 | pcie_hot_reset = (__force pcie_reset_state_t) 3 |
161 | }; |
162 | |
163 | typedef unsigned short __bitwise pci_dev_flags_t; |
164 | enum pci_dev_flags { |
165 | /* INTX_DISABLE in PCI_COMMAND register disables MSI |
166 | * generation too. |
167 | */ |
168 | PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) 1, |
169 | /* Device configuration is irrevocably lost if disabled into D3 */ |
170 | PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) 2, |
171 | /* Provide indication device is assigned by a Virtual Machine Manager */ |
172 | PCI_DEV_FLAGS_ASSIGNED = (__force pci_dev_flags_t) 4, |
173 | }; |
174 | |
175 | enum pci_irq_reroute_variant { |
176 | INTEL_IRQ_REROUTE_VARIANT = 1, |
177 | MAX_IRQ_REROUTE_VARIANTS = 3 |
178 | }; |
179 | |
180 | typedef unsigned short __bitwise pci_bus_flags_t; |
181 | enum pci_bus_flags { |
182 | PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1, |
183 | PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2, |
184 | }; |
185 | |
186 | /* Based on the PCI Hotplug Spec, but some values are made up by us */ |
187 | enum pci_bus_speed { |
188 | PCI_SPEED_33MHz = 0x00, |
189 | PCI_SPEED_66MHz = 0x01, |
190 | PCI_SPEED_66MHz_PCIX = 0x02, |
191 | PCI_SPEED_100MHz_PCIX = 0x03, |
192 | PCI_SPEED_133MHz_PCIX = 0x04, |
193 | PCI_SPEED_66MHz_PCIX_ECC = 0x05, |
194 | PCI_SPEED_100MHz_PCIX_ECC = 0x06, |
195 | PCI_SPEED_133MHz_PCIX_ECC = 0x07, |
196 | PCI_SPEED_66MHz_PCIX_266 = 0x09, |
197 | PCI_SPEED_100MHz_PCIX_266 = 0x0a, |
198 | PCI_SPEED_133MHz_PCIX_266 = 0x0b, |
199 | AGP_UNKNOWN = 0x0c, |
200 | AGP_1X = 0x0d, |
201 | AGP_2X = 0x0e, |
202 | AGP_4X = 0x0f, |
203 | AGP_8X = 0x10, |
204 | PCI_SPEED_66MHz_PCIX_533 = 0x11, |
205 | PCI_SPEED_100MHz_PCIX_533 = 0x12, |
206 | PCI_SPEED_133MHz_PCIX_533 = 0x13, |
207 | PCIE_SPEED_2_5GT = 0x14, |
208 | PCIE_SPEED_5_0GT = 0x15, |
209 | PCIE_SPEED_8_0GT = 0x16, |
210 | PCI_SPEED_UNKNOWN = 0xff, |
211 | }; |
212 | |
213 | struct pci_cap_saved_data { |
214 | char cap_nr; |
215 | unsigned int size; |
216 | u32 data[0]; |
217 | }; |
218 | |
219 | struct pci_cap_saved_state { |
220 | struct hlist_node next; |
221 | struct pci_cap_saved_data cap; |
222 | }; |
223 | |
224 | struct pcie_link_state; |
225 | struct pci_vpd; |
226 | struct pci_sriov; |
227 | struct pci_ats; |
228 | |
229 | /* |
230 | * The pci_dev structure is used to describe PCI devices. |
231 | */ |
232 | struct pci_dev { |
233 | struct list_head bus_list; /* node in per-bus list */ |
234 | struct pci_bus *bus; /* bus this device is on */ |
235 | struct pci_bus *subordinate; /* bus this device bridges to */ |
236 | |
237 | void *sysdata; /* hook for sys-specific extension */ |
238 | struct proc_dir_entry *procent; /* device entry in /proc/bus/pci */ |
239 | struct pci_slot *slot; /* Physical slot this device is in */ |
240 | |
241 | unsigned int devfn; /* encoded device & function index */ |
242 | unsigned short vendor; |
243 | unsigned short device; |
244 | unsigned short subsystem_vendor; |
245 | unsigned short subsystem_device; |
246 | unsigned int class; /* 3 bytes: (base,sub,prog-if) */ |
247 | u8 revision; /* PCI revision, low byte of class word */ |
248 | u8 hdr_type; /* PCI header type (`multi' flag masked out) */ |
249 | u8 pcie_cap; /* PCI-E capability offset */ |
250 | u8 msi_cap; /* MSI capability offset */ |
251 | u8 msix_cap; /* MSI-X capability offset */ |
252 | u8 pcie_mpss:3; /* PCI-E Max Payload Size Supported */ |
253 | u8 rom_base_reg; /* which config register controls the ROM */ |
254 | u8 pin; /* which interrupt pin this device uses */ |
255 | u16 pcie_flags_reg; /* cached PCI-E Capabilities Register */ |
256 | |
257 | struct pci_driver *driver; /* which driver has allocated this device */ |
258 | u64 dma_mask; /* Mask of the bits of bus address this |
259 | device implements. Normally this is |
260 | 0xffffffff. You only need to change |
261 | this if your device has broken DMA |
262 | or supports 64-bit transfers. */ |
263 | |
264 | struct device_dma_parameters dma_parms; |
265 | |
266 | pci_power_t current_state; /* Current operating state. In ACPI-speak, |
267 | this is D0-D3, D0 being fully functional, |
268 | and D3 being off. */ |
269 | u8 pm_cap; /* PM capability offset */ |
270 | unsigned int pme_support:5; /* Bitmask of states from which PME# |
271 | can be generated */ |
272 | unsigned int pme_interrupt:1; |
273 | unsigned int pme_poll:1; /* Poll device's PME status bit */ |
274 | unsigned int d1_support:1; /* Low power state D1 is supported */ |
275 | unsigned int d2_support:1; /* Low power state D2 is supported */ |
276 | unsigned int no_d1d2:1; /* D1 and D2 are forbidden */ |
277 | unsigned int no_d3cold:1; /* D3cold is forbidden */ |
278 | unsigned int d3cold_allowed:1; /* D3cold is allowed by user */ |
279 | unsigned int mmio_always_on:1; /* disallow turning off io/mem |
280 | decoding during bar sizing */ |
281 | unsigned int wakeup_prepared:1; |
282 | unsigned int runtime_d3cold:1; /* whether go through runtime |
283 | D3cold, not set for devices |
284 | powered on/off by the |
285 | corresponding bridge */ |
286 | unsigned int d3_delay; /* D3->D0 transition time in ms */ |
287 | unsigned int d3cold_delay; /* D3cold->D0 transition time in ms */ |
288 | |
289 | #ifdef CONFIG_PCIEASPM |
290 | struct pcie_link_state *link_state; /* ASPM link state. */ |
291 | #endif |
292 | |
293 | pci_channel_state_t error_state; /* current connectivity state */ |
294 | struct device dev; /* Generic device interface */ |
295 | |
296 | int cfg_size; /* Size of configuration space */ |
297 | |
298 | /* |
299 | * Instead of touching interrupt line and base address registers |
300 | * directly, use the values stored here. They might be different! |
301 | */ |
302 | unsigned int irq; |
303 | struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */ |
304 | |
305 | bool match_driver; /* Skip attaching driver */ |
306 | /* These fields are used by common fixups */ |
307 | unsigned int transparent:1; /* Transparent PCI bridge */ |
308 | unsigned int multifunction:1;/* Part of multi-function device */ |
309 | /* keep track of device state */ |
310 | unsigned int is_added:1; |
311 | unsigned int is_busmaster:1; /* device is busmaster */ |
312 | unsigned int no_msi:1; /* device may not use msi */ |
313 | unsigned int block_cfg_access:1; /* config space access is blocked */ |
314 | unsigned int broken_parity_status:1; /* Device generates false positive parity */ |
315 | unsigned int irq_reroute_variant:2; /* device needs IRQ rerouting variant */ |
316 | unsigned int msi_enabled:1; |
317 | unsigned int msix_enabled:1; |
318 | unsigned int ari_enabled:1; /* ARI forwarding */ |
319 | unsigned int is_managed:1; |
320 | unsigned int is_pcie:1; /* Obsolete. Will be removed. |
321 | Use pci_is_pcie() instead */ |
322 | unsigned int needs_freset:1; /* Dev requires fundamental reset */ |
323 | unsigned int state_saved:1; |
324 | unsigned int is_physfn:1; |
325 | unsigned int is_virtfn:1; |
326 | unsigned int reset_fn:1; |
327 | unsigned int is_hotplug_bridge:1; |
328 | unsigned int __aer_firmware_first_valid:1; |
329 | unsigned int __aer_firmware_first:1; |
330 | unsigned int broken_intx_masking:1; |
331 | unsigned int io_window_1k:1; /* Intel P2P bridge 1K I/O windows */ |
332 | pci_dev_flags_t dev_flags; |
333 | atomic_t enable_cnt; /* pci_enable_device has been called */ |
334 | |
335 | u32 saved_config_space[16]; /* config space saved at suspend time */ |
336 | struct hlist_head saved_cap_space; |
337 | struct bin_attribute *rom_attr; /* attribute descriptor for sysfs ROM entry */ |
338 | int rom_attr_enabled; /* has display of the rom attribute been enabled? */ |
339 | struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */ |
340 | struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */ |
341 | #ifdef CONFIG_PCI_MSI |
342 | struct list_head msi_list; |
343 | struct kset *msi_kset; |
344 | #endif |
345 | struct pci_vpd *vpd; |
346 | #ifdef CONFIG_PCI_ATS |
347 | union { |
348 | struct pci_sriov *sriov; /* SR-IOV capability related */ |
349 | struct pci_dev *physfn; /* the PF this VF is associated with */ |
350 | }; |
351 | struct pci_ats *ats; /* Address Translation Service */ |
352 | #endif |
353 | phys_addr_t rom; /* Physical address of ROM if it's not from the BAR */ |
354 | size_t romlen; /* Length of ROM if it's not from the BAR */ |
355 | }; |
356 | |
357 | static inline struct pci_dev *pci_physfn(struct pci_dev *dev) |
358 | { |
359 | #ifdef CONFIG_PCI_IOV |
360 | if (dev->is_virtfn) |
361 | dev = dev->physfn; |
362 | #endif |
363 | |
364 | return dev; |
365 | } |
366 | |
367 | struct pci_dev *pci_alloc_dev(struct pci_bus *bus); |
368 | struct pci_dev * __deprecated alloc_pci_dev(void); |
369 | |
370 | #define to_pci_dev(n) container_of(n, struct pci_dev, dev) |
371 | #define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL) |
372 | |
373 | static inline int pci_channel_offline(struct pci_dev *pdev) |
374 | { |
375 | return (pdev->error_state != pci_channel_io_normal); |
376 | } |
377 | |
378 | extern struct resource busn_resource; |
379 | |
380 | struct pci_host_bridge_window { |
381 | struct list_head list; |
382 | struct resource *res; /* host bridge aperture (CPU address) */ |
383 | resource_size_t offset; /* bus address + offset = CPU address */ |
384 | }; |
385 | |
386 | struct pci_host_bridge { |
387 | struct device dev; |
388 | struct pci_bus *bus; /* root bus */ |
389 | struct list_head windows; /* pci_host_bridge_windows */ |
390 | void (*release_fn)(struct pci_host_bridge *); |
391 | void *release_data; |
392 | }; |
393 | |
394 | #define to_pci_host_bridge(n) container_of(n, struct pci_host_bridge, dev) |
395 | void pci_set_host_bridge_release(struct pci_host_bridge *bridge, |
396 | void (*release_fn)(struct pci_host_bridge *), |
397 | void *release_data); |
398 | |
399 | int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge); |
400 | |
401 | /* |
402 | * The first PCI_BRIDGE_RESOURCE_NUM PCI bus resources (those that correspond |
403 | * to P2P or CardBus bridge windows) go in a table. Additional ones (for |
404 | * buses below host bridges or subtractive decode bridges) go in the list. |
405 | * Use pci_bus_for_each_resource() to iterate through all the resources. |
406 | */ |
407 | |
408 | /* |
409 | * PCI_SUBTRACTIVE_DECODE means the bridge forwards the window implicitly |
410 | * and there's no way to program the bridge with the details of the window. |
411 | * This does not apply to ACPI _CRS windows, even with the _DEC subtractive- |
412 | * decode bit set, because they are explicit and can be programmed with _SRS. |
413 | */ |
414 | #define PCI_SUBTRACTIVE_DECODE 0x1 |
415 | |
416 | struct pci_bus_resource { |
417 | struct list_head list; |
418 | struct resource *res; |
419 | unsigned int flags; |
420 | }; |
421 | |
422 | #define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */ |
423 | |
424 | struct pci_bus { |
425 | struct list_head node; /* node in list of buses */ |
426 | struct pci_bus *parent; /* parent bus this bridge is on */ |
427 | struct list_head children; /* list of child buses */ |
428 | struct list_head devices; /* list of devices on this bus */ |
429 | struct pci_dev *self; /* bridge device as seen by parent */ |
430 | struct list_head slots; /* list of slots on this bus */ |
431 | struct resource *resource[PCI_BRIDGE_RESOURCE_NUM]; |
432 | struct list_head resources; /* address space routed to this bus */ |
433 | struct resource busn_res; /* bus numbers routed to this bus */ |
434 | |
435 | struct pci_ops *ops; /* configuration access functions */ |
436 | void *sysdata; /* hook for sys-specific extension */ |
437 | struct proc_dir_entry *procdir; /* directory entry in /proc/bus/pci */ |
438 | |
439 | unsigned char number; /* bus number */ |
440 | unsigned char primary; /* number of primary bridge */ |
441 | unsigned char max_bus_speed; /* enum pci_bus_speed */ |
442 | unsigned char cur_bus_speed; /* enum pci_bus_speed */ |
443 | |
444 | char name[48]; |
445 | |
446 | unsigned short bridge_ctl; /* manage NO_ISA/FBB/et al behaviors */ |
447 | pci_bus_flags_t bus_flags; /* Inherited by child busses */ |
448 | struct device *bridge; |
449 | struct device dev; |
450 | struct bin_attribute *legacy_io; /* legacy I/O for this bus */ |
451 | struct bin_attribute *legacy_mem; /* legacy mem */ |
452 | unsigned int is_added:1; |
453 | }; |
454 | |
455 | #define pci_bus_b(n) list_entry(n, struct pci_bus, node) |
456 | #define to_pci_bus(n) container_of(n, struct pci_bus, dev) |
457 | |
458 | /* |
459 | * Returns true if the pci bus is root (behind host-pci bridge), |
460 | * false otherwise |
461 | */ |
462 | static inline bool pci_is_root_bus(struct pci_bus *pbus) |
463 | { |
464 | return !(pbus->parent); |
465 | } |
466 | |
467 | #ifdef CONFIG_PCI_MSI |
468 | static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) |
469 | { |
470 | return pci_dev->msi_enabled || pci_dev->msix_enabled; |
471 | } |
472 | #else |
473 | static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; } |
474 | #endif |
475 | |
476 | /* |
477 | * Error values that may be returned by PCI functions. |
478 | */ |
479 | #define PCIBIOS_SUCCESSFUL 0x00 |
480 | #define PCIBIOS_FUNC_NOT_SUPPORTED 0x81 |
481 | #define PCIBIOS_BAD_VENDOR_ID 0x83 |
482 | #define PCIBIOS_DEVICE_NOT_FOUND 0x86 |
483 | #define PCIBIOS_BAD_REGISTER_NUMBER 0x87 |
484 | #define PCIBIOS_SET_FAILED 0x88 |
485 | #define PCIBIOS_BUFFER_TOO_SMALL 0x89 |
486 | |
487 | /* |
488 | * Translate above to generic errno for passing back through non-pci. |
489 | */ |
490 | static inline int pcibios_err_to_errno(int err) |
491 | { |
492 | if (err <= PCIBIOS_SUCCESSFUL) |
493 | return err; /* Assume already errno */ |
494 | |
495 | switch (err) { |
496 | case PCIBIOS_FUNC_NOT_SUPPORTED: |
497 | return -ENOENT; |
498 | case PCIBIOS_BAD_VENDOR_ID: |
499 | return -EINVAL; |
500 | case PCIBIOS_DEVICE_NOT_FOUND: |
501 | return -ENODEV; |
502 | case PCIBIOS_BAD_REGISTER_NUMBER: |
503 | return -EFAULT; |
504 | case PCIBIOS_SET_FAILED: |
505 | return -EIO; |
506 | case PCIBIOS_BUFFER_TOO_SMALL: |
507 | return -ENOSPC; |
508 | } |
509 | |
510 | return -ENOTTY; |
511 | } |
512 | |
513 | /* Low-level architecture-dependent routines */ |
514 | |
515 | struct pci_ops { |
516 | int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val); |
517 | int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val); |
518 | }; |
519 | |
520 | /* |
521 | * ACPI needs to be able to access PCI config space before we've done a |
522 | * PCI bus scan and created pci_bus structures. |
523 | */ |
524 | int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn, |
525 | int reg, int len, u32 *val); |
526 | int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn, |
527 | int reg, int len, u32 val); |
528 | |
529 | struct pci_bus_region { |
530 | resource_size_t start; |
531 | resource_size_t end; |
532 | }; |
533 | |
534 | struct pci_dynids { |
535 | spinlock_t lock; /* protects list, index */ |
536 | struct list_head list; /* for IDs added at runtime */ |
537 | }; |
538 | |
539 | /* ---------------------------------------------------------------- */ |
540 | /** PCI Error Recovery System (PCI-ERS). If a PCI device driver provides |
541 | * a set of callbacks in struct pci_error_handlers, then that device driver |
542 | * will be notified of PCI bus errors, and will be driven to recovery |
543 | * when an error occurs. |
544 | */ |
545 | |
546 | typedef unsigned int __bitwise pci_ers_result_t; |
547 | |
548 | enum pci_ers_result { |
549 | /* no result/none/not supported in device driver */ |
550 | PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1, |
551 | |
552 | /* Device driver can recover without slot reset */ |
553 | PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2, |
554 | |
555 | /* Device driver wants slot to be reset. */ |
556 | PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3, |
557 | |
558 | /* Device has completely failed, is unrecoverable */ |
559 | PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4, |
560 | |
561 | /* Device driver is fully recovered and operational */ |
562 | PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5, |
563 | |
564 | /* No AER capabilities registered for the driver */ |
565 | PCI_ERS_RESULT_NO_AER_DRIVER = (__force pci_ers_result_t) 6, |
566 | }; |
567 | |
568 | /* PCI bus error event callbacks */ |
569 | struct pci_error_handlers { |
570 | /* PCI bus error detected on this device */ |
571 | pci_ers_result_t (*error_detected)(struct pci_dev *dev, |
572 | enum pci_channel_state error); |
573 | |
574 | /* MMIO has been re-enabled, but not DMA */ |
575 | pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev); |
576 | |
577 | /* PCI Express link has been reset */ |
578 | pci_ers_result_t (*link_reset)(struct pci_dev *dev); |
579 | |
580 | /* PCI slot has been reset */ |
581 | pci_ers_result_t (*slot_reset)(struct pci_dev *dev); |
582 | |
583 | /* Device driver may resume normal operations */ |
584 | void (*resume)(struct pci_dev *dev); |
585 | }; |
586 | |
587 | /* ---------------------------------------------------------------- */ |
588 | |
589 | struct module; |
590 | struct pci_driver { |
591 | struct list_head node; |
592 | const char *name; |
593 | const struct pci_device_id *id_table; /* must be non-NULL for probe to be called */ |
594 | int (*probe) (struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */ |
595 | void (*remove) (struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */ |
596 | int (*suspend) (struct pci_dev *dev, pm_message_t state); /* Device suspended */ |
597 | int (*suspend_late) (struct pci_dev *dev, pm_message_t state); |
598 | int (*resume_early) (struct pci_dev *dev); |
599 | int (*resume) (struct pci_dev *dev); /* Device woken up */ |
600 | void (*shutdown) (struct pci_dev *dev); |
601 | int (*sriov_configure) (struct pci_dev *dev, int num_vfs); /* PF pdev */ |
602 | const struct pci_error_handlers *err_handler; |
603 | struct device_driver driver; |
604 | struct pci_dynids dynids; |
605 | }; |
606 | |
607 | #define to_pci_driver(drv) container_of(drv, struct pci_driver, driver) |
608 | |
609 | /** |
610 | * DEFINE_PCI_DEVICE_TABLE - macro used to describe a pci device table |
611 | * @_table: device table name |
612 | * |
613 | * This macro is used to create a struct pci_device_id array (a device table) |
614 | * in a generic manner. |
615 | */ |
616 | #define DEFINE_PCI_DEVICE_TABLE(_table) \ |
617 | const struct pci_device_id _table[] |
618 | |
619 | /** |
620 | * PCI_DEVICE - macro used to describe a specific pci device |
621 | * @vend: the 16 bit PCI Vendor ID |
622 | * @dev: the 16 bit PCI Device ID |
623 | * |
624 | * This macro is used to create a struct pci_device_id that matches a |
625 | * specific device. The subvendor and subdevice fields will be set to |
626 | * PCI_ANY_ID. |
627 | */ |
628 | #define PCI_DEVICE(vend,dev) \ |
629 | .vendor = (vend), .device = (dev), \ |
630 | .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID |
631 | |
632 | /** |
633 | * PCI_DEVICE_SUB - macro used to describe a specific pci device with subsystem |
634 | * @vend: the 16 bit PCI Vendor ID |
635 | * @dev: the 16 bit PCI Device ID |
636 | * @subvend: the 16 bit PCI Subvendor ID |
637 | * @subdev: the 16 bit PCI Subdevice ID |
638 | * |
639 | * This macro is used to create a struct pci_device_id that matches a |
640 | * specific device with subsystem information. |
641 | */ |
642 | #define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \ |
643 | .vendor = (vend), .device = (dev), \ |
644 | .subvendor = (subvend), .subdevice = (subdev) |
645 | |
646 | /** |
647 | * PCI_DEVICE_CLASS - macro used to describe a specific pci device class |
648 | * @dev_class: the class, subclass, prog-if triple for this device |
649 | * @dev_class_mask: the class mask for this device |
650 | * |
651 | * This macro is used to create a struct pci_device_id that matches a |
652 | * specific PCI class. The vendor, device, subvendor, and subdevice |
653 | * fields will be set to PCI_ANY_ID. |
654 | */ |
655 | #define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \ |
656 | .class = (dev_class), .class_mask = (dev_class_mask), \ |
657 | .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \ |
658 | .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID |
659 | |
660 | /** |
661 | * PCI_VDEVICE - macro used to describe a specific pci device in short form |
662 | * @vendor: the vendor name |
663 | * @device: the 16 bit PCI Device ID |
664 | * |
665 | * This macro is used to create a struct pci_device_id that matches a |
666 | * specific PCI device. The subvendor, and subdevice fields will be set |
667 | * to PCI_ANY_ID. The macro allows the next field to follow as the device |
668 | * private data. |
669 | */ |
670 | |
671 | #define PCI_VDEVICE(vendor, device) \ |
672 | PCI_VENDOR_ID_##vendor, (device), \ |
673 | PCI_ANY_ID, PCI_ANY_ID, 0, 0 |
674 | |
675 | /* these external functions are only available when PCI support is enabled */ |
676 | #ifdef CONFIG_PCI |
677 | |
678 | void pcie_bus_configure_settings(struct pci_bus *bus, u8 smpss); |
679 | |
680 | enum pcie_bus_config_types { |
681 | PCIE_BUS_TUNE_OFF, |
682 | PCIE_BUS_SAFE, |
683 | PCIE_BUS_PERFORMANCE, |
684 | PCIE_BUS_PEER2PEER, |
685 | }; |
686 | |
687 | extern enum pcie_bus_config_types pcie_bus_config; |
688 | |
689 | extern struct bus_type pci_bus_type; |
690 | |
691 | /* Do NOT directly access these two variables, unless you are arch specific pci |
692 | * code, or pci core code. */ |
693 | extern struct list_head pci_root_buses; /* list of all known PCI buses */ |
694 | /* Some device drivers need know if pci is initiated */ |
695 | int no_pci_devices(void); |
696 | |
697 | void pcibios_resource_survey_bus(struct pci_bus *bus); |
698 | void pcibios_add_bus(struct pci_bus *bus); |
699 | void pcibios_remove_bus(struct pci_bus *bus); |
700 | void pcibios_fixup_bus(struct pci_bus *); |
701 | int __must_check pcibios_enable_device(struct pci_dev *, int mask); |
702 | /* Architecture specific versions may override this (weak) */ |
703 | char *pcibios_setup(char *str); |
704 | |
705 | /* Used only when drivers/pci/setup.c is used */ |
706 | resource_size_t pcibios_align_resource(void *, const struct resource *, |
707 | resource_size_t, |
708 | resource_size_t); |
709 | void pcibios_update_irq(struct pci_dev *, int irq); |
710 | |
711 | /* Weak but can be overriden by arch */ |
712 | void pci_fixup_cardbus(struct pci_bus *); |
713 | |
714 | /* Generic PCI functions used internally */ |
715 | |
716 | void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region, |
717 | struct resource *res); |
718 | void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res, |
719 | struct pci_bus_region *region); |
720 | void pcibios_scan_specific_bus(int busn); |
721 | struct pci_bus *pci_find_bus(int domain, int busnr); |
722 | void pci_bus_add_devices(const struct pci_bus *bus); |
723 | struct pci_bus *pci_scan_bus_parented(struct device *parent, int bus, |
724 | struct pci_ops *ops, void *sysdata); |
725 | struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata); |
726 | struct pci_bus *pci_create_root_bus(struct device *parent, int bus, |
727 | struct pci_ops *ops, void *sysdata, |
728 | struct list_head *resources); |
729 | int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int busmax); |
730 | int pci_bus_update_busn_res_end(struct pci_bus *b, int busmax); |
731 | void pci_bus_release_busn_res(struct pci_bus *b); |
732 | struct pci_bus *pci_scan_root_bus(struct device *parent, int bus, |
733 | struct pci_ops *ops, void *sysdata, |
734 | struct list_head *resources); |
735 | struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, |
736 | int busnr); |
737 | void pcie_update_link_speed(struct pci_bus *bus, u16 link_status); |
738 | struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr, |
739 | const char *name, |
740 | struct hotplug_slot *hotplug); |
741 | void pci_destroy_slot(struct pci_slot *slot); |
742 | void pci_renumber_slot(struct pci_slot *slot, int slot_nr); |
743 | int pci_scan_slot(struct pci_bus *bus, int devfn); |
744 | struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn); |
745 | void pci_device_add(struct pci_dev *dev, struct pci_bus *bus); |
746 | unsigned int pci_scan_child_bus(struct pci_bus *bus); |
747 | int __must_check pci_bus_add_device(struct pci_dev *dev); |
748 | void pci_read_bridge_bases(struct pci_bus *child); |
749 | struct resource *pci_find_parent_resource(const struct pci_dev *dev, |
750 | struct resource *res); |
751 | u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin); |
752 | int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge); |
753 | u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp); |
754 | struct pci_dev *pci_dev_get(struct pci_dev *dev); |
755 | void pci_dev_put(struct pci_dev *dev); |
756 | void pci_remove_bus(struct pci_bus *b); |
757 | void pci_stop_and_remove_bus_device(struct pci_dev *dev); |
758 | void pci_stop_root_bus(struct pci_bus *bus); |
759 | void pci_remove_root_bus(struct pci_bus *bus); |
760 | void pci_setup_cardbus(struct pci_bus *bus); |
761 | void pci_sort_breadthfirst(void); |
762 | #define dev_is_pci(d) ((d)->bus == &pci_bus_type) |
763 | #define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false)) |
764 | #define dev_num_vf(d) ((dev_is_pci(d) ? pci_num_vf(to_pci_dev(d)) : 0)) |
765 | |
766 | /* Generic PCI functions exported to card drivers */ |
767 | |
768 | enum pci_lost_interrupt_reason { |
769 | PCI_LOST_IRQ_NO_INFORMATION = 0, |
770 | PCI_LOST_IRQ_DISABLE_MSI, |
771 | PCI_LOST_IRQ_DISABLE_MSIX, |
772 | PCI_LOST_IRQ_DISABLE_ACPI, |
773 | }; |
774 | enum pci_lost_interrupt_reason pci_lost_interrupt(struct pci_dev *dev); |
775 | int pci_find_capability(struct pci_dev *dev, int cap); |
776 | int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap); |
777 | int pci_find_ext_capability(struct pci_dev *dev, int cap); |
778 | int pci_find_next_ext_capability(struct pci_dev *dev, int pos, int cap); |
779 | int pci_find_ht_capability(struct pci_dev *dev, int ht_cap); |
780 | int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap); |
781 | struct pci_bus *pci_find_next_bus(const struct pci_bus *from); |
782 | |
783 | struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device, |
784 | struct pci_dev *from); |
785 | struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device, |
786 | unsigned int ss_vendor, unsigned int ss_device, |
787 | struct pci_dev *from); |
788 | struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn); |
789 | struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus, |
790 | unsigned int devfn); |
791 | static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus, |
792 | unsigned int devfn) |
793 | { |
794 | return pci_get_domain_bus_and_slot(0, bus, devfn); |
795 | } |
796 | struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from); |
797 | int pci_dev_present(const struct pci_device_id *ids); |
798 | |
799 | int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn, |
800 | int where, u8 *val); |
801 | int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn, |
802 | int where, u16 *val); |
803 | int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn, |
804 | int where, u32 *val); |
805 | int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn, |
806 | int where, u8 val); |
807 | int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn, |
808 | int where, u16 val); |
809 | int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn, |
810 | int where, u32 val); |
811 | struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops); |
812 | |
813 | static inline int pci_read_config_byte(const struct pci_dev *dev, int where, u8 *val) |
814 | { |
815 | return pci_bus_read_config_byte(dev->bus, dev->devfn, where, val); |
816 | } |
817 | static inline int pci_read_config_word(const struct pci_dev *dev, int where, u16 *val) |
818 | { |
819 | return pci_bus_read_config_word(dev->bus, dev->devfn, where, val); |
820 | } |
821 | static inline int pci_read_config_dword(const struct pci_dev *dev, int where, |
822 | u32 *val) |
823 | { |
824 | return pci_bus_read_config_dword(dev->bus, dev->devfn, where, val); |
825 | } |
826 | static inline int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val) |
827 | { |
828 | return pci_bus_write_config_byte(dev->bus, dev->devfn, where, val); |
829 | } |
830 | static inline int pci_write_config_word(const struct pci_dev *dev, int where, u16 val) |
831 | { |
832 | return pci_bus_write_config_word(dev->bus, dev->devfn, where, val); |
833 | } |
834 | static inline int pci_write_config_dword(const struct pci_dev *dev, int where, |
835 | u32 val) |
836 | { |
837 | return pci_bus_write_config_dword(dev->bus, dev->devfn, where, val); |
838 | } |
839 | |
840 | int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val); |
841 | int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val); |
842 | int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val); |
843 | int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val); |
844 | int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos, |
845 | u16 clear, u16 set); |
846 | int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos, |
847 | u32 clear, u32 set); |
848 | |
849 | static inline int pcie_capability_set_word(struct pci_dev *dev, int pos, |
850 | u16 set) |
851 | { |
852 | return pcie_capability_clear_and_set_word(dev, pos, 0, set); |
853 | } |
854 | |
855 | static inline int pcie_capability_set_dword(struct pci_dev *dev, int pos, |
856 | u32 set) |
857 | { |
858 | return pcie_capability_clear_and_set_dword(dev, pos, 0, set); |
859 | } |
860 | |
861 | static inline int pcie_capability_clear_word(struct pci_dev *dev, int pos, |
862 | u16 clear) |
863 | { |
864 | return pcie_capability_clear_and_set_word(dev, pos, clear, 0); |
865 | } |
866 | |
867 | static inline int pcie_capability_clear_dword(struct pci_dev *dev, int pos, |
868 | u32 clear) |
869 | { |
870 | return pcie_capability_clear_and_set_dword(dev, pos, clear, 0); |
871 | } |
872 | |
873 | /* user-space driven config access */ |
874 | int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val); |
875 | int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val); |
876 | int pci_user_read_config_dword(struct pci_dev *dev, int where, u32 *val); |
877 | int pci_user_write_config_byte(struct pci_dev *dev, int where, u8 val); |
878 | int pci_user_write_config_word(struct pci_dev *dev, int where, u16 val); |
879 | int pci_user_write_config_dword(struct pci_dev *dev, int where, u32 val); |
880 | |
881 | int __must_check pci_enable_device(struct pci_dev *dev); |
882 | int __must_check pci_enable_device_io(struct pci_dev *dev); |
883 | int __must_check pci_enable_device_mem(struct pci_dev *dev); |
884 | int __must_check pci_reenable_device(struct pci_dev *); |
885 | int __must_check pcim_enable_device(struct pci_dev *pdev); |
886 | void pcim_pin_device(struct pci_dev *pdev); |
887 | |
888 | static inline int pci_is_enabled(struct pci_dev *pdev) |
889 | { |
890 | return (atomic_read(&pdev->enable_cnt) > 0); |
891 | } |
892 | |
893 | static inline int pci_is_managed(struct pci_dev *pdev) |
894 | { |
895 | return pdev->is_managed; |
896 | } |
897 | |
898 | void pci_disable_device(struct pci_dev *dev); |
899 | |
900 | extern unsigned int pcibios_max_latency; |
901 | void pci_set_master(struct pci_dev *dev); |
902 | void pci_clear_master(struct pci_dev *dev); |
903 | |
904 | int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state); |
905 | int pci_set_cacheline_size(struct pci_dev *dev); |
906 | #define HAVE_PCI_SET_MWI |
907 | int __must_check pci_set_mwi(struct pci_dev *dev); |
908 | int pci_try_set_mwi(struct pci_dev *dev); |
909 | void pci_clear_mwi(struct pci_dev *dev); |
910 | void pci_intx(struct pci_dev *dev, int enable); |
911 | bool pci_intx_mask_supported(struct pci_dev *dev); |
912 | bool pci_check_and_mask_intx(struct pci_dev *dev); |
913 | bool pci_check_and_unmask_intx(struct pci_dev *dev); |
914 | void pci_msi_off(struct pci_dev *dev); |
915 | int pci_set_dma_max_seg_size(struct pci_dev *dev, unsigned int size); |
916 | int pci_set_dma_seg_boundary(struct pci_dev *dev, unsigned long mask); |
917 | int pcix_get_max_mmrbc(struct pci_dev *dev); |
918 | int pcix_get_mmrbc(struct pci_dev *dev); |
919 | int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc); |
920 | int pcie_get_readrq(struct pci_dev *dev); |
921 | int pcie_set_readrq(struct pci_dev *dev, int rq); |
922 | int pcie_get_mps(struct pci_dev *dev); |
923 | int pcie_set_mps(struct pci_dev *dev, int mps); |
924 | int __pci_reset_function(struct pci_dev *dev); |
925 | int __pci_reset_function_locked(struct pci_dev *dev); |
926 | int pci_reset_function(struct pci_dev *dev); |
927 | void pci_update_resource(struct pci_dev *dev, int resno); |
928 | int __must_check pci_assign_resource(struct pci_dev *dev, int i); |
929 | int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align); |
930 | int pci_select_bars(struct pci_dev *dev, unsigned long flags); |
931 | |
932 | /* ROM control related routines */ |
933 | int pci_enable_rom(struct pci_dev *pdev); |
934 | void pci_disable_rom(struct pci_dev *pdev); |
935 | void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size); |
936 | void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom); |
937 | size_t pci_get_rom_size(struct pci_dev *pdev, void __iomem *rom, size_t size); |
938 | void __iomem __must_check *pci_platform_rom(struct pci_dev *pdev, size_t *size); |
939 | |
940 | /* Power management related routines */ |
941 | int pci_save_state(struct pci_dev *dev); |
942 | void pci_restore_state(struct pci_dev *dev); |
943 | struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev); |
944 | int pci_load_saved_state(struct pci_dev *dev, struct pci_saved_state *state); |
945 | int pci_load_and_free_saved_state(struct pci_dev *dev, |
946 | struct pci_saved_state **state); |
947 | int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state); |
948 | int pci_set_power_state(struct pci_dev *dev, pci_power_t state); |
949 | pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state); |
950 | bool pci_pme_capable(struct pci_dev *dev, pci_power_t state); |
951 | void pci_pme_active(struct pci_dev *dev, bool enable); |
952 | int __pci_enable_wake(struct pci_dev *dev, pci_power_t state, |
953 | bool runtime, bool enable); |
954 | int pci_wake_from_d3(struct pci_dev *dev, bool enable); |
955 | pci_power_t pci_target_state(struct pci_dev *dev); |
956 | int pci_prepare_to_sleep(struct pci_dev *dev); |
957 | int pci_back_from_sleep(struct pci_dev *dev); |
958 | bool pci_dev_run_wake(struct pci_dev *dev); |
959 | bool pci_check_pme_status(struct pci_dev *dev); |
960 | void pci_pme_wakeup_bus(struct pci_bus *bus); |
961 | |
962 | static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state, |
963 | bool enable) |
964 | { |
965 | return __pci_enable_wake(dev, state, false, enable); |
966 | } |
967 | |
968 | #define PCI_EXP_IDO_REQUEST (1<<0) |
969 | #define PCI_EXP_IDO_COMPLETION (1<<1) |
970 | void pci_enable_ido(struct pci_dev *dev, unsigned long type); |
971 | void pci_disable_ido(struct pci_dev *dev, unsigned long type); |
972 | |
973 | enum pci_obff_signal_type { |
974 | PCI_EXP_OBFF_SIGNAL_L0 = 0, |
975 | PCI_EXP_OBFF_SIGNAL_ALWAYS = 1, |
976 | }; |
977 | int pci_enable_obff(struct pci_dev *dev, enum pci_obff_signal_type); |
978 | void pci_disable_obff(struct pci_dev *dev); |
979 | |
980 | int pci_enable_ltr(struct pci_dev *dev); |
981 | void pci_disable_ltr(struct pci_dev *dev); |
982 | int pci_set_ltr(struct pci_dev *dev, int snoop_lat_ns, int nosnoop_lat_ns); |
983 | |
984 | /* For use by arch with custom probe code */ |
985 | void set_pcie_port_type(struct pci_dev *pdev); |
986 | void set_pcie_hotplug_bridge(struct pci_dev *pdev); |
987 | |
988 | /* Functions for PCI Hotplug drivers to use */ |
989 | int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap); |
990 | unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge); |
991 | unsigned int pci_rescan_bus(struct pci_bus *bus); |
992 | |
993 | /* Vital product data routines */ |
994 | ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf); |
995 | ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf); |
996 | int pci_vpd_truncate(struct pci_dev *dev, size_t size); |
997 | |
998 | /* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */ |
999 | resource_size_t pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx); |
1000 | void pci_bus_assign_resources(const struct pci_bus *bus); |
1001 | void pci_bus_size_bridges(struct pci_bus *bus); |
1002 | int pci_claim_resource(struct pci_dev *, int); |
1003 | void pci_assign_unassigned_resources(void); |
1004 | void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge); |
1005 | void pci_assign_unassigned_bus_resources(struct pci_bus *bus); |
1006 | void pdev_enable_device(struct pci_dev *); |
1007 | int pci_enable_resources(struct pci_dev *, int mask); |
1008 | void pci_fixup_irqs(u8 (*)(struct pci_dev *, u8 *), |
1009 | int (*)(const struct pci_dev *, u8, u8)); |
1010 | #define HAVE_PCI_REQ_REGIONS 2 |
1011 | int __must_check pci_request_regions(struct pci_dev *, const char *); |
1012 | int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *); |
1013 | void pci_release_regions(struct pci_dev *); |
1014 | int __must_check pci_request_region(struct pci_dev *, int, const char *); |
1015 | int __must_check pci_request_region_exclusive(struct pci_dev *, int, const char *); |
1016 | void pci_release_region(struct pci_dev *, int); |
1017 | int pci_request_selected_regions(struct pci_dev *, int, const char *); |
1018 | int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *); |
1019 | void pci_release_selected_regions(struct pci_dev *, int); |
1020 | |
1021 | /* drivers/pci/bus.c */ |
1022 | struct pci_bus *pci_bus_get(struct pci_bus *bus); |
1023 | void pci_bus_put(struct pci_bus *bus); |
1024 | void pci_add_resource(struct list_head *resources, struct resource *res); |
1025 | void pci_add_resource_offset(struct list_head *resources, struct resource *res, |
1026 | resource_size_t offset); |
1027 | void pci_free_resource_list(struct list_head *resources); |
1028 | void pci_bus_add_resource(struct pci_bus *bus, struct resource *res, unsigned int flags); |
1029 | struct resource *pci_bus_resource_n(const struct pci_bus *bus, int n); |
1030 | void pci_bus_remove_resources(struct pci_bus *bus); |
1031 | |
1032 | #define pci_bus_for_each_resource(bus, res, i) \ |
1033 | for (i = 0; \ |
1034 | (res = pci_bus_resource_n(bus, i)) || i < PCI_BRIDGE_RESOURCE_NUM; \ |
1035 | i++) |
1036 | |
1037 | int __must_check pci_bus_alloc_resource(struct pci_bus *bus, |
1038 | struct resource *res, resource_size_t size, |
1039 | resource_size_t align, resource_size_t min, |
1040 | unsigned int type_mask, |
1041 | resource_size_t (*alignf)(void *, |
1042 | const struct resource *, |
1043 | resource_size_t, |
1044 | resource_size_t), |
1045 | void *alignf_data); |
1046 | void pci_enable_bridges(struct pci_bus *bus); |
1047 | |
1048 | /* Proper probing supporting hot-pluggable devices */ |
1049 | int __must_check __pci_register_driver(struct pci_driver *, struct module *, |
1050 | const char *mod_name); |
1051 | |
1052 | /* |
1053 | * pci_register_driver must be a macro so that KBUILD_MODNAME can be expanded |
1054 | */ |
1055 | #define pci_register_driver(driver) \ |
1056 | __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME) |
1057 | |
1058 | void pci_unregister_driver(struct pci_driver *dev); |
1059 | |
1060 | /** |
1061 | * module_pci_driver() - Helper macro for registering a PCI driver |
1062 | * @__pci_driver: pci_driver struct |
1063 | * |
1064 | * Helper macro for PCI drivers which do not do anything special in module |
1065 | * init/exit. This eliminates a lot of boilerplate. Each module may only |
1066 | * use this macro once, and calling it replaces module_init() and module_exit() |
1067 | */ |
1068 | #define module_pci_driver(__pci_driver) \ |
1069 | module_driver(__pci_driver, pci_register_driver, \ |
1070 | pci_unregister_driver) |
1071 | |
1072 | struct pci_driver *pci_dev_driver(const struct pci_dev *dev); |
1073 | int pci_add_dynid(struct pci_driver *drv, |
1074 | unsigned int vendor, unsigned int device, |
1075 | unsigned int subvendor, unsigned int subdevice, |
1076 | unsigned int class, unsigned int class_mask, |
1077 | unsigned long driver_data); |
1078 | const struct pci_device_id *pci_match_id(const struct pci_device_id *ids, |
1079 | struct pci_dev *dev); |
1080 | int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, |
1081 | int pass); |
1082 | |
1083 | void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *), |
1084 | void *userdata); |
1085 | int pci_cfg_space_size_ext(struct pci_dev *dev); |
1086 | int pci_cfg_space_size(struct pci_dev *dev); |
1087 | unsigned char pci_bus_max_busnr(struct pci_bus *bus); |
1088 | void pci_setup_bridge(struct pci_bus *bus); |
1089 | resource_size_t pcibios_window_alignment(struct pci_bus *bus, |
1090 | unsigned long type); |
1091 | |
1092 | #define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0) |
1093 | #define PCI_VGA_STATE_CHANGE_DECODES (1 << 1) |
1094 | |
1095 | int pci_set_vga_state(struct pci_dev *pdev, bool decode, |
1096 | unsigned int command_bits, u32 flags); |
1097 | /* kmem_cache style wrapper around pci_alloc_consistent() */ |
1098 | |
1099 | #include <linux/pci-dma.h> |
1100 | #include <linux/dmapool.h> |
1101 | |
1102 | #define pci_pool dma_pool |
1103 | #define pci_pool_create(name, pdev, size, align, allocation) \ |
1104 | dma_pool_create(name, &pdev->dev, size, align, allocation) |
1105 | #define pci_pool_destroy(pool) dma_pool_destroy(pool) |
1106 | #define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle) |
1107 | #define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr) |
1108 | |
1109 | enum pci_dma_burst_strategy { |
1110 | PCI_DMA_BURST_INFINITY, /* make bursts as large as possible, |
1111 | strategy_parameter is N/A */ |
1112 | PCI_DMA_BURST_BOUNDARY, /* disconnect at every strategy_parameter |
1113 | byte boundaries */ |
1114 | PCI_DMA_BURST_MULTIPLE, /* disconnect at some multiple of |
1115 | strategy_parameter byte boundaries */ |
1116 | }; |
1117 | |
1118 | struct msix_entry { |
1119 | u32 vector; /* kernel uses to write allocated vector */ |
1120 | u16 entry; /* driver uses to specify entry, OS writes */ |
1121 | }; |
1122 | |
1123 | |
1124 | #ifndef CONFIG_PCI_MSI |
1125 | static inline int pci_enable_msi_block(struct pci_dev *dev, unsigned int nvec) |
1126 | { |
1127 | return -1; |
1128 | } |
1129 | |
1130 | static inline int |
1131 | pci_enable_msi_block_auto(struct pci_dev *dev, unsigned int *maxvec) |
1132 | { |
1133 | return -1; |
1134 | } |
1135 | |
1136 | static inline void pci_msi_shutdown(struct pci_dev *dev) |
1137 | { } |
1138 | static inline void pci_disable_msi(struct pci_dev *dev) |
1139 | { } |
1140 | |
1141 | static inline int pci_msix_table_size(struct pci_dev *dev) |
1142 | { |
1143 | return 0; |
1144 | } |
1145 | static inline int pci_enable_msix(struct pci_dev *dev, |
1146 | struct msix_entry *entries, int nvec) |
1147 | { |
1148 | return -1; |
1149 | } |
1150 | |
1151 | static inline void pci_msix_shutdown(struct pci_dev *dev) |
1152 | { } |
1153 | static inline void pci_disable_msix(struct pci_dev *dev) |
1154 | { } |
1155 | |
1156 | static inline void msi_remove_pci_irq_vectors(struct pci_dev *dev) |
1157 | { } |
1158 | |
1159 | static inline void pci_restore_msi_state(struct pci_dev *dev) |
1160 | { } |
1161 | static inline int pci_msi_enabled(void) |
1162 | { |
1163 | return 0; |
1164 | } |
1165 | #else |
1166 | int pci_enable_msi_block(struct pci_dev *dev, unsigned int nvec); |
1167 | int pci_enable_msi_block_auto(struct pci_dev *dev, unsigned int *maxvec); |
1168 | void pci_msi_shutdown(struct pci_dev *dev); |
1169 | void pci_disable_msi(struct pci_dev *dev); |
1170 | int pci_msix_table_size(struct pci_dev *dev); |
1171 | int pci_enable_msix(struct pci_dev *dev, struct msix_entry *entries, int nvec); |
1172 | void pci_msix_shutdown(struct pci_dev *dev); |
1173 | void pci_disable_msix(struct pci_dev *dev); |
1174 | void msi_remove_pci_irq_vectors(struct pci_dev *dev); |
1175 | void pci_restore_msi_state(struct pci_dev *dev); |
1176 | int pci_msi_enabled(void); |
1177 | #endif |
1178 | |
1179 | #ifdef CONFIG_PCIEPORTBUS |
1180 | extern bool pcie_ports_disabled; |
1181 | extern bool pcie_ports_auto; |
1182 | #else |
1183 | #define pcie_ports_disabled true |
1184 | #define pcie_ports_auto false |
1185 | #endif |
1186 | |
1187 | #ifndef CONFIG_PCIEASPM |
1188 | static inline int pcie_aspm_enabled(void) { return 0; } |
1189 | static inline bool pcie_aspm_support_enabled(void) { return false; } |
1190 | #else |
1191 | int pcie_aspm_enabled(void); |
1192 | bool pcie_aspm_support_enabled(void); |
1193 | #endif |
1194 | |
1195 | #ifdef CONFIG_PCIEAER |
1196 | void pci_no_aer(void); |
1197 | bool pci_aer_available(void); |
1198 | #else |
1199 | static inline void pci_no_aer(void) { } |
1200 | static inline bool pci_aer_available(void) { return false; } |
1201 | #endif |
1202 | |
1203 | #ifndef CONFIG_PCIE_ECRC |
1204 | static inline void pcie_set_ecrc_checking(struct pci_dev *dev) |
1205 | { |
1206 | return; |
1207 | } |
1208 | static inline void pcie_ecrc_get_policy(char *str) {}; |
1209 | #else |
1210 | void pcie_set_ecrc_checking(struct pci_dev *dev); |
1211 | void pcie_ecrc_get_policy(char *str); |
1212 | #endif |
1213 | |
1214 | #define pci_enable_msi(pdev) pci_enable_msi_block(pdev, 1) |
1215 | |
1216 | #ifdef CONFIG_HT_IRQ |
1217 | /* The functions a driver should call */ |
1218 | int ht_create_irq(struct pci_dev *dev, int idx); |
1219 | void ht_destroy_irq(unsigned int irq); |
1220 | #endif /* CONFIG_HT_IRQ */ |
1221 | |
1222 | void pci_cfg_access_lock(struct pci_dev *dev); |
1223 | bool pci_cfg_access_trylock(struct pci_dev *dev); |
1224 | void pci_cfg_access_unlock(struct pci_dev *dev); |
1225 | |
1226 | /* |
1227 | * PCI domain support. Sometimes called PCI segment (eg by ACPI), |
1228 | * a PCI domain is defined to be a set of PCI busses which share |
1229 | * configuration space. |
1230 | */ |
1231 | #ifdef CONFIG_PCI_DOMAINS |
1232 | extern int pci_domains_supported; |
1233 | #else |
1234 | enum { pci_domains_supported = 0 }; |
1235 | static inline int pci_domain_nr(struct pci_bus *bus) |
1236 | { |
1237 | return 0; |
1238 | } |
1239 | |
1240 | static inline int pci_proc_domain(struct pci_bus *bus) |
1241 | { |
1242 | return 0; |
1243 | } |
1244 | #endif /* CONFIG_PCI_DOMAINS */ |
1245 | |
1246 | /* some architectures require additional setup to direct VGA traffic */ |
1247 | typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode, |
1248 | unsigned int command_bits, u32 flags); |
1249 | void pci_register_set_vga_state(arch_set_vga_state_t func); |
1250 | |
1251 | #else /* CONFIG_PCI is not enabled */ |
1252 | |
1253 | /* |
1254 | * If the system does not have PCI, clearly these return errors. Define |
1255 | * these as simple inline functions to avoid hair in drivers. |
1256 | */ |
1257 | |
1258 | #define _PCI_NOP(o, s, t) \ |
1259 | static inline int pci_##o##_config_##s(struct pci_dev *dev, \ |
1260 | int where, t val) \ |
1261 | { return PCIBIOS_FUNC_NOT_SUPPORTED; } |
1262 | |
1263 | #define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \ |
1264 | _PCI_NOP(o, word, u16 x) \ |
1265 | _PCI_NOP(o, dword, u32 x) |
1266 | _PCI_NOP_ALL(read, *) |
1267 | _PCI_NOP_ALL(write,) |
1268 | |
1269 | static inline struct pci_dev *pci_get_device(unsigned int vendor, |
1270 | unsigned int device, |
1271 | struct pci_dev *from) |
1272 | { |
1273 | return NULL; |
1274 | } |
1275 | |
1276 | static inline struct pci_dev *pci_get_subsys(unsigned int vendor, |
1277 | unsigned int device, |
1278 | unsigned int ss_vendor, |
1279 | unsigned int ss_device, |
1280 | struct pci_dev *from) |
1281 | { |
1282 | return NULL; |
1283 | } |
1284 | |
1285 | static inline struct pci_dev *pci_get_class(unsigned int class, |
1286 | struct pci_dev *from) |
1287 | { |
1288 | return NULL; |
1289 | } |
1290 | |
1291 | #define pci_dev_present(ids) (0) |
1292 | #define no_pci_devices() (1) |
1293 | #define pci_dev_put(dev) do { } while (0) |
1294 | |
1295 | static inline void pci_set_master(struct pci_dev *dev) |
1296 | { } |
1297 | |
1298 | static inline int pci_enable_device(struct pci_dev *dev) |
1299 | { |
1300 | return -EIO; |
1301 | } |
1302 | |
1303 | static inline void pci_disable_device(struct pci_dev *dev) |
1304 | { } |
1305 | |
1306 | static inline int pci_set_dma_mask(struct pci_dev *dev, u64 mask) |
1307 | { |
1308 | return -EIO; |
1309 | } |
1310 | |
1311 | static inline int pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask) |
1312 | { |
1313 | return -EIO; |
1314 | } |
1315 | |
1316 | static inline int pci_set_dma_max_seg_size(struct pci_dev *dev, |
1317 | unsigned int size) |
1318 | { |
1319 | return -EIO; |
1320 | } |
1321 | |
1322 | static inline int pci_set_dma_seg_boundary(struct pci_dev *dev, |
1323 | unsigned long mask) |
1324 | { |
1325 | return -EIO; |
1326 | } |
1327 | |
1328 | static inline int pci_assign_resource(struct pci_dev *dev, int i) |
1329 | { |
1330 | return -EBUSY; |
1331 | } |
1332 | |
1333 | static inline int __pci_register_driver(struct pci_driver *drv, |
1334 | struct module *owner) |
1335 | { |
1336 | return 0; |
1337 | } |
1338 | |
1339 | static inline int pci_register_driver(struct pci_driver *drv) |
1340 | { |
1341 | return 0; |
1342 | } |
1343 | |
1344 | static inline void pci_unregister_driver(struct pci_driver *drv) |
1345 | { } |
1346 | |
1347 | static inline int pci_find_capability(struct pci_dev *dev, int cap) |
1348 | { |
1349 | return 0; |
1350 | } |
1351 | |
1352 | static inline int pci_find_next_capability(struct pci_dev *dev, u8 post, |
1353 | int cap) |
1354 | { |
1355 | return 0; |
1356 | } |
1357 | |
1358 | static inline int pci_find_ext_capability(struct pci_dev *dev, int cap) |
1359 | { |
1360 | return 0; |
1361 | } |
1362 | |
1363 | /* Power management related routines */ |
1364 | static inline int pci_save_state(struct pci_dev *dev) |
1365 | { |
1366 | return 0; |
1367 | } |
1368 | |
1369 | static inline void pci_restore_state(struct pci_dev *dev) |
1370 | { } |
1371 | |
1372 | static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state) |
1373 | { |
1374 | return 0; |
1375 | } |
1376 | |
1377 | static inline int pci_wake_from_d3(struct pci_dev *dev, bool enable) |
1378 | { |
1379 | return 0; |
1380 | } |
1381 | |
1382 | static inline pci_power_t pci_choose_state(struct pci_dev *dev, |
1383 | pm_message_t state) |
1384 | { |
1385 | return PCI_D0; |
1386 | } |
1387 | |
1388 | static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state, |
1389 | int enable) |
1390 | { |
1391 | return 0; |
1392 | } |
1393 | |
1394 | static inline void pci_enable_ido(struct pci_dev *dev, unsigned long type) |
1395 | { |
1396 | } |
1397 | |
1398 | static inline void pci_disable_ido(struct pci_dev *dev, unsigned long type) |
1399 | { |
1400 | } |
1401 | |
1402 | static inline int pci_enable_obff(struct pci_dev *dev, unsigned long type) |
1403 | { |
1404 | return 0; |
1405 | } |
1406 | |
1407 | static inline void pci_disable_obff(struct pci_dev *dev) |
1408 | { |
1409 | } |
1410 | |
1411 | static inline int pci_request_regions(struct pci_dev *dev, const char *res_name) |
1412 | { |
1413 | return -EIO; |
1414 | } |
1415 | |
1416 | static inline void pci_release_regions(struct pci_dev *dev) |
1417 | { } |
1418 | |
1419 | #define pci_dma_burst_advice(pdev, strat, strategy_parameter) do { } while (0) |
1420 | |
1421 | static inline void pci_block_cfg_access(struct pci_dev *dev) |
1422 | { } |
1423 | |
1424 | static inline int pci_block_cfg_access_in_atomic(struct pci_dev *dev) |
1425 | { return 0; } |
1426 | |
1427 | static inline void pci_unblock_cfg_access(struct pci_dev *dev) |
1428 | { } |
1429 | |
1430 | static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from) |
1431 | { return NULL; } |
1432 | |
1433 | static inline struct pci_dev *pci_get_slot(struct pci_bus *bus, |
1434 | unsigned int devfn) |
1435 | { return NULL; } |
1436 | |
1437 | static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus, |
1438 | unsigned int devfn) |
1439 | { return NULL; } |
1440 | |
1441 | static inline int pci_domain_nr(struct pci_bus *bus) |
1442 | { return 0; } |
1443 | |
1444 | static inline struct pci_dev *pci_dev_get(struct pci_dev *dev) |
1445 | { return NULL; } |
1446 | |
1447 | #define dev_is_pci(d) (false) |
1448 | #define dev_is_pf(d) (false) |
1449 | #define dev_num_vf(d) (0) |
1450 | #endif /* CONFIG_PCI */ |
1451 | |
1452 | /* Include architecture-dependent settings and functions */ |
1453 | |
1454 | #include <asm/pci.h> |
1455 | |
1456 | #ifndef PCIBIOS_MAX_MEM_32 |
1457 | #define PCIBIOS_MAX_MEM_32 (-1) |
1458 | #endif |
1459 | |
1460 | /* these helpers provide future and backwards compatibility |
1461 | * for accessing popular PCI BAR info */ |
1462 | #define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start) |
1463 | #define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end) |
1464 | #define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags) |
1465 | #define pci_resource_len(dev,bar) \ |
1466 | ((pci_resource_start((dev), (bar)) == 0 && \ |
1467 | pci_resource_end((dev), (bar)) == \ |
1468 | pci_resource_start((dev), (bar))) ? 0 : \ |
1469 | \ |
1470 | (pci_resource_end((dev), (bar)) - \ |
1471 | pci_resource_start((dev), (bar)) + 1)) |
1472 | |
1473 | /* Similar to the helpers above, these manipulate per-pci_dev |
1474 | * driver-specific data. They are really just a wrapper around |
1475 | * the generic device structure functions of these calls. |
1476 | */ |
1477 | static inline void *pci_get_drvdata(struct pci_dev *pdev) |
1478 | { |
1479 | return dev_get_drvdata(&pdev->dev); |
1480 | } |
1481 | |
1482 | static inline void pci_set_drvdata(struct pci_dev *pdev, void *data) |
1483 | { |
1484 | dev_set_drvdata(&pdev->dev, data); |
1485 | } |
1486 | |
1487 | /* If you want to know what to call your pci_dev, ask this function. |
1488 | * Again, it's a wrapper around the generic device. |
1489 | */ |
1490 | static inline const char *pci_name(const struct pci_dev *pdev) |
1491 | { |
1492 | return dev_name(&pdev->dev); |
1493 | } |
1494 | |
1495 | |
1496 | /* Some archs don't want to expose struct resource to userland as-is |
1497 | * in sysfs and /proc |
1498 | */ |
1499 | #ifndef HAVE_ARCH_PCI_RESOURCE_TO_USER |
1500 | static inline void pci_resource_to_user(const struct pci_dev *dev, int bar, |
1501 | const struct resource *rsrc, resource_size_t *start, |
1502 | resource_size_t *end) |
1503 | { |
1504 | *start = rsrc->start; |
1505 | *end = rsrc->end; |
1506 | } |
1507 | #endif /* HAVE_ARCH_PCI_RESOURCE_TO_USER */ |
1508 | |
1509 | |
1510 | /* |
1511 | * The world is not perfect and supplies us with broken PCI devices. |
1512 | * For at least a part of these bugs we need a work-around, so both |
1513 | * generic (drivers/pci/quirks.c) and per-architecture code can define |
1514 | * fixup hooks to be called for particular buggy devices. |
1515 | */ |
1516 | |
1517 | struct pci_fixup { |
1518 | u16 vendor; /* You can use PCI_ANY_ID here of course */ |
1519 | u16 device; /* You can use PCI_ANY_ID here of course */ |
1520 | u32 class; /* You can use PCI_ANY_ID here too */ |
1521 | unsigned int class_shift; /* should be 0, 8, 16 */ |
1522 | void (*hook)(struct pci_dev *dev); |
1523 | }; |
1524 | |
1525 | enum pci_fixup_pass { |
1526 | pci_fixup_early, /* Before probing BARs */ |
1527 | pci_fixup_header, /* After reading configuration header */ |
1528 | pci_fixup_final, /* Final phase of device fixups */ |
1529 | pci_fixup_enable, /* pci_enable_device() time */ |
1530 | pci_fixup_resume, /* pci_device_resume() */ |
1531 | pci_fixup_suspend, /* pci_device_suspend */ |
1532 | pci_fixup_resume_early, /* pci_device_resume_early() */ |
1533 | }; |
1534 | |
1535 | /* Anonymous variables would be nice... */ |
1536 | #define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, class, \ |
1537 | class_shift, hook) \ |
1538 | static const struct pci_fixup __pci_fixup_##name __used \ |
1539 | __attribute__((__section__(#section), aligned((sizeof(void *))))) \ |
1540 | = { vendor, device, class, class_shift, hook }; |
1541 | |
1542 | #define DECLARE_PCI_FIXUP_CLASS_EARLY(vendor, device, class, \ |
1543 | class_shift, hook) \ |
1544 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \ |
1545 | vendor##device##hook, vendor, device, class, class_shift, hook) |
1546 | #define DECLARE_PCI_FIXUP_CLASS_HEADER(vendor, device, class, \ |
1547 | class_shift, hook) \ |
1548 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \ |
1549 | vendor##device##hook, vendor, device, class, class_shift, hook) |
1550 | #define DECLARE_PCI_FIXUP_CLASS_FINAL(vendor, device, class, \ |
1551 | class_shift, hook) \ |
1552 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \ |
1553 | vendor##device##hook, vendor, device, class, class_shift, hook) |
1554 | #define DECLARE_PCI_FIXUP_CLASS_ENABLE(vendor, device, class, \ |
1555 | class_shift, hook) \ |
1556 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \ |
1557 | vendor##device##hook, vendor, device, class, class_shift, hook) |
1558 | #define DECLARE_PCI_FIXUP_CLASS_RESUME(vendor, device, class, \ |
1559 | class_shift, hook) \ |
1560 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \ |
1561 | resume##vendor##device##hook, vendor, device, class, \ |
1562 | class_shift, hook) |
1563 | #define DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(vendor, device, class, \ |
1564 | class_shift, hook) \ |
1565 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \ |
1566 | resume_early##vendor##device##hook, vendor, device, \ |
1567 | class, class_shift, hook) |
1568 | #define DECLARE_PCI_FIXUP_CLASS_SUSPEND(vendor, device, class, \ |
1569 | class_shift, hook) \ |
1570 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \ |
1571 | suspend##vendor##device##hook, vendor, device, class, \ |
1572 | class_shift, hook) |
1573 | |
1574 | #define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \ |
1575 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \ |
1576 | vendor##device##hook, vendor, device, PCI_ANY_ID, 0, hook) |
1577 | #define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \ |
1578 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \ |
1579 | vendor##device##hook, vendor, device, PCI_ANY_ID, 0, hook) |
1580 | #define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \ |
1581 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \ |
1582 | vendor##device##hook, vendor, device, PCI_ANY_ID, 0, hook) |
1583 | #define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \ |
1584 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \ |
1585 | vendor##device##hook, vendor, device, PCI_ANY_ID, 0, hook) |
1586 | #define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \ |
1587 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \ |
1588 | resume##vendor##device##hook, vendor, device, \ |
1589 | PCI_ANY_ID, 0, hook) |
1590 | #define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \ |
1591 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \ |
1592 | resume_early##vendor##device##hook, vendor, device, \ |
1593 | PCI_ANY_ID, 0, hook) |
1594 | #define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \ |
1595 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \ |
1596 | suspend##vendor##device##hook, vendor, device, \ |
1597 | PCI_ANY_ID, 0, hook) |
1598 | |
1599 | #ifdef CONFIG_PCI_QUIRKS |
1600 | void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev); |
1601 | struct pci_dev *pci_get_dma_source(struct pci_dev *dev); |
1602 | int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags); |
1603 | #else |
1604 | static inline void pci_fixup_device(enum pci_fixup_pass pass, |
1605 | struct pci_dev *dev) {} |
1606 | static inline struct pci_dev *pci_get_dma_source(struct pci_dev *dev) |
1607 | { |
1608 | return pci_dev_get(dev); |
1609 | } |
1610 | static inline int pci_dev_specific_acs_enabled(struct pci_dev *dev, |
1611 | u16 acs_flags) |
1612 | { |
1613 | return -ENOTTY; |
1614 | } |
1615 | #endif |
1616 | |
1617 | void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen); |
1618 | void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr); |
1619 | void __iomem * const *pcim_iomap_table(struct pci_dev *pdev); |
1620 | int pcim_iomap_regions(struct pci_dev *pdev, int mask, const char *name); |
1621 | int pcim_iomap_regions_request_all(struct pci_dev *pdev, int mask, |
1622 | const char *name); |
1623 | void pcim_iounmap_regions(struct pci_dev *pdev, int mask); |
1624 | |
1625 | extern int pci_pci_problems; |
1626 | #define PCIPCI_FAIL 1 /* No PCI PCI DMA */ |
1627 | #define PCIPCI_TRITON 2 |
1628 | #define PCIPCI_NATOMA 4 |
1629 | #define PCIPCI_VIAETBF 8 |
1630 | #define PCIPCI_VSFX 16 |
1631 | #define PCIPCI_ALIMAGIK 32 /* Need low latency setting */ |
1632 | #define PCIAGP_FAIL 64 /* No PCI to AGP DMA */ |
1633 | |
1634 | extern unsigned long pci_cardbus_io_size; |
1635 | extern unsigned long pci_cardbus_mem_size; |
1636 | extern u8 pci_dfl_cache_line_size; |
1637 | extern u8 pci_cache_line_size; |
1638 | |
1639 | extern unsigned long pci_hotplug_io_size; |
1640 | extern unsigned long pci_hotplug_mem_size; |
1641 | |
1642 | /* Architecture specific versions may override these (weak) */ |
1643 | int pcibios_add_platform_entries(struct pci_dev *dev); |
1644 | void pcibios_disable_device(struct pci_dev *dev); |
1645 | void pcibios_set_master(struct pci_dev *dev); |
1646 | int pcibios_set_pcie_reset_state(struct pci_dev *dev, |
1647 | enum pcie_reset_state state); |
1648 | int pcibios_add_device(struct pci_dev *dev); |
1649 | void pcibios_release_device(struct pci_dev *dev); |
1650 | |
1651 | #ifdef CONFIG_PCI_MMCONFIG |
1652 | void __init pci_mmcfg_early_init(void); |
1653 | void __init pci_mmcfg_late_init(void); |
1654 | #else |
1655 | static inline void pci_mmcfg_early_init(void) { } |
1656 | static inline void pci_mmcfg_late_init(void) { } |
1657 | #endif |
1658 | |
1659 | int pci_ext_cfg_avail(void); |
1660 | |
1661 | void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar); |
1662 | |
1663 | #ifdef CONFIG_PCI_IOV |
1664 | int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn); |
1665 | void pci_disable_sriov(struct pci_dev *dev); |
1666 | irqreturn_t pci_sriov_migration(struct pci_dev *dev); |
1667 | int pci_num_vf(struct pci_dev *dev); |
1668 | int pci_vfs_assigned(struct pci_dev *dev); |
1669 | int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs); |
1670 | int pci_sriov_get_totalvfs(struct pci_dev *dev); |
1671 | #else |
1672 | static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn) |
1673 | { |
1674 | return -ENODEV; |
1675 | } |
1676 | static inline void pci_disable_sriov(struct pci_dev *dev) |
1677 | { |
1678 | } |
1679 | static inline irqreturn_t pci_sriov_migration(struct pci_dev *dev) |
1680 | { |
1681 | return IRQ_NONE; |
1682 | } |
1683 | static inline int pci_num_vf(struct pci_dev *dev) |
1684 | { |
1685 | return 0; |
1686 | } |
1687 | static inline int pci_vfs_assigned(struct pci_dev *dev) |
1688 | { |
1689 | return 0; |
1690 | } |
1691 | static inline int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs) |
1692 | { |
1693 | return 0; |
1694 | } |
1695 | static inline int pci_sriov_get_totalvfs(struct pci_dev *dev) |
1696 | { |
1697 | return 0; |
1698 | } |
1699 | #endif |
1700 | |
1701 | #if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE) |
1702 | void pci_hp_create_module_link(struct pci_slot *pci_slot); |
1703 | void pci_hp_remove_module_link(struct pci_slot *pci_slot); |
1704 | #endif |
1705 | |
1706 | /** |
1707 | * pci_pcie_cap - get the saved PCIe capability offset |
1708 | * @dev: PCI device |
1709 | * |
1710 | * PCIe capability offset is calculated at PCI device initialization |
1711 | * time and saved in the data structure. This function returns saved |
1712 | * PCIe capability offset. Using this instead of pci_find_capability() |
1713 | * reduces unnecessary search in the PCI configuration space. If you |
1714 | * need to calculate PCIe capability offset from raw device for some |
1715 | * reasons, please use pci_find_capability() instead. |
1716 | */ |
1717 | static inline int pci_pcie_cap(struct pci_dev *dev) |
1718 | { |
1719 | return dev->pcie_cap; |
1720 | } |
1721 | |
1722 | /** |
1723 | * pci_is_pcie - check if the PCI device is PCI Express capable |
1724 | * @dev: PCI device |
1725 | * |
1726 | * Retrun true if the PCI device is PCI Express capable, false otherwise. |
1727 | */ |
1728 | static inline bool pci_is_pcie(struct pci_dev *dev) |
1729 | { |
1730 | return !!pci_pcie_cap(dev); |
1731 | } |
1732 | |
1733 | /** |
1734 | * pcie_caps_reg - get the PCIe Capabilities Register |
1735 | * @dev: PCI device |
1736 | */ |
1737 | static inline u16 pcie_caps_reg(const struct pci_dev *dev) |
1738 | { |
1739 | return dev->pcie_flags_reg; |
1740 | } |
1741 | |
1742 | /** |
1743 | * pci_pcie_type - get the PCIe device/port type |
1744 | * @dev: PCI device |
1745 | */ |
1746 | static inline int pci_pcie_type(const struct pci_dev *dev) |
1747 | { |
1748 | return (pcie_caps_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4; |
1749 | } |
1750 | |
1751 | void pci_request_acs(void); |
1752 | bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags); |
1753 | bool pci_acs_path_enabled(struct pci_dev *start, |
1754 | struct pci_dev *end, u16 acs_flags); |
1755 | |
1756 | #define PCI_VPD_LRDT 0x80 /* Large Resource Data Type */ |
1757 | #define PCI_VPD_LRDT_ID(x) (x | PCI_VPD_LRDT) |
1758 | |
1759 | /* Large Resource Data Type Tag Item Names */ |
1760 | #define PCI_VPD_LTIN_ID_STRING 0x02 /* Identifier String */ |
1761 | #define PCI_VPD_LTIN_RO_DATA 0x10 /* Read-Only Data */ |
1762 | #define PCI_VPD_LTIN_RW_DATA 0x11 /* Read-Write Data */ |
1763 | |
1764 | #define PCI_VPD_LRDT_ID_STRING PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING) |
1765 | #define PCI_VPD_LRDT_RO_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA) |
1766 | #define PCI_VPD_LRDT_RW_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA) |
1767 | |
1768 | /* Small Resource Data Type Tag Item Names */ |
1769 | #define PCI_VPD_STIN_END 0x78 /* End */ |
1770 | |
1771 | #define PCI_VPD_SRDT_END PCI_VPD_STIN_END |
1772 | |
1773 | #define PCI_VPD_SRDT_TIN_MASK 0x78 |
1774 | #define PCI_VPD_SRDT_LEN_MASK 0x07 |
1775 | |
1776 | #define PCI_VPD_LRDT_TAG_SIZE 3 |
1777 | #define PCI_VPD_SRDT_TAG_SIZE 1 |
1778 | |
1779 | #define PCI_VPD_INFO_FLD_HDR_SIZE 3 |
1780 | |
1781 | #define PCI_VPD_RO_KEYWORD_PARTNO "PN" |
1782 | #define PCI_VPD_RO_KEYWORD_MFR_ID "MN" |
1783 | #define PCI_VPD_RO_KEYWORD_VENDOR0 "V0" |
1784 | #define PCI_VPD_RO_KEYWORD_CHKSUM "RV" |
1785 | |
1786 | /** |
1787 | * pci_vpd_lrdt_size - Extracts the Large Resource Data Type length |
1788 | * @lrdt: Pointer to the beginning of the Large Resource Data Type tag |
1789 | * |
1790 | * Returns the extracted Large Resource Data Type length. |
1791 | */ |
1792 | static inline u16 pci_vpd_lrdt_size(const u8 *lrdt) |
1793 | { |
1794 | return (u16)lrdt[1] + ((u16)lrdt[2] << 8); |
1795 | } |
1796 | |
1797 | /** |
1798 | * pci_vpd_srdt_size - Extracts the Small Resource Data Type length |
1799 | * @lrdt: Pointer to the beginning of the Small Resource Data Type tag |
1800 | * |
1801 | * Returns the extracted Small Resource Data Type length. |
1802 | */ |
1803 | static inline u8 pci_vpd_srdt_size(const u8 *srdt) |
1804 | { |
1805 | return (*srdt) & PCI_VPD_SRDT_LEN_MASK; |
1806 | } |
1807 | |
1808 | /** |
1809 | * pci_vpd_info_field_size - Extracts the information field length |
1810 | * @lrdt: Pointer to the beginning of an information field header |
1811 | * |
1812 | * Returns the extracted information field length. |
1813 | */ |
1814 | static inline u8 pci_vpd_info_field_size(const u8 *info_field) |
1815 | { |
1816 | return info_field[2]; |
1817 | } |
1818 | |
1819 | /** |
1820 | * pci_vpd_find_tag - Locates the Resource Data Type tag provided |
1821 | * @buf: Pointer to buffered vpd data |
1822 | * @off: The offset into the buffer at which to begin the search |
1823 | * @len: The length of the vpd buffer |
1824 | * @rdt: The Resource Data Type to search for |
1825 | * |
1826 | * Returns the index where the Resource Data Type was found or |
1827 | * -ENOENT otherwise. |
1828 | */ |
1829 | int pci_vpd_find_tag(const u8 *buf, unsigned int off, unsigned int len, u8 rdt); |
1830 | |
1831 | /** |
1832 | * pci_vpd_find_info_keyword - Locates an information field keyword in the VPD |
1833 | * @buf: Pointer to buffered vpd data |
1834 | * @off: The offset into the buffer at which to begin the search |
1835 | * @len: The length of the buffer area, relative to off, in which to search |
1836 | * @kw: The keyword to search for |
1837 | * |
1838 | * Returns the index where the information field keyword was found or |
1839 | * -ENOENT otherwise. |
1840 | */ |
1841 | int pci_vpd_find_info_keyword(const u8 *buf, unsigned int off, |
1842 | unsigned int len, const char *kw); |
1843 | |
1844 | /* PCI <-> OF binding helpers */ |
1845 | #ifdef CONFIG_OF |
1846 | struct device_node; |
1847 | void pci_set_of_node(struct pci_dev *dev); |
1848 | void pci_release_of_node(struct pci_dev *dev); |
1849 | void pci_set_bus_of_node(struct pci_bus *bus); |
1850 | void pci_release_bus_of_node(struct pci_bus *bus); |
1851 | |
1852 | /* Arch may override this (weak) */ |
1853 | struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus); |
1854 | |
1855 | static inline struct device_node * |
1856 | pci_device_to_OF_node(const struct pci_dev *pdev) |
1857 | { |
1858 | return pdev ? pdev->dev.of_node : NULL; |
1859 | } |
1860 | |
1861 | static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus) |
1862 | { |
1863 | return bus ? bus->dev.of_node : NULL; |
1864 | } |
1865 | |
1866 | #else /* CONFIG_OF */ |
1867 | static inline void pci_set_of_node(struct pci_dev *dev) { } |
1868 | static inline void pci_release_of_node(struct pci_dev *dev) { } |
1869 | static inline void pci_set_bus_of_node(struct pci_bus *bus) { } |
1870 | static inline void pci_release_bus_of_node(struct pci_bus *bus) { } |
1871 | #endif /* CONFIG_OF */ |
1872 | |
1873 | #ifdef CONFIG_EEH |
1874 | static inline struct eeh_dev *pci_dev_to_eeh_dev(struct pci_dev *pdev) |
1875 | { |
1876 | return pdev->dev.archdata.edev; |
1877 | } |
1878 | #endif |
1879 | |
1880 | /** |
1881 | * pci_find_upstream_pcie_bridge - find upstream PCIe-to-PCI bridge of a device |
1882 | * @pdev: the PCI device |
1883 | * |
1884 | * if the device is PCIE, return NULL |
1885 | * if the device isn't connected to a PCIe bridge (that is its parent is a |
1886 | * legacy PCI bridge and the bridge is directly connected to bus 0), return its |
1887 | * parent |
1888 | */ |
1889 | struct pci_dev *pci_find_upstream_pcie_bridge(struct pci_dev *pdev); |
1890 | |
1891 | #endif /* LINUX_PCI_H */ |
1892 |
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