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1 | /* |
2 | * Definitions for DDR memories based on JEDEC specs |
3 | * |
4 | * Copyright (C) 2012 Texas Instruments, Inc. |
5 | * |
6 | * Aneesh V <aneesh@ti.com> |
7 | * |
8 | * This program is free software; you can redistribute it and/or modify |
9 | * it under the terms of the GNU General Public License version 2 as |
10 | * published by the Free Software Foundation. |
11 | */ |
12 | #ifndef __LINUX_JEDEC_DDR_H |
13 | #define __LINUX_JEDEC_DDR_H |
14 | |
15 | #include <linux/types.h> |
16 | |
17 | /* DDR Densities */ |
18 | #define DDR_DENSITY_64Mb 1 |
19 | #define DDR_DENSITY_128Mb 2 |
20 | #define DDR_DENSITY_256Mb 3 |
21 | #define DDR_DENSITY_512Mb 4 |
22 | #define DDR_DENSITY_1Gb 5 |
23 | #define DDR_DENSITY_2Gb 6 |
24 | #define DDR_DENSITY_4Gb 7 |
25 | #define DDR_DENSITY_8Gb 8 |
26 | #define DDR_DENSITY_16Gb 9 |
27 | #define DDR_DENSITY_32Gb 10 |
28 | |
29 | /* DDR type */ |
30 | #define DDR_TYPE_DDR2 1 |
31 | #define DDR_TYPE_DDR3 2 |
32 | #define DDR_TYPE_LPDDR2_S4 3 |
33 | #define DDR_TYPE_LPDDR2_S2 4 |
34 | #define DDR_TYPE_LPDDR2_NVM 5 |
35 | |
36 | /* DDR IO width */ |
37 | #define DDR_IO_WIDTH_4 1 |
38 | #define DDR_IO_WIDTH_8 2 |
39 | #define DDR_IO_WIDTH_16 3 |
40 | #define DDR_IO_WIDTH_32 4 |
41 | |
42 | /* Number of Row bits */ |
43 | #define R9 9 |
44 | #define R10 10 |
45 | #define R11 11 |
46 | #define R12 12 |
47 | #define R13 13 |
48 | #define R14 14 |
49 | #define R15 15 |
50 | #define R16 16 |
51 | |
52 | /* Number of Column bits */ |
53 | #define C7 7 |
54 | #define C8 8 |
55 | #define C9 9 |
56 | #define C10 10 |
57 | #define C11 11 |
58 | #define C12 12 |
59 | |
60 | /* Number of Banks */ |
61 | #define B1 0 |
62 | #define B2 1 |
63 | #define B4 2 |
64 | #define B8 3 |
65 | |
66 | /* Refresh rate in nano-seconds */ |
67 | #define T_REFI_15_6 15600 |
68 | #define T_REFI_7_8 7800 |
69 | #define T_REFI_3_9 3900 |
70 | |
71 | /* tRFC values */ |
72 | #define T_RFC_90 90000 |
73 | #define T_RFC_110 110000 |
74 | #define T_RFC_130 130000 |
75 | #define T_RFC_160 160000 |
76 | #define T_RFC_210 210000 |
77 | #define T_RFC_300 300000 |
78 | #define T_RFC_350 350000 |
79 | |
80 | /* Mode register numbers */ |
81 | #define DDR_MR0 0 |
82 | #define DDR_MR1 1 |
83 | #define DDR_MR2 2 |
84 | #define DDR_MR3 3 |
85 | #define DDR_MR4 4 |
86 | #define DDR_MR5 5 |
87 | #define DDR_MR6 6 |
88 | #define DDR_MR7 7 |
89 | #define DDR_MR8 8 |
90 | #define DDR_MR9 9 |
91 | #define DDR_MR10 10 |
92 | #define DDR_MR11 11 |
93 | #define DDR_MR16 16 |
94 | #define DDR_MR17 17 |
95 | #define DDR_MR18 18 |
96 | |
97 | /* |
98 | * LPDDR2 related defines |
99 | */ |
100 | |
101 | /* MR4 register fields */ |
102 | #define MR4_SDRAM_REF_RATE_SHIFT 0 |
103 | #define MR4_SDRAM_REF_RATE_MASK 7 |
104 | #define MR4_TUF_SHIFT 7 |
105 | #define MR4_TUF_MASK (1 << 7) |
106 | |
107 | /* MR4 SDRAM Refresh Rate field values */ |
108 | #define SDRAM_TEMP_NOMINAL 0x3 |
109 | #define SDRAM_TEMP_RESERVED_4 0x4 |
110 | #define SDRAM_TEMP_HIGH_DERATE_REFRESH 0x5 |
111 | #define SDRAM_TEMP_HIGH_DERATE_REFRESH_AND_TIMINGS 0x6 |
112 | #define SDRAM_TEMP_VERY_HIGH_SHUTDOWN 0x7 |
113 | |
114 | #define NUM_DDR_ADDR_TABLE_ENTRIES 11 |
115 | #define NUM_DDR_TIMING_TABLE_ENTRIES 4 |
116 | |
117 | /* Structure for DDR addressing info from the JEDEC spec */ |
118 | struct lpddr2_addressing { |
119 | u32 num_banks; |
120 | u32 tREFI_ns; |
121 | u32 tRFCab_ps; |
122 | }; |
123 | |
124 | /* |
125 | * Structure for timings from the LPDDR2 datasheet |
126 | * All parameters are in pico seconds(ps) unless explicitly indicated |
127 | * with a suffix like tRAS_max_ns below |
128 | */ |
129 | struct lpddr2_timings { |
130 | u32 max_freq; |
131 | u32 min_freq; |
132 | u32 tRPab; |
133 | u32 tRCD; |
134 | u32 tWR; |
135 | u32 tRAS_min; |
136 | u32 tRRD; |
137 | u32 tWTR; |
138 | u32 tXP; |
139 | u32 tRTP; |
140 | u32 tCKESR; |
141 | u32 tDQSCK_max; |
142 | u32 tDQSCK_max_derated; |
143 | u32 tFAW; |
144 | u32 tZQCS; |
145 | u32 tZQCL; |
146 | u32 tZQinit; |
147 | u32 tRAS_max_ns; |
148 | }; |
149 | |
150 | /* |
151 | * Min value for some parameters in terms of number of tCK cycles(nCK) |
152 | * Please set to zero parameters that are not valid for a given memory |
153 | * type |
154 | */ |
155 | struct lpddr2_min_tck { |
156 | u32 tRPab; |
157 | u32 tRCD; |
158 | u32 tWR; |
159 | u32 tRASmin; |
160 | u32 tRRD; |
161 | u32 tWTR; |
162 | u32 tXP; |
163 | u32 tRTP; |
164 | u32 tCKE; |
165 | u32 tCKESR; |
166 | u32 tFAW; |
167 | }; |
168 | |
169 | extern const struct lpddr2_addressing |
170 | lpddr2_jedec_addressing_table[NUM_DDR_ADDR_TABLE_ENTRIES]; |
171 | extern const struct lpddr2_timings |
172 | lpddr2_jedec_timings[NUM_DDR_TIMING_TABLE_ENTRIES]; |
173 | extern const struct lpddr2_min_tck lpddr2_jedec_min_tck; |
174 | |
175 | #endif /* __LINUX_JEDEC_DDR_H */ |
176 |
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