Root/
1 | #ifndef _LINUX_IRQ_H |
2 | #define _LINUX_IRQ_H |
3 | |
4 | /* |
5 | * Please do not include this file in generic code. There is currently |
6 | * no requirement for any architecture to implement anything held |
7 | * within this file. |
8 | * |
9 | * Thanks. --rmk |
10 | */ |
11 | |
12 | #include <linux/smp.h> |
13 | #include <linux/linkage.h> |
14 | #include <linux/cache.h> |
15 | #include <linux/spinlock.h> |
16 | #include <linux/cpumask.h> |
17 | #include <linux/gfp.h> |
18 | #include <linux/irqreturn.h> |
19 | #include <linux/irqnr.h> |
20 | #include <linux/errno.h> |
21 | #include <linux/topology.h> |
22 | #include <linux/wait.h> |
23 | |
24 | #include <asm/irq.h> |
25 | #include <asm/ptrace.h> |
26 | #include <asm/irq_regs.h> |
27 | |
28 | struct seq_file; |
29 | struct module; |
30 | struct irq_desc; |
31 | struct irq_data; |
32 | typedef void (*irq_flow_handler_t)(unsigned int irq, |
33 | struct irq_desc *desc); |
34 | typedef void (*irq_preflow_handler_t)(struct irq_data *data); |
35 | |
36 | /* |
37 | * IRQ line status. |
38 | * |
39 | * Bits 0-7 are the same as the IRQF_* bits in linux/interrupt.h |
40 | * |
41 | * IRQ_TYPE_NONE - default, unspecified type |
42 | * IRQ_TYPE_EDGE_RISING - rising edge triggered |
43 | * IRQ_TYPE_EDGE_FALLING - falling edge triggered |
44 | * IRQ_TYPE_EDGE_BOTH - rising and falling edge triggered |
45 | * IRQ_TYPE_LEVEL_HIGH - high level triggered |
46 | * IRQ_TYPE_LEVEL_LOW - low level triggered |
47 | * IRQ_TYPE_LEVEL_MASK - Mask to filter out the level bits |
48 | * IRQ_TYPE_SENSE_MASK - Mask for all the above bits |
49 | * IRQ_TYPE_DEFAULT - For use by some PICs to ask irq_set_type |
50 | * to setup the HW to a sane default (used |
51 | * by irqdomain map() callbacks to synchronize |
52 | * the HW state and SW flags for a newly |
53 | * allocated descriptor). |
54 | * |
55 | * IRQ_TYPE_PROBE - Special flag for probing in progress |
56 | * |
57 | * Bits which can be modified via irq_set/clear/modify_status_flags() |
58 | * IRQ_LEVEL - Interrupt is level type. Will be also |
59 | * updated in the code when the above trigger |
60 | * bits are modified via irq_set_irq_type() |
61 | * IRQ_PER_CPU - Mark an interrupt PER_CPU. Will protect |
62 | * it from affinity setting |
63 | * IRQ_NOPROBE - Interrupt cannot be probed by autoprobing |
64 | * IRQ_NOREQUEST - Interrupt cannot be requested via |
65 | * request_irq() |
66 | * IRQ_NOTHREAD - Interrupt cannot be threaded |
67 | * IRQ_NOAUTOEN - Interrupt is not automatically enabled in |
68 | * request/setup_irq() |
69 | * IRQ_NO_BALANCING - Interrupt cannot be balanced (affinity set) |
70 | * IRQ_MOVE_PCNTXT - Interrupt can be migrated from process context |
71 | * IRQ_NESTED_TRHEAD - Interrupt nests into another thread |
72 | * IRQ_PER_CPU_DEVID - Dev_id is a per-cpu variable |
73 | * IRQ_IS_POLLED - Always polled by another interrupt. Exclude |
74 | * it from the spurious interrupt detection |
75 | * mechanism and from core side polling. |
76 | */ |
77 | enum { |
78 | IRQ_TYPE_NONE = 0x00000000, |
79 | IRQ_TYPE_EDGE_RISING = 0x00000001, |
80 | IRQ_TYPE_EDGE_FALLING = 0x00000002, |
81 | IRQ_TYPE_EDGE_BOTH = (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING), |
82 | IRQ_TYPE_LEVEL_HIGH = 0x00000004, |
83 | IRQ_TYPE_LEVEL_LOW = 0x00000008, |
84 | IRQ_TYPE_LEVEL_MASK = (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH), |
85 | IRQ_TYPE_SENSE_MASK = 0x0000000f, |
86 | IRQ_TYPE_DEFAULT = IRQ_TYPE_SENSE_MASK, |
87 | |
88 | IRQ_TYPE_PROBE = 0x00000010, |
89 | |
90 | IRQ_LEVEL = (1 << 8), |
91 | IRQ_PER_CPU = (1 << 9), |
92 | IRQ_NOPROBE = (1 << 10), |
93 | IRQ_NOREQUEST = (1 << 11), |
94 | IRQ_NOAUTOEN = (1 << 12), |
95 | IRQ_NO_BALANCING = (1 << 13), |
96 | IRQ_MOVE_PCNTXT = (1 << 14), |
97 | IRQ_NESTED_THREAD = (1 << 15), |
98 | IRQ_NOTHREAD = (1 << 16), |
99 | IRQ_PER_CPU_DEVID = (1 << 17), |
100 | IRQ_IS_POLLED = (1 << 18), |
101 | }; |
102 | |
103 | #define IRQF_MODIFY_MASK \ |
104 | (IRQ_TYPE_SENSE_MASK | IRQ_NOPROBE | IRQ_NOREQUEST | \ |
105 | IRQ_NOAUTOEN | IRQ_MOVE_PCNTXT | IRQ_LEVEL | IRQ_NO_BALANCING | \ |
106 | IRQ_PER_CPU | IRQ_NESTED_THREAD | IRQ_NOTHREAD | IRQ_PER_CPU_DEVID | \ |
107 | IRQ_IS_POLLED) |
108 | |
109 | #define IRQ_NO_BALANCING_MASK (IRQ_PER_CPU | IRQ_NO_BALANCING) |
110 | |
111 | /* |
112 | * Return value for chip->irq_set_affinity() |
113 | * |
114 | * IRQ_SET_MASK_OK - OK, core updates irq_data.affinity |
115 | * IRQ_SET_MASK_NOCPY - OK, chip did update irq_data.affinity |
116 | */ |
117 | enum { |
118 | IRQ_SET_MASK_OK = 0, |
119 | IRQ_SET_MASK_OK_NOCOPY, |
120 | }; |
121 | |
122 | struct msi_desc; |
123 | struct irq_domain; |
124 | |
125 | /** |
126 | * struct irq_data - per irq and irq chip data passed down to chip functions |
127 | * @mask: precomputed bitmask for accessing the chip registers |
128 | * @irq: interrupt number |
129 | * @hwirq: hardware interrupt number, local to the interrupt domain |
130 | * @node: node index useful for balancing |
131 | * @state_use_accessors: status information for irq chip functions. |
132 | * Use accessor functions to deal with it |
133 | * @chip: low level interrupt hardware access |
134 | * @domain: Interrupt translation domain; responsible for mapping |
135 | * between hwirq number and linux irq number. |
136 | * @handler_data: per-IRQ data for the irq_chip methods |
137 | * @chip_data: platform-specific per-chip private data for the chip |
138 | * methods, to allow shared chip implementations |
139 | * @msi_desc: MSI descriptor |
140 | * @affinity: IRQ affinity on SMP |
141 | * |
142 | * The fields here need to overlay the ones in irq_desc until we |
143 | * cleaned up the direct references and switched everything over to |
144 | * irq_data. |
145 | */ |
146 | struct irq_data { |
147 | u32 mask; |
148 | unsigned int irq; |
149 | unsigned long hwirq; |
150 | unsigned int node; |
151 | unsigned int state_use_accessors; |
152 | struct irq_chip *chip; |
153 | struct irq_domain *domain; |
154 | void *handler_data; |
155 | void *chip_data; |
156 | struct msi_desc *msi_desc; |
157 | cpumask_var_t affinity; |
158 | }; |
159 | |
160 | /* |
161 | * Bit masks for irq_data.state |
162 | * |
163 | * IRQD_TRIGGER_MASK - Mask for the trigger type bits |
164 | * IRQD_SETAFFINITY_PENDING - Affinity setting is pending |
165 | * IRQD_NO_BALANCING - Balancing disabled for this IRQ |
166 | * IRQD_PER_CPU - Interrupt is per cpu |
167 | * IRQD_AFFINITY_SET - Interrupt affinity was set |
168 | * IRQD_LEVEL - Interrupt is level triggered |
169 | * IRQD_WAKEUP_STATE - Interrupt is configured for wakeup |
170 | * from suspend |
171 | * IRDQ_MOVE_PCNTXT - Interrupt can be moved in process |
172 | * context |
173 | * IRQD_IRQ_DISABLED - Disabled state of the interrupt |
174 | * IRQD_IRQ_MASKED - Masked state of the interrupt |
175 | * IRQD_IRQ_INPROGRESS - In progress state of the interrupt |
176 | */ |
177 | enum { |
178 | IRQD_TRIGGER_MASK = 0xf, |
179 | IRQD_SETAFFINITY_PENDING = (1 << 8), |
180 | IRQD_NO_BALANCING = (1 << 10), |
181 | IRQD_PER_CPU = (1 << 11), |
182 | IRQD_AFFINITY_SET = (1 << 12), |
183 | IRQD_LEVEL = (1 << 13), |
184 | IRQD_WAKEUP_STATE = (1 << 14), |
185 | IRQD_MOVE_PCNTXT = (1 << 15), |
186 | IRQD_IRQ_DISABLED = (1 << 16), |
187 | IRQD_IRQ_MASKED = (1 << 17), |
188 | IRQD_IRQ_INPROGRESS = (1 << 18), |
189 | }; |
190 | |
191 | static inline bool irqd_is_setaffinity_pending(struct irq_data *d) |
192 | { |
193 | return d->state_use_accessors & IRQD_SETAFFINITY_PENDING; |
194 | } |
195 | |
196 | static inline bool irqd_is_per_cpu(struct irq_data *d) |
197 | { |
198 | return d->state_use_accessors & IRQD_PER_CPU; |
199 | } |
200 | |
201 | static inline bool irqd_can_balance(struct irq_data *d) |
202 | { |
203 | return !(d->state_use_accessors & (IRQD_PER_CPU | IRQD_NO_BALANCING)); |
204 | } |
205 | |
206 | static inline bool irqd_affinity_was_set(struct irq_data *d) |
207 | { |
208 | return d->state_use_accessors & IRQD_AFFINITY_SET; |
209 | } |
210 | |
211 | static inline void irqd_mark_affinity_was_set(struct irq_data *d) |
212 | { |
213 | d->state_use_accessors |= IRQD_AFFINITY_SET; |
214 | } |
215 | |
216 | static inline u32 irqd_get_trigger_type(struct irq_data *d) |
217 | { |
218 | return d->state_use_accessors & IRQD_TRIGGER_MASK; |
219 | } |
220 | |
221 | /* |
222 | * Must only be called inside irq_chip.irq_set_type() functions. |
223 | */ |
224 | static inline void irqd_set_trigger_type(struct irq_data *d, u32 type) |
225 | { |
226 | d->state_use_accessors &= ~IRQD_TRIGGER_MASK; |
227 | d->state_use_accessors |= type & IRQD_TRIGGER_MASK; |
228 | } |
229 | |
230 | static inline bool irqd_is_level_type(struct irq_data *d) |
231 | { |
232 | return d->state_use_accessors & IRQD_LEVEL; |
233 | } |
234 | |
235 | static inline bool irqd_is_wakeup_set(struct irq_data *d) |
236 | { |
237 | return d->state_use_accessors & IRQD_WAKEUP_STATE; |
238 | } |
239 | |
240 | static inline bool irqd_can_move_in_process_context(struct irq_data *d) |
241 | { |
242 | return d->state_use_accessors & IRQD_MOVE_PCNTXT; |
243 | } |
244 | |
245 | static inline bool irqd_irq_disabled(struct irq_data *d) |
246 | { |
247 | return d->state_use_accessors & IRQD_IRQ_DISABLED; |
248 | } |
249 | |
250 | static inline bool irqd_irq_masked(struct irq_data *d) |
251 | { |
252 | return d->state_use_accessors & IRQD_IRQ_MASKED; |
253 | } |
254 | |
255 | static inline bool irqd_irq_inprogress(struct irq_data *d) |
256 | { |
257 | return d->state_use_accessors & IRQD_IRQ_INPROGRESS; |
258 | } |
259 | |
260 | /* |
261 | * Functions for chained handlers which can be enabled/disabled by the |
262 | * standard disable_irq/enable_irq calls. Must be called with |
263 | * irq_desc->lock held. |
264 | */ |
265 | static inline void irqd_set_chained_irq_inprogress(struct irq_data *d) |
266 | { |
267 | d->state_use_accessors |= IRQD_IRQ_INPROGRESS; |
268 | } |
269 | |
270 | static inline void irqd_clr_chained_irq_inprogress(struct irq_data *d) |
271 | { |
272 | d->state_use_accessors &= ~IRQD_IRQ_INPROGRESS; |
273 | } |
274 | |
275 | static inline irq_hw_number_t irqd_to_hwirq(struct irq_data *d) |
276 | { |
277 | return d->hwirq; |
278 | } |
279 | |
280 | /** |
281 | * struct irq_chip - hardware interrupt chip descriptor |
282 | * |
283 | * @name: name for /proc/interrupts |
284 | * @irq_startup: start up the interrupt (defaults to ->enable if NULL) |
285 | * @irq_shutdown: shut down the interrupt (defaults to ->disable if NULL) |
286 | * @irq_enable: enable the interrupt (defaults to chip->unmask if NULL) |
287 | * @irq_disable: disable the interrupt |
288 | * @irq_ack: start of a new interrupt |
289 | * @irq_mask: mask an interrupt source |
290 | * @irq_mask_ack: ack and mask an interrupt source |
291 | * @irq_unmask: unmask an interrupt source |
292 | * @irq_eoi: end of interrupt |
293 | * @irq_set_affinity: set the CPU affinity on SMP machines |
294 | * @irq_retrigger: resend an IRQ to the CPU |
295 | * @irq_set_type: set the flow type (IRQ_TYPE_LEVEL/etc.) of an IRQ |
296 | * @irq_set_wake: enable/disable power-management wake-on of an IRQ |
297 | * @irq_bus_lock: function to lock access to slow bus (i2c) chips |
298 | * @irq_bus_sync_unlock:function to sync and unlock slow bus (i2c) chips |
299 | * @irq_cpu_online: configure an interrupt source for a secondary CPU |
300 | * @irq_cpu_offline: un-configure an interrupt source for a secondary CPU |
301 | * @irq_suspend: function called from core code on suspend once per chip |
302 | * @irq_resume: function called from core code on resume once per chip |
303 | * @irq_pm_shutdown: function called from core code on shutdown once per chip |
304 | * @irq_calc_mask: Optional function to set irq_data.mask for special cases |
305 | * @irq_print_chip: optional to print special chip info in show_interrupts |
306 | * @flags: chip specific flags |
307 | */ |
308 | struct irq_chip { |
309 | const char *name; |
310 | unsigned int (*irq_startup)(struct irq_data *data); |
311 | void (*irq_shutdown)(struct irq_data *data); |
312 | void (*irq_enable)(struct irq_data *data); |
313 | void (*irq_disable)(struct irq_data *data); |
314 | |
315 | void (*irq_ack)(struct irq_data *data); |
316 | void (*irq_mask)(struct irq_data *data); |
317 | void (*irq_mask_ack)(struct irq_data *data); |
318 | void (*irq_unmask)(struct irq_data *data); |
319 | void (*irq_eoi)(struct irq_data *data); |
320 | |
321 | int (*irq_set_affinity)(struct irq_data *data, const struct cpumask *dest, bool force); |
322 | int (*irq_retrigger)(struct irq_data *data); |
323 | int (*irq_set_type)(struct irq_data *data, unsigned int flow_type); |
324 | int (*irq_set_wake)(struct irq_data *data, unsigned int on); |
325 | |
326 | void (*irq_bus_lock)(struct irq_data *data); |
327 | void (*irq_bus_sync_unlock)(struct irq_data *data); |
328 | |
329 | void (*irq_cpu_online)(struct irq_data *data); |
330 | void (*irq_cpu_offline)(struct irq_data *data); |
331 | |
332 | void (*irq_suspend)(struct irq_data *data); |
333 | void (*irq_resume)(struct irq_data *data); |
334 | void (*irq_pm_shutdown)(struct irq_data *data); |
335 | |
336 | void (*irq_calc_mask)(struct irq_data *data); |
337 | |
338 | void (*irq_print_chip)(struct irq_data *data, struct seq_file *p); |
339 | |
340 | unsigned long flags; |
341 | }; |
342 | |
343 | /* |
344 | * irq_chip specific flags |
345 | * |
346 | * IRQCHIP_SET_TYPE_MASKED: Mask before calling chip.irq_set_type() |
347 | * IRQCHIP_EOI_IF_HANDLED: Only issue irq_eoi() when irq was handled |
348 | * IRQCHIP_MASK_ON_SUSPEND: Mask non wake irqs in the suspend path |
349 | * IRQCHIP_ONOFFLINE_ENABLED: Only call irq_on/off_line callbacks |
350 | * when irq enabled |
351 | * IRQCHIP_SKIP_SET_WAKE: Skip chip.irq_set_wake(), for this irq chip |
352 | */ |
353 | enum { |
354 | IRQCHIP_SET_TYPE_MASKED = (1 << 0), |
355 | IRQCHIP_EOI_IF_HANDLED = (1 << 1), |
356 | IRQCHIP_MASK_ON_SUSPEND = (1 << 2), |
357 | IRQCHIP_ONOFFLINE_ENABLED = (1 << 3), |
358 | IRQCHIP_SKIP_SET_WAKE = (1 << 4), |
359 | IRQCHIP_ONESHOT_SAFE = (1 << 5), |
360 | }; |
361 | |
362 | /* This include will go away once we isolated irq_desc usage to core code */ |
363 | #include <linux/irqdesc.h> |
364 | |
365 | /* |
366 | * Pick up the arch-dependent methods: |
367 | */ |
368 | #include <asm/hw_irq.h> |
369 | |
370 | #ifndef NR_IRQS_LEGACY |
371 | # define NR_IRQS_LEGACY 0 |
372 | #endif |
373 | |
374 | #ifndef ARCH_IRQ_INIT_FLAGS |
375 | # define ARCH_IRQ_INIT_FLAGS 0 |
376 | #endif |
377 | |
378 | #define IRQ_DEFAULT_INIT_FLAGS ARCH_IRQ_INIT_FLAGS |
379 | |
380 | struct irqaction; |
381 | extern int setup_irq(unsigned int irq, struct irqaction *new); |
382 | extern void remove_irq(unsigned int irq, struct irqaction *act); |
383 | extern int setup_percpu_irq(unsigned int irq, struct irqaction *new); |
384 | extern void remove_percpu_irq(unsigned int irq, struct irqaction *act); |
385 | |
386 | extern void irq_cpu_online(void); |
387 | extern void irq_cpu_offline(void); |
388 | extern int __irq_set_affinity_locked(struct irq_data *data, const struct cpumask *cpumask); |
389 | |
390 | #if defined(CONFIG_SMP) && defined(CONFIG_GENERIC_PENDING_IRQ) |
391 | void irq_move_irq(struct irq_data *data); |
392 | void irq_move_masked_irq(struct irq_data *data); |
393 | #else |
394 | static inline void irq_move_irq(struct irq_data *data) { } |
395 | static inline void irq_move_masked_irq(struct irq_data *data) { } |
396 | #endif |
397 | |
398 | extern int no_irq_affinity; |
399 | |
400 | #ifdef CONFIG_HARDIRQS_SW_RESEND |
401 | int irq_set_parent(int irq, int parent_irq); |
402 | #else |
403 | static inline int irq_set_parent(int irq, int parent_irq) |
404 | { |
405 | return 0; |
406 | } |
407 | #endif |
408 | |
409 | /* |
410 | * Built-in IRQ handlers for various IRQ types, |
411 | * callable via desc->handle_irq() |
412 | */ |
413 | extern void handle_level_irq(unsigned int irq, struct irq_desc *desc); |
414 | extern void handle_fasteoi_irq(unsigned int irq, struct irq_desc *desc); |
415 | extern void handle_edge_irq(unsigned int irq, struct irq_desc *desc); |
416 | extern void handle_edge_eoi_irq(unsigned int irq, struct irq_desc *desc); |
417 | extern void handle_simple_irq(unsigned int irq, struct irq_desc *desc); |
418 | extern void handle_percpu_irq(unsigned int irq, struct irq_desc *desc); |
419 | extern void handle_percpu_devid_irq(unsigned int irq, struct irq_desc *desc); |
420 | extern void handle_bad_irq(unsigned int irq, struct irq_desc *desc); |
421 | extern void handle_nested_irq(unsigned int irq); |
422 | |
423 | /* Handling of unhandled and spurious interrupts: */ |
424 | extern void note_interrupt(unsigned int irq, struct irq_desc *desc, |
425 | irqreturn_t action_ret); |
426 | |
427 | |
428 | /* Enable/disable irq debugging output: */ |
429 | extern int noirqdebug_setup(char *str); |
430 | |
431 | /* Checks whether the interrupt can be requested by request_irq(): */ |
432 | extern int can_request_irq(unsigned int irq, unsigned long irqflags); |
433 | |
434 | /* Dummy irq-chip implementations: */ |
435 | extern struct irq_chip no_irq_chip; |
436 | extern struct irq_chip dummy_irq_chip; |
437 | |
438 | extern void |
439 | irq_set_chip_and_handler_name(unsigned int irq, struct irq_chip *chip, |
440 | irq_flow_handler_t handle, const char *name); |
441 | |
442 | static inline void irq_set_chip_and_handler(unsigned int irq, struct irq_chip *chip, |
443 | irq_flow_handler_t handle) |
444 | { |
445 | irq_set_chip_and_handler_name(irq, chip, handle, NULL); |
446 | } |
447 | |
448 | extern int irq_set_percpu_devid(unsigned int irq); |
449 | |
450 | extern void |
451 | __irq_set_handler(unsigned int irq, irq_flow_handler_t handle, int is_chained, |
452 | const char *name); |
453 | |
454 | static inline void |
455 | irq_set_handler(unsigned int irq, irq_flow_handler_t handle) |
456 | { |
457 | __irq_set_handler(irq, handle, 0, NULL); |
458 | } |
459 | |
460 | /* |
461 | * Set a highlevel chained flow handler for a given IRQ. |
462 | * (a chained handler is automatically enabled and set to |
463 | * IRQ_NOREQUEST, IRQ_NOPROBE, and IRQ_NOTHREAD) |
464 | */ |
465 | static inline void |
466 | irq_set_chained_handler(unsigned int irq, irq_flow_handler_t handle) |
467 | { |
468 | __irq_set_handler(irq, handle, 1, NULL); |
469 | } |
470 | |
471 | void irq_modify_status(unsigned int irq, unsigned long clr, unsigned long set); |
472 | |
473 | static inline void irq_set_status_flags(unsigned int irq, unsigned long set) |
474 | { |
475 | irq_modify_status(irq, 0, set); |
476 | } |
477 | |
478 | static inline void irq_clear_status_flags(unsigned int irq, unsigned long clr) |
479 | { |
480 | irq_modify_status(irq, clr, 0); |
481 | } |
482 | |
483 | static inline void irq_set_noprobe(unsigned int irq) |
484 | { |
485 | irq_modify_status(irq, 0, IRQ_NOPROBE); |
486 | } |
487 | |
488 | static inline void irq_set_probe(unsigned int irq) |
489 | { |
490 | irq_modify_status(irq, IRQ_NOPROBE, 0); |
491 | } |
492 | |
493 | static inline void irq_set_nothread(unsigned int irq) |
494 | { |
495 | irq_modify_status(irq, 0, IRQ_NOTHREAD); |
496 | } |
497 | |
498 | static inline void irq_set_thread(unsigned int irq) |
499 | { |
500 | irq_modify_status(irq, IRQ_NOTHREAD, 0); |
501 | } |
502 | |
503 | static inline void irq_set_nested_thread(unsigned int irq, bool nest) |
504 | { |
505 | if (nest) |
506 | irq_set_status_flags(irq, IRQ_NESTED_THREAD); |
507 | else |
508 | irq_clear_status_flags(irq, IRQ_NESTED_THREAD); |
509 | } |
510 | |
511 | static inline void irq_set_percpu_devid_flags(unsigned int irq) |
512 | { |
513 | irq_set_status_flags(irq, |
514 | IRQ_NOAUTOEN | IRQ_PER_CPU | IRQ_NOTHREAD | |
515 | IRQ_NOPROBE | IRQ_PER_CPU_DEVID); |
516 | } |
517 | |
518 | /* Handle dynamic irq creation and destruction */ |
519 | extern unsigned int create_irq_nr(unsigned int irq_want, int node); |
520 | extern unsigned int __create_irqs(unsigned int from, unsigned int count, |
521 | int node); |
522 | extern int create_irq(void); |
523 | extern void destroy_irq(unsigned int irq); |
524 | extern void destroy_irqs(unsigned int irq, unsigned int count); |
525 | |
526 | /* |
527 | * Dynamic irq helper functions. Obsolete. Use irq_alloc_desc* and |
528 | * irq_free_desc instead. |
529 | */ |
530 | extern void dynamic_irq_cleanup(unsigned int irq); |
531 | static inline void dynamic_irq_init(unsigned int irq) |
532 | { |
533 | dynamic_irq_cleanup(irq); |
534 | } |
535 | |
536 | /* Set/get chip/data for an IRQ: */ |
537 | extern int irq_set_chip(unsigned int irq, struct irq_chip *chip); |
538 | extern int irq_set_handler_data(unsigned int irq, void *data); |
539 | extern int irq_set_chip_data(unsigned int irq, void *data); |
540 | extern int irq_set_irq_type(unsigned int irq, unsigned int type); |
541 | extern int irq_set_msi_desc(unsigned int irq, struct msi_desc *entry); |
542 | extern int irq_set_msi_desc_off(unsigned int irq_base, unsigned int irq_offset, |
543 | struct msi_desc *entry); |
544 | extern struct irq_data *irq_get_irq_data(unsigned int irq); |
545 | |
546 | static inline struct irq_chip *irq_get_chip(unsigned int irq) |
547 | { |
548 | struct irq_data *d = irq_get_irq_data(irq); |
549 | return d ? d->chip : NULL; |
550 | } |
551 | |
552 | static inline struct irq_chip *irq_data_get_irq_chip(struct irq_data *d) |
553 | { |
554 | return d->chip; |
555 | } |
556 | |
557 | static inline void *irq_get_chip_data(unsigned int irq) |
558 | { |
559 | struct irq_data *d = irq_get_irq_data(irq); |
560 | return d ? d->chip_data : NULL; |
561 | } |
562 | |
563 | static inline void *irq_data_get_irq_chip_data(struct irq_data *d) |
564 | { |
565 | return d->chip_data; |
566 | } |
567 | |
568 | static inline void *irq_get_handler_data(unsigned int irq) |
569 | { |
570 | struct irq_data *d = irq_get_irq_data(irq); |
571 | return d ? d->handler_data : NULL; |
572 | } |
573 | |
574 | static inline void *irq_data_get_irq_handler_data(struct irq_data *d) |
575 | { |
576 | return d->handler_data; |
577 | } |
578 | |
579 | static inline struct msi_desc *irq_get_msi_desc(unsigned int irq) |
580 | { |
581 | struct irq_data *d = irq_get_irq_data(irq); |
582 | return d ? d->msi_desc : NULL; |
583 | } |
584 | |
585 | static inline struct msi_desc *irq_data_get_msi(struct irq_data *d) |
586 | { |
587 | return d->msi_desc; |
588 | } |
589 | |
590 | static inline u32 irq_get_trigger_type(unsigned int irq) |
591 | { |
592 | struct irq_data *d = irq_get_irq_data(irq); |
593 | return d ? irqd_get_trigger_type(d) : 0; |
594 | } |
595 | |
596 | int __irq_alloc_descs(int irq, unsigned int from, unsigned int cnt, int node, |
597 | struct module *owner); |
598 | |
599 | /* use macros to avoid needing export.h for THIS_MODULE */ |
600 | #define irq_alloc_descs(irq, from, cnt, node) \ |
601 | __irq_alloc_descs(irq, from, cnt, node, THIS_MODULE) |
602 | |
603 | #define irq_alloc_desc(node) \ |
604 | irq_alloc_descs(-1, 0, 1, node) |
605 | |
606 | #define irq_alloc_desc_at(at, node) \ |
607 | irq_alloc_descs(at, at, 1, node) |
608 | |
609 | #define irq_alloc_desc_from(from, node) \ |
610 | irq_alloc_descs(-1, from, 1, node) |
611 | |
612 | #define irq_alloc_descs_from(from, cnt, node) \ |
613 | irq_alloc_descs(-1, from, cnt, node) |
614 | |
615 | void irq_free_descs(unsigned int irq, unsigned int cnt); |
616 | int irq_reserve_irqs(unsigned int from, unsigned int cnt); |
617 | |
618 | static inline void irq_free_desc(unsigned int irq) |
619 | { |
620 | irq_free_descs(irq, 1); |
621 | } |
622 | |
623 | static inline int irq_reserve_irq(unsigned int irq) |
624 | { |
625 | return irq_reserve_irqs(irq, 1); |
626 | } |
627 | |
628 | #ifndef irq_reg_writel |
629 | # define irq_reg_writel(val, addr) writel(val, addr) |
630 | #endif |
631 | #ifndef irq_reg_readl |
632 | # define irq_reg_readl(addr) readl(addr) |
633 | #endif |
634 | |
635 | /** |
636 | * struct irq_chip_regs - register offsets for struct irq_gci |
637 | * @enable: Enable register offset to reg_base |
638 | * @disable: Disable register offset to reg_base |
639 | * @mask: Mask register offset to reg_base |
640 | * @ack: Ack register offset to reg_base |
641 | * @eoi: Eoi register offset to reg_base |
642 | * @type: Type configuration register offset to reg_base |
643 | * @polarity: Polarity configuration register offset to reg_base |
644 | */ |
645 | struct irq_chip_regs { |
646 | unsigned long enable; |
647 | unsigned long disable; |
648 | unsigned long mask; |
649 | unsigned long ack; |
650 | unsigned long eoi; |
651 | unsigned long type; |
652 | unsigned long polarity; |
653 | }; |
654 | |
655 | /** |
656 | * struct irq_chip_type - Generic interrupt chip instance for a flow type |
657 | * @chip: The real interrupt chip which provides the callbacks |
658 | * @regs: Register offsets for this chip |
659 | * @handler: Flow handler associated with this chip |
660 | * @type: Chip can handle these flow types |
661 | * @mask_cache_priv: Cached mask register private to the chip type |
662 | * @mask_cache: Pointer to cached mask register |
663 | * |
664 | * A irq_generic_chip can have several instances of irq_chip_type when |
665 | * it requires different functions and register offsets for different |
666 | * flow types. |
667 | */ |
668 | struct irq_chip_type { |
669 | struct irq_chip chip; |
670 | struct irq_chip_regs regs; |
671 | irq_flow_handler_t handler; |
672 | u32 type; |
673 | u32 mask_cache_priv; |
674 | u32 *mask_cache; |
675 | }; |
676 | |
677 | /** |
678 | * struct irq_chip_generic - Generic irq chip data structure |
679 | * @lock: Lock to protect register and cache data access |
680 | * @reg_base: Register base address (virtual) |
681 | * @irq_base: Interrupt base nr for this chip |
682 | * @irq_cnt: Number of interrupts handled by this chip |
683 | * @mask_cache: Cached mask register shared between all chip types |
684 | * @type_cache: Cached type register |
685 | * @polarity_cache: Cached polarity register |
686 | * @wake_enabled: Interrupt can wakeup from suspend |
687 | * @wake_active: Interrupt is marked as an wakeup from suspend source |
688 | * @num_ct: Number of available irq_chip_type instances (usually 1) |
689 | * @private: Private data for non generic chip callbacks |
690 | * @installed: bitfield to denote installed interrupts |
691 | * @unused: bitfield to denote unused interrupts |
692 | * @domain: irq domain pointer |
693 | * @list: List head for keeping track of instances |
694 | * @chip_types: Array of interrupt irq_chip_types |
695 | * |
696 | * Note, that irq_chip_generic can have multiple irq_chip_type |
697 | * implementations which can be associated to a particular irq line of |
698 | * an irq_chip_generic instance. That allows to share and protect |
699 | * state in an irq_chip_generic instance when we need to implement |
700 | * different flow mechanisms (level/edge) for it. |
701 | */ |
702 | struct irq_chip_generic { |
703 | raw_spinlock_t lock; |
704 | void __iomem *reg_base; |
705 | unsigned int irq_base; |
706 | unsigned int irq_cnt; |
707 | u32 mask_cache; |
708 | u32 type_cache; |
709 | u32 polarity_cache; |
710 | u32 wake_enabled; |
711 | u32 wake_active; |
712 | unsigned int num_ct; |
713 | void *private; |
714 | unsigned long installed; |
715 | unsigned long unused; |
716 | struct irq_domain *domain; |
717 | struct list_head list; |
718 | struct irq_chip_type chip_types[0]; |
719 | }; |
720 | |
721 | /** |
722 | * enum irq_gc_flags - Initialization flags for generic irq chips |
723 | * @IRQ_GC_INIT_MASK_CACHE: Initialize the mask_cache by reading mask reg |
724 | * @IRQ_GC_INIT_NESTED_LOCK: Set the lock class of the irqs to nested for |
725 | * irq chips which need to call irq_set_wake() on |
726 | * the parent irq. Usually GPIO implementations |
727 | * @IRQ_GC_MASK_CACHE_PER_TYPE: Mask cache is chip type private |
728 | * @IRQ_GC_NO_MASK: Do not calculate irq_data->mask |
729 | */ |
730 | enum irq_gc_flags { |
731 | IRQ_GC_INIT_MASK_CACHE = 1 << 0, |
732 | IRQ_GC_INIT_NESTED_LOCK = 1 << 1, |
733 | IRQ_GC_MASK_CACHE_PER_TYPE = 1 << 2, |
734 | IRQ_GC_NO_MASK = 1 << 3, |
735 | }; |
736 | |
737 | /* |
738 | * struct irq_domain_chip_generic - Generic irq chip data structure for irq domains |
739 | * @irqs_per_chip: Number of interrupts per chip |
740 | * @num_chips: Number of chips |
741 | * @irq_flags_to_set: IRQ* flags to set on irq setup |
742 | * @irq_flags_to_clear: IRQ* flags to clear on irq setup |
743 | * @gc_flags: Generic chip specific setup flags |
744 | * @gc: Array of pointers to generic interrupt chips |
745 | */ |
746 | struct irq_domain_chip_generic { |
747 | unsigned int irqs_per_chip; |
748 | unsigned int num_chips; |
749 | unsigned int irq_flags_to_clear; |
750 | unsigned int irq_flags_to_set; |
751 | enum irq_gc_flags gc_flags; |
752 | struct irq_chip_generic *gc[0]; |
753 | }; |
754 | |
755 | /* Generic chip callback functions */ |
756 | void irq_gc_noop(struct irq_data *d); |
757 | void irq_gc_mask_disable_reg(struct irq_data *d); |
758 | void irq_gc_mask_set_bit(struct irq_data *d); |
759 | void irq_gc_mask_clr_bit(struct irq_data *d); |
760 | void irq_gc_unmask_enable_reg(struct irq_data *d); |
761 | void irq_gc_ack_set_bit(struct irq_data *d); |
762 | void irq_gc_ack_clr_bit(struct irq_data *d); |
763 | void irq_gc_mask_disable_reg_and_ack(struct irq_data *d); |
764 | void irq_gc_eoi(struct irq_data *d); |
765 | int irq_gc_set_wake(struct irq_data *d, unsigned int on); |
766 | |
767 | /* Setup functions for irq_chip_generic */ |
768 | struct irq_chip_generic * |
769 | irq_alloc_generic_chip(const char *name, int nr_ct, unsigned int irq_base, |
770 | void __iomem *reg_base, irq_flow_handler_t handler); |
771 | void irq_setup_generic_chip(struct irq_chip_generic *gc, u32 msk, |
772 | enum irq_gc_flags flags, unsigned int clr, |
773 | unsigned int set); |
774 | int irq_setup_alt_chip(struct irq_data *d, unsigned int type); |
775 | void irq_remove_generic_chip(struct irq_chip_generic *gc, u32 msk, |
776 | unsigned int clr, unsigned int set); |
777 | |
778 | struct irq_chip_generic *irq_get_domain_generic_chip(struct irq_domain *d, unsigned int hw_irq); |
779 | int irq_alloc_domain_generic_chips(struct irq_domain *d, int irqs_per_chip, |
780 | int num_ct, const char *name, |
781 | irq_flow_handler_t handler, |
782 | unsigned int clr, unsigned int set, |
783 | enum irq_gc_flags flags); |
784 | |
785 | |
786 | static inline struct irq_chip_type *irq_data_get_chip_type(struct irq_data *d) |
787 | { |
788 | return container_of(d->chip, struct irq_chip_type, chip); |
789 | } |
790 | |
791 | #define IRQ_MSK(n) (u32)((n) < 32 ? ((1 << (n)) - 1) : UINT_MAX) |
792 | |
793 | #ifdef CONFIG_SMP |
794 | static inline void irq_gc_lock(struct irq_chip_generic *gc) |
795 | { |
796 | raw_spin_lock(&gc->lock); |
797 | } |
798 | |
799 | static inline void irq_gc_unlock(struct irq_chip_generic *gc) |
800 | { |
801 | raw_spin_unlock(&gc->lock); |
802 | } |
803 | #else |
804 | static inline void irq_gc_lock(struct irq_chip_generic *gc) { } |
805 | static inline void irq_gc_unlock(struct irq_chip_generic *gc) { } |
806 | #endif |
807 | |
808 | #endif /* _LINUX_IRQ_H */ |
809 |
Branches:
ben-wpan
ben-wpan-stefan
javiroman/ks7010
jz-2.6.34
jz-2.6.34-rc5
jz-2.6.34-rc6
jz-2.6.34-rc7
jz-2.6.35
jz-2.6.36
jz-2.6.37
jz-2.6.38
jz-2.6.39
jz-3.0
jz-3.1
jz-3.11
jz-3.12
jz-3.13
jz-3.15
jz-3.16
jz-3.18-dt
jz-3.2
jz-3.3
jz-3.4
jz-3.5
jz-3.6
jz-3.6-rc2-pwm
jz-3.9
jz-3.9-clk
jz-3.9-rc8
jz47xx
jz47xx-2.6.38
master
Tags:
od-2011-09-04
od-2011-09-18
v2.6.34-rc5
v2.6.34-rc6
v2.6.34-rc7
v3.9