Root/include/sound/emu10k1.h

1/*
2 * Copyright (c) by Jaroslav Kysela <perex@perex.cz>,
3 * Creative Labs, Inc.
4 * Definitions for EMU10K1 (SB Live!) chips
5 *
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 *
21 */
22#ifndef __SOUND_EMU10K1_H
23#define __SOUND_EMU10K1_H
24
25
26#include <sound/pcm.h>
27#include <sound/rawmidi.h>
28#include <sound/hwdep.h>
29#include <sound/ac97_codec.h>
30#include <sound/util_mem.h>
31#include <sound/pcm-indirect.h>
32#include <sound/timer.h>
33#include <linux/interrupt.h>
34#include <linux/mutex.h>
35#include <linux/firmware.h>
36
37#include <asm/io.h>
38#include <uapi/sound/emu10k1.h>
39
40/* ------------------- DEFINES -------------------- */
41
42#define EMUPAGESIZE 4096
43#define MAXREQVOICES 8
44#define MAXPAGES 8192
45#define RESERVED 0
46#define NUM_MIDI 16
47#define NUM_G 64 /* use all channels */
48#define NUM_FXSENDS 4
49#define NUM_EFX_PLAYBACK 16
50
51/* FIXME? - according to the OSS driver the EMU10K1 needs a 29 bit DMA mask */
52#define EMU10K1_DMA_MASK 0x7fffffffUL /* 31bit */
53#define AUDIGY_DMA_MASK 0x7fffffffUL /* 31bit FIXME - 32 should work? */
54                        /* See ALSA bug #1276 - rlrevell */
55
56#define TMEMSIZE 256*1024
57#define TMEMSIZEREG 4
58
59#define IP_TO_CP(ip) ((ip == 0) ? 0 : (((0x00001000uL | (ip & 0x00000FFFL)) << (((ip >> 12) & 0x000FL) + 4)) & 0xFFFF0000uL))
60
61// Audigy specify registers are prefixed with 'A_'
62
63/************************************************************************************************/
64/* PCI function 0 registers, address = <val> + PCIBASE0 */
65/************************************************************************************************/
66
67#define PTR 0x00 /* Indexed register set pointer register */
68                        /* NOTE: The CHANNELNUM and ADDRESS words can */
69                        /* be modified independently of each other. */
70#define PTR_CHANNELNUM_MASK 0x0000003f /* For each per-channel register, indicates the */
71                        /* channel number of the register to be */
72                        /* accessed. For non per-channel registers the */
73                        /* value should be set to zero. */
74#define PTR_ADDRESS_MASK 0x07ff0000 /* Register index */
75#define A_PTR_ADDRESS_MASK 0x0fff0000
76
77#define DATA 0x04 /* Indexed register set data register */
78
79#define IPR 0x08 /* Global interrupt pending register */
80                        /* Clear pending interrupts by writing a 1 to */
81                        /* the relevant bits and zero to the other bits */
82#define IPR_P16V 0x80000000 /* Bit set when the CA0151 P16V chip wishes
83                           to interrupt */
84#define IPR_GPIOMSG 0x20000000 /* GPIO message interrupt (RE'd, still not sure
85                           which INTE bits enable it) */
86
87/* The next two interrupts are for the midi port on the Audigy Drive (A_MPU1) */
88#define IPR_A_MIDITRANSBUFEMPTY2 0x10000000 /* MIDI UART transmit buffer empty */
89#define IPR_A_MIDIRECVBUFEMPTY2 0x08000000 /* MIDI UART receive buffer empty */
90
91#define IPR_SPDIFBUFFULL 0x04000000 /* SPDIF capture related, 10k2 only? (RE) */
92#define IPR_SPDIFBUFHALFFULL 0x02000000 /* SPDIF capture related? (RE) */
93
94#define IPR_SAMPLERATETRACKER 0x01000000 /* Sample rate tracker lock status change */
95#define IPR_FXDSP 0x00800000 /* Enable FX DSP interrupts */
96#define IPR_FORCEINT 0x00400000 /* Force Sound Blaster interrupt */
97#define IPR_PCIERROR 0x00200000 /* PCI bus error */
98#define IPR_VOLINCR 0x00100000 /* Volume increment button pressed */
99#define IPR_VOLDECR 0x00080000 /* Volume decrement button pressed */
100#define IPR_MUTE 0x00040000 /* Mute button pressed */
101#define IPR_MICBUFFULL 0x00020000 /* Microphone buffer full */
102#define IPR_MICBUFHALFFULL 0x00010000 /* Microphone buffer half full */
103#define IPR_ADCBUFFULL 0x00008000 /* ADC buffer full */
104#define IPR_ADCBUFHALFFULL 0x00004000 /* ADC buffer half full */
105#define IPR_EFXBUFFULL 0x00002000 /* Effects buffer full */
106#define IPR_EFXBUFHALFFULL 0x00001000 /* Effects buffer half full */
107#define IPR_GPSPDIFSTATUSCHANGE 0x00000800 /* GPSPDIF channel status change */
108#define IPR_CDROMSTATUSCHANGE 0x00000400 /* CD-ROM channel status change */
109#define IPR_INTERVALTIMER 0x00000200 /* Interval timer terminal count */
110#define IPR_MIDITRANSBUFEMPTY 0x00000100 /* MIDI UART transmit buffer empty */
111#define IPR_MIDIRECVBUFEMPTY 0x00000080 /* MIDI UART receive buffer empty */
112#define IPR_CHANNELLOOP 0x00000040 /* Channel (half) loop interrupt(s) pending */
113#define IPR_CHANNELNUMBERMASK 0x0000003f /* When IPR_CHANNELLOOP is set, indicates the */
114                        /* highest set channel in CLIPL, CLIPH, HLIPL, */
115                        /* or HLIPH. When IP is written with CL set, */
116                        /* the bit in H/CLIPL or H/CLIPH corresponding */
117                        /* to the CIN value written will be cleared. */
118
119#define INTE 0x0c /* Interrupt enable register */
120#define INTE_VIRTUALSB_MASK 0xc0000000 /* Virtual Soundblaster I/O port capture */
121#define INTE_VIRTUALSB_220 0x00000000 /* Capture at I/O base address 0x220-0x22f */
122#define INTE_VIRTUALSB_240 0x40000000 /* Capture at I/O base address 0x240 */
123#define INTE_VIRTUALSB_260 0x80000000 /* Capture at I/O base address 0x260 */
124#define INTE_VIRTUALSB_280 0xc0000000 /* Capture at I/O base address 0x280 */
125#define INTE_VIRTUALMPU_MASK 0x30000000 /* Virtual MPU I/O port capture */
126#define INTE_VIRTUALMPU_300 0x00000000 /* Capture at I/O base address 0x300-0x301 */
127#define INTE_VIRTUALMPU_310 0x10000000 /* Capture at I/O base address 0x310 */
128#define INTE_VIRTUALMPU_320 0x20000000 /* Capture at I/O base address 0x320 */
129#define INTE_VIRTUALMPU_330 0x30000000 /* Capture at I/O base address 0x330 */
130#define INTE_MASTERDMAENABLE 0x08000000 /* Master DMA emulation at 0x000-0x00f */
131#define INTE_SLAVEDMAENABLE 0x04000000 /* Slave DMA emulation at 0x0c0-0x0df */
132#define INTE_MASTERPICENABLE 0x02000000 /* Master PIC emulation at 0x020-0x021 */
133#define INTE_SLAVEPICENABLE 0x01000000 /* Slave PIC emulation at 0x0a0-0x0a1 */
134#define INTE_VSBENABLE 0x00800000 /* Enable virtual Soundblaster */
135#define INTE_ADLIBENABLE 0x00400000 /* Enable AdLib emulation at 0x388-0x38b */
136#define INTE_MPUENABLE 0x00200000 /* Enable virtual MPU */
137#define INTE_FORCEINT 0x00100000 /* Continuously assert INTAN */
138
139#define INTE_MRHANDENABLE 0x00080000 /* Enable the "Mr. Hand" logic */
140                        /* NOTE: There is no reason to use this under */
141                        /* Linux, and it will cause odd hardware */
142                        /* behavior and possibly random segfaults and */
143                        /* lockups if enabled. */
144
145/* The next two interrupts are for the midi port on the Audigy Drive (A_MPU1) */
146#define INTE_A_MIDITXENABLE2 0x00020000 /* Enable MIDI transmit-buffer-empty interrupts */
147#define INTE_A_MIDIRXENABLE2 0x00010000 /* Enable MIDI receive-buffer-empty interrupts */
148
149
150#define INTE_SAMPLERATETRACKER 0x00002000 /* Enable sample rate tracker interrupts */
151                        /* NOTE: This bit must always be enabled */
152#define INTE_FXDSPENABLE 0x00001000 /* Enable FX DSP interrupts */
153#define INTE_PCIERRORENABLE 0x00000800 /* Enable PCI bus error interrupts */
154#define INTE_VOLINCRENABLE 0x00000400 /* Enable volume increment button interrupts */
155#define INTE_VOLDECRENABLE 0x00000200 /* Enable volume decrement button interrupts */
156#define INTE_MUTEENABLE 0x00000100 /* Enable mute button interrupts */
157#define INTE_MICBUFENABLE 0x00000080 /* Enable microphone buffer interrupts */
158#define INTE_ADCBUFENABLE 0x00000040 /* Enable ADC buffer interrupts */
159#define INTE_EFXBUFENABLE 0x00000020 /* Enable Effects buffer interrupts */
160#define INTE_GPSPDIFENABLE 0x00000010 /* Enable GPSPDIF status interrupts */
161#define INTE_CDSPDIFENABLE 0x00000008 /* Enable CDSPDIF status interrupts */
162#define INTE_INTERVALTIMERENB 0x00000004 /* Enable interval timer interrupts */
163#define INTE_MIDITXENABLE 0x00000002 /* Enable MIDI transmit-buffer-empty interrupts */
164#define INTE_MIDIRXENABLE 0x00000001 /* Enable MIDI receive-buffer-empty interrupts */
165
166#define WC 0x10 /* Wall Clock register */
167#define WC_SAMPLECOUNTER_MASK 0x03FFFFC0 /* Sample periods elapsed since reset */
168#define WC_SAMPLECOUNTER 0x14060010
169#define WC_CURRENTCHANNEL 0x0000003F /* Channel [0..63] currently being serviced */
170                        /* NOTE: Each channel takes 1/64th of a sample */
171                        /* period to be serviced. */
172
173#define HCFG 0x14 /* Hardware config register */
174                        /* NOTE: There is no reason to use the legacy */
175                        /* SoundBlaster emulation stuff described below */
176                        /* under Linux, and all kinds of weird hardware */
177                        /* behavior can result if you try. Don't. */
178#define HCFG_LEGACYFUNC_MASK 0xe0000000 /* Legacy function number */
179#define HCFG_LEGACYFUNC_MPU 0x00000000 /* Legacy MPU */
180#define HCFG_LEGACYFUNC_SB 0x40000000 /* Legacy SB */
181#define HCFG_LEGACYFUNC_AD 0x60000000 /* Legacy AD */
182#define HCFG_LEGACYFUNC_MPIC 0x80000000 /* Legacy MPIC */
183#define HCFG_LEGACYFUNC_MDMA 0xa0000000 /* Legacy MDMA */
184#define HCFG_LEGACYFUNC_SPCI 0xc0000000 /* Legacy SPCI */
185#define HCFG_LEGACYFUNC_SDMA 0xe0000000 /* Legacy SDMA */
186#define HCFG_IOCAPTUREADDR 0x1f000000 /* The 4 LSBs of the captured I/O address. */
187#define HCFG_LEGACYWRITE 0x00800000 /* 1 = write, 0 = read */
188#define HCFG_LEGACYWORD 0x00400000 /* 1 = word, 0 = byte */
189#define HCFG_LEGACYINT 0x00200000 /* 1 = legacy event captured. Write 1 to clear. */
190                        /* NOTE: The rest of the bits in this register */
191                        /* _are_ relevant under Linux. */
192#define HCFG_PUSH_BUTTON_ENABLE 0x00100000 /* Enables Volume Inc/Dec and Mute functions */
193#define HCFG_BAUD_RATE 0x00080000 /* 0 = 48kHz, 1 = 44.1kHz */
194#define HCFG_EXPANDED_MEM 0x00040000 /* 1 = any 16M of 4G addr, 0 = 32M of 2G addr */
195#define HCFG_CODECFORMAT_MASK 0x00030000 /* CODEC format */
196
197/* Specific to Alice2, CA0102 */
198#define HCFG_CODECFORMAT_AC97_1 0x00000000 /* AC97 CODEC format -- Ver 1.03 */
199#define HCFG_CODECFORMAT_AC97_2 0x00010000 /* AC97 CODEC format -- Ver 2.1 */
200#define HCFG_AUTOMUTE_ASYNC 0x00008000 /* When set, the async sample rate convertors */
201                        /* will automatically mute their output when */
202                        /* they are not rate-locked to the external */
203                        /* async audio source */
204#define HCFG_AUTOMUTE_SPDIF 0x00004000 /* When set, the async sample rate convertors */
205                        /* will automatically mute their output when */
206                        /* the SPDIF V-bit indicates invalid audio */
207#define HCFG_EMU32_SLAVE 0x00002000 /* 0 = Master, 1 = Slave. Slave for EMU1010 */
208#define HCFG_SLOW_RAMP 0x00001000 /* Increases Send Smoothing time constant */
209/* 0x00000800 not used on Alice2 */
210#define HCFG_PHASE_TRACK_MASK 0x00000700 /* When set, forces corresponding input to */
211                        /* phase track the previous input. */
212                        /* I2S0 can phase track the last S/PDIF input */
213#define HCFG_I2S_ASRC_ENABLE 0x00000070 /* When set, enables asynchronous sample rate */
214                        /* conversion for the corresponding */
215                         /* I2S format input */
216/* Rest of HCFG 0x0000000f same as below. LOCKSOUNDCACHE etc. */
217
218
219
220/* Older chips */
221#define HCFG_CODECFORMAT_AC97 0x00000000 /* AC97 CODEC format -- Primary Output */
222#define HCFG_CODECFORMAT_I2S 0x00010000 /* I2S CODEC format -- Secondary (Rear) Output */
223#define HCFG_GPINPUT0 0x00004000 /* External pin112 */
224#define HCFG_GPINPUT1 0x00002000 /* External pin110 */
225#define HCFG_GPOUTPUT_MASK 0x00001c00 /* External pins which may be controlled */
226#define HCFG_GPOUT0 0x00001000 /* External pin? (spdif enable on 5.1) */
227#define HCFG_GPOUT1 0x00000800 /* External pin? (IR) */
228#define HCFG_GPOUT2 0x00000400 /* External pin? (IR) */
229#define HCFG_JOYENABLE 0x00000200 /* Internal joystick enable */
230#define HCFG_PHASETRACKENABLE 0x00000100 /* Phase tracking enable */
231                        /* 1 = Force all 3 async digital inputs to use */
232                        /* the same async sample rate tracker (ZVIDEO) */
233#define HCFG_AC3ENABLE_MASK 0x000000e0 /* AC3 async input control - Not implemented */
234#define HCFG_AC3ENABLE_ZVIDEO 0x00000080 /* Channels 0 and 1 replace ZVIDEO */
235#define HCFG_AC3ENABLE_CDSPDIF 0x00000040 /* Channels 0 and 1 replace CDSPDIF */
236#define HCFG_AC3ENABLE_GPSPDIF 0x00000020 /* Channels 0 and 1 replace GPSPDIF */
237#define HCFG_AUTOMUTE 0x00000010 /* When set, the async sample rate convertors */
238                        /* will automatically mute their output when */
239                        /* they are not rate-locked to the external */
240                        /* async audio source */
241#define HCFG_LOCKSOUNDCACHE 0x00000008 /* 1 = Cancel bustmaster accesses to soundcache */
242                        /* NOTE: This should generally never be used. */
243#define HCFG_LOCKTANKCACHE_MASK 0x00000004 /* 1 = Cancel bustmaster accesses to tankcache */
244                        /* NOTE: This should generally never be used. */
245#define HCFG_LOCKTANKCACHE 0x01020014
246#define HCFG_MUTEBUTTONENABLE 0x00000002 /* 1 = Master mute button sets AUDIOENABLE = 0. */
247                        /* NOTE: This is a 'cheap' way to implement a */
248                        /* master mute function on the mute button, and */
249                        /* in general should not be used unless a more */
250                        /* sophisticated master mute function has not */
251                        /* been written. */
252#define HCFG_AUDIOENABLE 0x00000001 /* 0 = CODECs transmit zero-valued samples */
253                        /* Should be set to 1 when the EMU10K1 is */
254                        /* completely initialized. */
255
256//For Audigy, MPU port move to 0x70-0x74 ptr register
257
258#define MUDATA 0x18 /* MPU401 data register (8 bits) */
259
260#define MUCMD 0x19 /* MPU401 command register (8 bits) */
261#define MUCMD_RESET 0xff /* RESET command */
262#define MUCMD_ENTERUARTMODE 0x3f /* Enter_UART_mode command */
263                        /* NOTE: All other commands are ignored */
264
265#define MUSTAT MUCMD /* MPU401 status register (8 bits) */
266#define MUSTAT_IRDYN 0x80 /* 0 = MIDI data or command ACK */
267#define MUSTAT_ORDYN 0x40 /* 0 = MUDATA can accept a command or data */
268
269#define A_IOCFG 0x18 /* GPIO on Audigy card (16bits) */
270#define A_GPINPUT_MASK 0xff00
271#define A_GPOUTPUT_MASK 0x00ff
272
273// Audigy output/GPIO stuff taken from the kX drivers
274#define A_IOCFG_GPOUT0 0x0044 /* analog/digital */
275#define A_IOCFG_DISABLE_ANALOG 0x0040 /* = 'enable' for Audigy2 (chiprev=4) */
276#define A_IOCFG_ENABLE_DIGITAL 0x0004
277#define A_IOCFG_ENABLE_DIGITAL_AUDIGY4 0x0080
278#define A_IOCFG_UNKNOWN_20 0x0020
279#define A_IOCFG_DISABLE_AC97_FRONT 0x0080 /* turn off ac97 front -> front (10k2.1) */
280#define A_IOCFG_GPOUT1 0x0002 /* IR? drive's internal bypass (?) */
281#define A_IOCFG_GPOUT2 0x0001 /* IR */
282#define A_IOCFG_MULTIPURPOSE_JACK 0x2000 /* center+lfe+rear_center (a2/a2ex) */
283                                                /* + digital for generic 10k2 */
284#define A_IOCFG_DIGITAL_JACK 0x1000 /* digital for a2 platinum */
285#define A_IOCFG_FRONT_JACK 0x4000
286#define A_IOCFG_REAR_JACK 0x8000
287#define A_IOCFG_PHONES_JACK 0x0100 /* LiveDrive */
288
289/* outputs:
290 * for audigy2 platinum: 0xa00
291 * for a2 platinum ex: 0x1c00
292 * for a1 platinum: 0x0
293 */
294
295#define TIMER 0x1a /* Timer terminal count register */
296                        /* NOTE: After the rate is changed, a maximum */
297                        /* of 1024 sample periods should be allowed */
298                        /* before the new rate is guaranteed accurate. */
299#define TIMER_RATE_MASK 0x000003ff /* Timer interrupt rate in sample periods */
300                        /* 0 == 1024 periods, [1..4] are not useful */
301#define TIMER_RATE 0x0a00001a
302
303#define AC97DATA 0x1c /* AC97 register set data register (16 bit) */
304
305#define AC97ADDRESS 0x1e /* AC97 register set address register (8 bit) */
306#define AC97ADDRESS_READY 0x80 /* Read-only bit, reflects CODEC READY signal */
307#define AC97ADDRESS_ADDRESS 0x7f /* Address of indexed AC97 register */
308
309/* Available on the Audigy 2 and Audigy 4 only. This is the P16V chip. */
310#define PTR2 0x20 /* Indexed register set pointer register */
311#define DATA2 0x24 /* Indexed register set data register */
312#define IPR2 0x28 /* P16V interrupt pending register */
313#define IPR2_PLAYBACK_CH_0_LOOP 0x00001000 /* Playback Channel 0 loop */
314#define IPR2_PLAYBACK_CH_0_HALF_LOOP 0x00000100 /* Playback Channel 0 half loop */
315#define IPR2_CAPTURE_CH_0_LOOP 0x00100000 /* Capture Channel 0 loop */
316#define IPR2_CAPTURE_CH_0_HALF_LOOP 0x00010000 /* Capture Channel 0 half loop */
317                        /* 0x00000100 Playback. Only in once per period.
318                         * 0x00110000 Capture. Int on half buffer.
319                         */
320#define INTE2 0x2c /* P16V Interrupt enable register. */
321#define INTE2_PLAYBACK_CH_0_LOOP 0x00001000 /* Playback Channel 0 loop */
322#define INTE2_PLAYBACK_CH_0_HALF_LOOP 0x00000100 /* Playback Channel 0 half loop */
323#define INTE2_PLAYBACK_CH_1_LOOP 0x00002000 /* Playback Channel 1 loop */
324#define INTE2_PLAYBACK_CH_1_HALF_LOOP 0x00000200 /* Playback Channel 1 half loop */
325#define INTE2_PLAYBACK_CH_2_LOOP 0x00004000 /* Playback Channel 2 loop */
326#define INTE2_PLAYBACK_CH_2_HALF_LOOP 0x00000400 /* Playback Channel 2 half loop */
327#define INTE2_PLAYBACK_CH_3_LOOP 0x00008000 /* Playback Channel 3 loop */
328#define INTE2_PLAYBACK_CH_3_HALF_LOOP 0x00000800 /* Playback Channel 3 half loop */
329#define INTE2_CAPTURE_CH_0_LOOP 0x00100000 /* Capture Channel 0 loop */
330#define INTE2_CAPTURE_CH_0_HALF_LOOP 0x00010000 /* Caputre Channel 0 half loop */
331#define HCFG2 0x34 /* Defaults: 0, win2000 sets it to 00004201 */
332                        /* 0x00000000 2-channel output. */
333                        /* 0x00000200 8-channel output. */
334                        /* 0x00000004 pauses stream/irq fail. */
335                        /* Rest of bits no nothing to sound output */
336                        /* bit 0: Enable P16V audio.
337                         * bit 1: Lock P16V record memory cache.
338                         * bit 2: Lock P16V playback memory cache.
339                         * bit 3: Dummy record insert zero samples.
340                         * bit 8: Record 8-channel in phase.
341                         * bit 9: Playback 8-channel in phase.
342                         * bit 11-12: Playback mixer attenuation: 0=0dB, 1=-6dB, 2=-12dB, 3=Mute.
343                         * bit 13: Playback mixer enable.
344                         * bit 14: Route SRC48 mixer output to fx engine.
345                         * bit 15: Enable IEEE 1394 chip.
346                         */
347#define IPR3 0x38 /* Cdif interrupt pending register */
348#define INTE3 0x3c /* Cdif interrupt enable register. */
349/************************************************************************************************/
350/* PCI function 1 registers, address = <val> + PCIBASE1 */
351/************************************************************************************************/
352
353#define JOYSTICK1 0x00 /* Analog joystick port register */
354#define JOYSTICK2 0x01 /* Analog joystick port register */
355#define JOYSTICK3 0x02 /* Analog joystick port register */
356#define JOYSTICK4 0x03 /* Analog joystick port register */
357#define JOYSTICK5 0x04 /* Analog joystick port register */
358#define JOYSTICK6 0x05 /* Analog joystick port register */
359#define JOYSTICK7 0x06 /* Analog joystick port register */
360#define JOYSTICK8 0x07 /* Analog joystick port register */
361
362/* When writing, any write causes JOYSTICK_COMPARATOR output enable to be pulsed on write. */
363/* When reading, use these bitfields: */
364#define JOYSTICK_BUTTONS 0x0f /* Joystick button data */
365#define JOYSTICK_COMPARATOR 0xf0 /* Joystick comparator data */
366
367
368/********************************************************************************************************/
369/* Emu10k1 pointer-offset register set, accessed through the PTR and DATA registers */
370/********************************************************************************************************/
371
372#define CPF 0x00 /* Current pitch and fraction register */
373#define CPF_CURRENTPITCH_MASK 0xffff0000 /* Current pitch (linear, 0x4000 == unity pitch shift) */
374#define CPF_CURRENTPITCH 0x10100000
375#define CPF_STEREO_MASK 0x00008000 /* 1 = Even channel interleave, odd channel locked */
376#define CPF_STOP_MASK 0x00004000 /* 1 = Current pitch forced to 0 */
377#define CPF_FRACADDRESS_MASK 0x00003fff /* Linear fractional address of the current channel */
378
379#define PTRX 0x01 /* Pitch target and send A/B amounts register */
380#define PTRX_PITCHTARGET_MASK 0xffff0000 /* Pitch target of specified channel */
381#define PTRX_PITCHTARGET 0x10100001
382#define PTRX_FXSENDAMOUNT_A_MASK 0x0000ff00 /* Linear level of channel output sent to FX send bus A */
383#define PTRX_FXSENDAMOUNT_A 0x08080001
384#define PTRX_FXSENDAMOUNT_B_MASK 0x000000ff /* Linear level of channel output sent to FX send bus B */
385#define PTRX_FXSENDAMOUNT_B 0x08000001
386
387#define CVCF 0x02 /* Current volume and filter cutoff register */
388#define CVCF_CURRENTVOL_MASK 0xffff0000 /* Current linear volume of specified channel */
389#define CVCF_CURRENTVOL 0x10100002
390#define CVCF_CURRENTFILTER_MASK 0x0000ffff /* Current filter cutoff frequency of specified channel */
391#define CVCF_CURRENTFILTER 0x10000002
392
393#define VTFT 0x03 /* Volume target and filter cutoff target register */
394#define VTFT_VOLUMETARGET_MASK 0xffff0000 /* Volume target of specified channel */
395#define VTFT_VOLUMETARGET 0x10100003
396#define VTFT_FILTERTARGET_MASK 0x0000ffff /* Filter cutoff target of specified channel */
397#define VTFT_FILTERTARGET 0x10000003
398
399#define Z1 0x05 /* Filter delay memory 1 register */
400
401#define Z2 0x04 /* Filter delay memory 2 register */
402
403#define PSST 0x06 /* Send C amount and loop start address register */
404#define PSST_FXSENDAMOUNT_C_MASK 0xff000000 /* Linear level of channel output sent to FX send bus C */
405
406#define PSST_FXSENDAMOUNT_C 0x08180006
407
408#define PSST_LOOPSTARTADDR_MASK 0x00ffffff /* Loop start address of the specified channel */
409#define PSST_LOOPSTARTADDR 0x18000006
410
411#define DSL 0x07 /* Send D amount and loop start address register */
412#define DSL_FXSENDAMOUNT_D_MASK 0xff000000 /* Linear level of channel output sent to FX send bus D */
413
414#define DSL_FXSENDAMOUNT_D 0x08180007
415
416#define DSL_LOOPENDADDR_MASK 0x00ffffff /* Loop end address of the specified channel */
417#define DSL_LOOPENDADDR 0x18000007
418
419#define CCCA 0x08 /* Filter Q, interp. ROM, byte size, cur. addr register */
420#define CCCA_RESONANCE 0xf0000000 /* Lowpass filter resonance (Q) height */
421#define CCCA_INTERPROMMASK 0x0e000000 /* Selects passband of interpolation ROM */
422                        /* 1 == full band, 7 == lowpass */
423                        /* ROM 0 is used when pitch shifting downward or less */
424                        /* then 3 semitones upward. Increasingly higher ROM */
425                        /* numbers are used, typically in steps of 3 semitones, */
426                        /* as upward pitch shifting is performed. */
427#define CCCA_INTERPROM_0 0x00000000 /* Select interpolation ROM 0 */
428#define CCCA_INTERPROM_1 0x02000000 /* Select interpolation ROM 1 */
429#define CCCA_INTERPROM_2 0x04000000 /* Select interpolation ROM 2 */
430#define CCCA_INTERPROM_3 0x06000000 /* Select interpolation ROM 3 */
431#define CCCA_INTERPROM_4 0x08000000 /* Select interpolation ROM 4 */
432#define CCCA_INTERPROM_5 0x0a000000 /* Select interpolation ROM 5 */
433#define CCCA_INTERPROM_6 0x0c000000 /* Select interpolation ROM 6 */
434#define CCCA_INTERPROM_7 0x0e000000 /* Select interpolation ROM 7 */
435#define CCCA_8BITSELECT 0x01000000 /* 1 = Sound memory for this channel uses 8-bit samples */
436#define CCCA_CURRADDR_MASK 0x00ffffff /* Current address of the selected channel */
437#define CCCA_CURRADDR 0x18000008
438
439/* undefine CCR to avoid conflict with the definition for SH */
440#undef CCR
441#define CCR 0x09 /* Cache control register */
442#define CCR_CACHEINVALIDSIZE 0x07190009
443#define CCR_CACHEINVALIDSIZE_MASK 0xfe000000 /* Number of invalid samples cache for this channel */
444#define CCR_CACHELOOPFLAG 0x01000000 /* 1 = Cache has a loop service pending */
445#define CCR_INTERLEAVEDSAMPLES 0x00800000 /* 1 = A cache service will fetch interleaved samples */
446#define CCR_WORDSIZEDSAMPLES 0x00400000 /* 1 = A cache service will fetch word sized samples */
447#define CCR_READADDRESS 0x06100009
448#define CCR_READADDRESS_MASK 0x003f0000 /* Location of cache just beyond current cache service */
449#define CCR_LOOPINVALSIZE 0x0000fe00 /* Number of invalid samples in cache prior to loop */
450                        /* NOTE: This is valid only if CACHELOOPFLAG is set */
451#define CCR_LOOPFLAG 0x00000100 /* Set for a single sample period when a loop occurs */
452#define CCR_CACHELOOPADDRHI 0x000000ff /* DSL_LOOPSTARTADDR's hi byte if CACHELOOPFLAG is set */
453
454#define CLP 0x0a /* Cache loop register (valid if CCR_CACHELOOPFLAG = 1) */
455                        /* NOTE: This register is normally not used */
456#define CLP_CACHELOOPADDR 0x0000ffff /* Cache loop address (DSL_LOOPSTARTADDR [0..15]) */
457
458#define FXRT 0x0b /* Effects send routing register */
459                        /* NOTE: It is illegal to assign the same routing to */
460                        /* two effects sends. */
461#define FXRT_CHANNELA 0x000f0000 /* Effects send bus number for channel's effects send A */
462#define FXRT_CHANNELB 0x00f00000 /* Effects send bus number for channel's effects send B */
463#define FXRT_CHANNELC 0x0f000000 /* Effects send bus number for channel's effects send C */
464#define FXRT_CHANNELD 0xf0000000 /* Effects send bus number for channel's effects send D */
465
466#define A_HR 0x0b /* High Resolution. 24bit playback from host to DSP. */
467#define MAPA 0x0c /* Cache map A */
468
469#define MAPB 0x0d /* Cache map B */
470
471#define MAP_PTE_MASK 0xffffe000 /* The 19 MSBs of the PTE indexed by the PTI */
472#define MAP_PTI_MASK 0x00001fff /* The 13 bit index to one of the 8192 PTE dwords */
473
474/* 0x0e, 0x0f: Not used */
475
476#define ENVVOL 0x10 /* Volume envelope register */
477#define ENVVOL_MASK 0x0000ffff /* Current value of volume envelope state variable */
478                        /* 0x8000-n == 666*n usec delay */
479
480#define ATKHLDV 0x11 /* Volume envelope hold and attack register */
481#define ATKHLDV_PHASE0 0x00008000 /* 0 = Begin attack phase */
482#define ATKHLDV_HOLDTIME_MASK 0x00007f00 /* Envelope hold time (127-n == n*88.2msec) */
483#define ATKHLDV_ATTACKTIME_MASK 0x0000007f /* Envelope attack time, log encoded */
484                        /* 0 = infinite, 1 = 10.9msec, ... 0x7f = 5.5msec */
485
486#define DCYSUSV 0x12 /* Volume envelope sustain and decay register */
487#define DCYSUSV_PHASE1_MASK 0x00008000 /* 0 = Begin attack phase, 1 = begin release phase */
488#define DCYSUSV_SUSTAINLEVEL_MASK 0x00007f00 /* 127 = full, 0 = off, 0.75dB increments */
489#define DCYSUSV_CHANNELENABLE_MASK 0x00000080 /* 1 = Inhibit envelope engine from writing values in */
490                        /* this channel and from writing to pitch, filter and */
491                        /* volume targets. */
492#define DCYSUSV_DECAYTIME_MASK 0x0000007f /* Volume envelope decay time, log encoded */
493                        /* 0 = 43.7msec, 1 = 21.8msec, 0x7f = 22msec */
494
495#define LFOVAL1 0x13 /* Modulation LFO value */
496#define LFOVAL_MASK 0x0000ffff /* Current value of modulation LFO state variable */
497                        /* 0x8000-n == 666*n usec delay */
498
499#define ENVVAL 0x14 /* Modulation envelope register */
500#define ENVVAL_MASK 0x0000ffff /* Current value of modulation envelope state variable */
501                        /* 0x8000-n == 666*n usec delay */
502
503#define ATKHLDM 0x15 /* Modulation envelope hold and attack register */
504#define ATKHLDM_PHASE0 0x00008000 /* 0 = Begin attack phase */
505#define ATKHLDM_HOLDTIME 0x00007f00 /* Envelope hold time (127-n == n*42msec) */
506#define ATKHLDM_ATTACKTIME 0x0000007f /* Envelope attack time, log encoded */
507                        /* 0 = infinite, 1 = 11msec, ... 0x7f = 5.5msec */
508
509#define DCYSUSM 0x16 /* Modulation envelope decay and sustain register */
510#define DCYSUSM_PHASE1_MASK 0x00008000 /* 0 = Begin attack phase, 1 = begin release phase */
511#define DCYSUSM_SUSTAINLEVEL_MASK 0x00007f00 /* 127 = full, 0 = off, 0.75dB increments */
512#define DCYSUSM_DECAYTIME_MASK 0x0000007f /* Envelope decay time, log encoded */
513                        /* 0 = 43.7msec, 1 = 21.8msec, 0x7f = 22msec */
514
515#define LFOVAL2 0x17 /* Vibrato LFO register */
516#define LFOVAL2_MASK 0x0000ffff /* Current value of vibrato LFO state variable */
517                        /* 0x8000-n == 666*n usec delay */
518
519#define IP 0x18 /* Initial pitch register */
520#define IP_MASK 0x0000ffff /* Exponential initial pitch shift */
521                        /* 4 bits of octave, 12 bits of fractional octave */
522#define IP_UNITY 0x0000e000 /* Unity pitch shift */
523
524#define IFATN 0x19 /* Initial filter cutoff and attenuation register */
525#define IFATN_FILTERCUTOFF_MASK 0x0000ff00 /* Initial filter cutoff frequency in exponential units */
526                        /* 6 most significant bits are semitones */
527                        /* 2 least significant bits are fractions */
528#define IFATN_FILTERCUTOFF 0x08080019
529#define IFATN_ATTENUATION_MASK 0x000000ff /* Initial attenuation in 0.375dB steps */
530#define IFATN_ATTENUATION 0x08000019
531
532
533#define PEFE 0x1a /* Pitch envelope and filter envelope amount register */
534#define PEFE_PITCHAMOUNT_MASK 0x0000ff00 /* Pitch envlope amount */
535                        /* Signed 2's complement, +/- one octave peak extremes */
536#define PEFE_PITCHAMOUNT 0x0808001a
537#define PEFE_FILTERAMOUNT_MASK 0x000000ff /* Filter envlope amount */
538                        /* Signed 2's complement, +/- six octaves peak extremes */
539#define PEFE_FILTERAMOUNT 0x0800001a
540#define FMMOD 0x1b /* Vibrato/filter modulation from LFO register */
541#define FMMOD_MODVIBRATO 0x0000ff00 /* Vibrato LFO modulation depth */
542                        /* Signed 2's complement, +/- one octave extremes */
543#define FMMOD_MOFILTER 0x000000ff /* Filter LFO modulation depth */
544                        /* Signed 2's complement, +/- three octave extremes */
545
546
547#define TREMFRQ 0x1c /* Tremolo amount and modulation LFO frequency register */
548#define TREMFRQ_DEPTH 0x0000ff00 /* Tremolo depth */
549                        /* Signed 2's complement, with +/- 12dB extremes */
550
551#define TREMFRQ_FREQUENCY 0x000000ff /* Tremolo LFO frequency */
552                        /* ??Hz steps, maximum of ?? Hz. */
553#define FM2FRQ2 0x1d /* Vibrato amount and vibrato LFO frequency register */
554#define FM2FRQ2_DEPTH 0x0000ff00 /* Vibrato LFO vibrato depth */
555                        /* Signed 2's complement, +/- one octave extremes */
556#define FM2FRQ2_FREQUENCY 0x000000ff /* Vibrato LFO frequency */
557                        /* 0.039Hz steps, maximum of 9.85 Hz. */
558
559#define TEMPENV 0x1e /* Tempory envelope register */
560#define TEMPENV_MASK 0x0000ffff /* 16-bit value */
561                        /* NOTE: All channels contain internal variables; do */
562                        /* not write to these locations. */
563
564/* 0x1f: not used */
565
566#define CD0 0x20 /* Cache data 0 register */
567#define CD1 0x21 /* Cache data 1 register */
568#define CD2 0x22 /* Cache data 2 register */
569#define CD3 0x23 /* Cache data 3 register */
570#define CD4 0x24 /* Cache data 4 register */
571#define CD5 0x25 /* Cache data 5 register */
572#define CD6 0x26 /* Cache data 6 register */
573#define CD7 0x27 /* Cache data 7 register */
574#define CD8 0x28 /* Cache data 8 register */
575#define CD9 0x29 /* Cache data 9 register */
576#define CDA 0x2a /* Cache data A register */
577#define CDB 0x2b /* Cache data B register */
578#define CDC 0x2c /* Cache data C register */
579#define CDD 0x2d /* Cache data D register */
580#define CDE 0x2e /* Cache data E register */
581#define CDF 0x2f /* Cache data F register */
582
583/* 0x30-3f seem to be the same as 0x20-2f */
584
585#define PTB 0x40 /* Page table base register */
586#define PTB_MASK 0xfffff000 /* Physical address of the page table in host memory */
587
588#define TCB 0x41 /* Tank cache base register */
589#define TCB_MASK 0xfffff000 /* Physical address of the bottom of host based TRAM */
590
591#define ADCCR 0x42 /* ADC sample rate/stereo control register */
592#define ADCCR_RCHANENABLE 0x00000010 /* Enables right channel for writing to the host */
593#define ADCCR_LCHANENABLE 0x00000008 /* Enables left channel for writing to the host */
594                        /* NOTE: To guarantee phase coherency, both channels */
595                        /* must be disabled prior to enabling both channels. */
596#define A_ADCCR_RCHANENABLE 0x00000020
597#define A_ADCCR_LCHANENABLE 0x00000010
598
599#define A_ADCCR_SAMPLERATE_MASK 0x0000000F /* Audigy sample rate convertor output rate */
600#define ADCCR_SAMPLERATE_MASK 0x00000007 /* Sample rate convertor output rate */
601#define ADCCR_SAMPLERATE_48 0x00000000 /* 48kHz sample rate */
602#define ADCCR_SAMPLERATE_44 0x00000001 /* 44.1kHz sample rate */
603#define ADCCR_SAMPLERATE_32 0x00000002 /* 32kHz sample rate */
604#define ADCCR_SAMPLERATE_24 0x00000003 /* 24kHz sample rate */
605#define ADCCR_SAMPLERATE_22 0x00000004 /* 22.05kHz sample rate */
606#define ADCCR_SAMPLERATE_16 0x00000005 /* 16kHz sample rate */
607#define ADCCR_SAMPLERATE_11 0x00000006 /* 11.025kHz sample rate */
608#define ADCCR_SAMPLERATE_8 0x00000007 /* 8kHz sample rate */
609#define A_ADCCR_SAMPLERATE_12 0x00000006 /* 12kHz sample rate */
610#define A_ADCCR_SAMPLERATE_11 0x00000007 /* 11.025kHz sample rate */
611#define A_ADCCR_SAMPLERATE_8 0x00000008 /* 8kHz sample rate */
612
613#define FXWC 0x43 /* FX output write channels register */
614                        /* When set, each bit enables the writing of the */
615                        /* corresponding FX output channel (internal registers */
616                        /* 0x20-0x3f) to host memory. This mode of recording */
617                        /* is 16bit, 48KHz only. All 32 channels can be enabled */
618                        /* simultaneously. */
619
620#define FXWC_DEFAULTROUTE_C (1<<0) /* left emu out? */
621#define FXWC_DEFAULTROUTE_B (1<<1) /* right emu out? */
622#define FXWC_DEFAULTROUTE_A (1<<12)
623#define FXWC_DEFAULTROUTE_D (1<<13)
624#define FXWC_ADCLEFT (1<<18)
625#define FXWC_CDROMSPDIFLEFT (1<<18)
626#define FXWC_ADCRIGHT (1<<19)
627#define FXWC_CDROMSPDIFRIGHT (1<<19)
628#define FXWC_MIC (1<<20)
629#define FXWC_ZOOMLEFT (1<<20)
630#define FXWC_ZOOMRIGHT (1<<21)
631#define FXWC_SPDIFLEFT (1<<22) /* 0x00400000 */
632#define FXWC_SPDIFRIGHT (1<<23) /* 0x00800000 */
633
634#define A_TBLSZ 0x43 /* Effects Tank Internal Table Size. Only low byte or register used */
635
636#define TCBS 0x44 /* Tank cache buffer size register */
637#define TCBS_MASK 0x00000007 /* Tank cache buffer size field */
638#define TCBS_BUFFSIZE_16K 0x00000000
639#define TCBS_BUFFSIZE_32K 0x00000001
640#define TCBS_BUFFSIZE_64K 0x00000002
641#define TCBS_BUFFSIZE_128K 0x00000003
642#define TCBS_BUFFSIZE_256K 0x00000004
643#define TCBS_BUFFSIZE_512K 0x00000005
644#define TCBS_BUFFSIZE_1024K 0x00000006
645#define TCBS_BUFFSIZE_2048K 0x00000007
646
647#define MICBA 0x45 /* AC97 microphone buffer address register */
648#define MICBA_MASK 0xfffff000 /* 20 bit base address */
649
650#define ADCBA 0x46 /* ADC buffer address register */
651#define ADCBA_MASK 0xfffff000 /* 20 bit base address */
652
653#define FXBA 0x47 /* FX Buffer Address */
654#define FXBA_MASK 0xfffff000 /* 20 bit base address */
655
656#define A_HWM 0x48 /* High PCI Water Mark - word access, defaults to 3f */
657
658#define MICBS 0x49 /* Microphone buffer size register */
659
660#define ADCBS 0x4a /* ADC buffer size register */
661
662#define FXBS 0x4b /* FX buffer size register */
663
664/* register: 0x4c..4f: ffff-ffff current amounts, per-channel */
665
666/* The following mask values define the size of the ADC, MIX and FX buffers in bytes */
667#define ADCBS_BUFSIZE_NONE 0x00000000
668#define ADCBS_BUFSIZE_384 0x00000001
669#define ADCBS_BUFSIZE_448 0x00000002
670#define ADCBS_BUFSIZE_512 0x00000003
671#define ADCBS_BUFSIZE_640 0x00000004
672#define ADCBS_BUFSIZE_768 0x00000005
673#define ADCBS_BUFSIZE_896 0x00000006
674#define ADCBS_BUFSIZE_1024 0x00000007
675#define ADCBS_BUFSIZE_1280 0x00000008
676#define ADCBS_BUFSIZE_1536 0x00000009
677#define ADCBS_BUFSIZE_1792 0x0000000a
678#define ADCBS_BUFSIZE_2048 0x0000000b
679#define ADCBS_BUFSIZE_2560 0x0000000c
680#define ADCBS_BUFSIZE_3072 0x0000000d
681#define ADCBS_BUFSIZE_3584 0x0000000e
682#define ADCBS_BUFSIZE_4096 0x0000000f
683#define ADCBS_BUFSIZE_5120 0x00000010
684#define ADCBS_BUFSIZE_6144 0x00000011
685#define ADCBS_BUFSIZE_7168 0x00000012
686#define ADCBS_BUFSIZE_8192 0x00000013
687#define ADCBS_BUFSIZE_10240 0x00000014
688#define ADCBS_BUFSIZE_12288 0x00000015
689#define ADCBS_BUFSIZE_14366 0x00000016
690#define ADCBS_BUFSIZE_16384 0x00000017
691#define ADCBS_BUFSIZE_20480 0x00000018
692#define ADCBS_BUFSIZE_24576 0x00000019
693#define ADCBS_BUFSIZE_28672 0x0000001a
694#define ADCBS_BUFSIZE_32768 0x0000001b
695#define ADCBS_BUFSIZE_40960 0x0000001c
696#define ADCBS_BUFSIZE_49152 0x0000001d
697#define ADCBS_BUFSIZE_57344 0x0000001e
698#define ADCBS_BUFSIZE_65536 0x0000001f
699
700/* Current Send B, A Amounts */
701#define A_CSBA 0x4c
702
703/* Current Send D, C Amounts */
704#define A_CSDC 0x4d
705
706/* Current Send F, E Amounts */
707#define A_CSFE 0x4e
708
709/* Current Send H, G Amounts */
710#define A_CSHG 0x4f
711
712
713#define CDCS 0x50 /* CD-ROM digital channel status register */
714
715#define GPSCS 0x51 /* General Purpose SPDIF channel status register*/
716
717#define DBG 0x52 /* DO NOT PROGRAM THIS REGISTER!!! MAY DESTROY CHIP */
718
719/* S/PDIF Input C Channel Status */
720#define A_SPSC 0x52
721
722#define REG53 0x53 /* DO NOT PROGRAM THIS REGISTER!!! MAY DESTROY CHIP */
723
724#define A_DBG 0x53
725#define A_DBG_SINGLE_STEP 0x00020000 /* Set to zero to start dsp */
726#define A_DBG_ZC 0x40000000 /* zero tram counter */
727#define A_DBG_STEP_ADDR 0x000003ff
728#define A_DBG_SATURATION_OCCURED 0x20000000
729#define A_DBG_SATURATION_ADDR 0x0ffc0000
730
731// NOTE: 0x54,55,56: 64-bit
732#define SPCS0 0x54 /* SPDIF output Channel Status 0 register */
733
734#define SPCS1 0x55 /* SPDIF output Channel Status 1 register */
735
736#define SPCS2 0x56 /* SPDIF output Channel Status 2 register */
737
738#define SPCS_CLKACCYMASK 0x30000000 /* Clock accuracy */
739#define SPCS_CLKACCY_1000PPM 0x00000000 /* 1000 parts per million */
740#define SPCS_CLKACCY_50PPM 0x10000000 /* 50 parts per million */
741#define SPCS_CLKACCY_VARIABLE 0x20000000 /* Variable accuracy */
742#define SPCS_SAMPLERATEMASK 0x0f000000 /* Sample rate */
743#define SPCS_SAMPLERATE_44 0x00000000 /* 44.1kHz sample rate */
744#define SPCS_SAMPLERATE_48 0x02000000 /* 48kHz sample rate */
745#define SPCS_SAMPLERATE_32 0x03000000 /* 32kHz sample rate */
746#define SPCS_CHANNELNUMMASK 0x00f00000 /* Channel number */
747#define SPCS_CHANNELNUM_UNSPEC 0x00000000 /* Unspecified channel number */
748#define SPCS_CHANNELNUM_LEFT 0x00100000 /* Left channel */
749#define SPCS_CHANNELNUM_RIGHT 0x00200000 /* Right channel */
750#define SPCS_SOURCENUMMASK 0x000f0000 /* Source number */
751#define SPCS_SOURCENUM_UNSPEC 0x00000000 /* Unspecified source number */
752#define SPCS_GENERATIONSTATUS 0x00008000 /* Originality flag (see IEC-958 spec) */
753#define SPCS_CATEGORYCODEMASK 0x00007f00 /* Category code (see IEC-958 spec) */
754#define SPCS_MODEMASK 0x000000c0 /* Mode (see IEC-958 spec) */
755#define SPCS_EMPHASISMASK 0x00000038 /* Emphasis */
756#define SPCS_EMPHASIS_NONE 0x00000000 /* No emphasis */
757#define SPCS_EMPHASIS_50_15 0x00000008 /* 50/15 usec 2 channel */
758#define SPCS_COPYRIGHT 0x00000004 /* Copyright asserted flag -- do not modify */
759#define SPCS_NOTAUDIODATA 0x00000002 /* 0 = Digital audio, 1 = not audio */
760#define SPCS_PROFESSIONAL 0x00000001 /* 0 = Consumer (IEC-958), 1 = pro (AES3-1992) */
761
762/* 0x57: Not used */
763
764/* The 32-bit CLIx and SOLx registers all have one bit per channel control/status */
765#define CLIEL 0x58 /* Channel loop interrupt enable low register */
766
767#define CLIEH 0x59 /* Channel loop interrupt enable high register */
768
769#define CLIPL 0x5a /* Channel loop interrupt pending low register */
770
771#define CLIPH 0x5b /* Channel loop interrupt pending high register */
772
773#define SOLEL 0x5c /* Stop on loop enable low register */
774
775#define SOLEH 0x5d /* Stop on loop enable high register */
776
777#define SPBYPASS 0x5e /* SPDIF BYPASS mode register */
778#define SPBYPASS_SPDIF0_MASK 0x00000003 /* SPDIF 0 bypass mode */
779#define SPBYPASS_SPDIF1_MASK 0x0000000c /* SPDIF 1 bypass mode */
780/* bypass mode: 0 - DSP; 1 - SPDIF A, 2 - SPDIF B, 3 - SPDIF C */
781#define SPBYPASS_FORMAT 0x00000f00 /* If 1, SPDIF XX uses 24 bit, if 0 - 20 bit */
782
783#define AC97SLOT 0x5f /* additional AC97 slots enable bits */
784#define AC97SLOT_REAR_RIGHT 0x01 /* Rear left */
785#define AC97SLOT_REAR_LEFT 0x02 /* Rear right */
786#define AC97SLOT_CNTR 0x10 /* Center enable */
787#define AC97SLOT_LFE 0x20 /* LFE enable */
788
789/* PCB Revision */
790#define A_PCB 0x5f
791
792// NOTE: 0x60,61,62: 64-bit
793#define CDSRCS 0x60 /* CD-ROM Sample Rate Converter status register */
794
795#define GPSRCS 0x61 /* General Purpose SPDIF sample rate cvt status */
796
797#define ZVSRCS 0x62 /* ZVideo sample rate converter status */
798                        /* NOTE: This one has no SPDIFLOCKED field */
799                        /* Assumes sample lock */
800
801/* These three bitfields apply to CDSRCS, GPSRCS, and (except as noted) ZVSRCS. */
802#define SRCS_SPDIFVALID 0x04000000 /* SPDIF stream valid */
803#define SRCS_SPDIFLOCKED 0x02000000 /* SPDIF stream locked */
804#define SRCS_RATELOCKED 0x01000000 /* Sample rate locked */
805#define SRCS_ESTSAMPLERATE 0x0007ffff /* Do not modify this field. */
806
807/* Note that these values can vary +/- by a small amount */
808#define SRCS_SPDIFRATE_44 0x0003acd9
809#define SRCS_SPDIFRATE_48 0x00040000
810#define SRCS_SPDIFRATE_96 0x00080000
811
812#define MICIDX 0x63 /* Microphone recording buffer index register */
813#define MICIDX_MASK 0x0000ffff /* 16-bit value */
814#define MICIDX_IDX 0x10000063
815
816#define ADCIDX 0x64 /* ADC recording buffer index register */
817#define ADCIDX_MASK 0x0000ffff /* 16 bit index field */
818#define ADCIDX_IDX 0x10000064
819
820#define A_ADCIDX 0x63
821#define A_ADCIDX_IDX 0x10000063
822
823#define A_MICIDX 0x64
824#define A_MICIDX_IDX 0x10000064
825
826#define FXIDX 0x65 /* FX recording buffer index register */
827#define FXIDX_MASK 0x0000ffff /* 16-bit value */
828#define FXIDX_IDX 0x10000065
829
830/* The 32-bit HLIx and HLIPx registers all have one bit per channel control/status */
831#define HLIEL 0x66 /* Channel half loop interrupt enable low register */
832
833#define HLIEH 0x67 /* Channel half loop interrupt enable high register */
834
835#define HLIPL 0x68 /* Channel half loop interrupt pending low register */
836
837#define HLIPH 0x69 /* Channel half loop interrupt pending high register */
838
839/* S/PDIF Host Record Index (bypasses SRC) */
840#define A_SPRI 0x6a
841/* S/PDIF Host Record Address */
842#define A_SPRA 0x6b
843/* S/PDIF Host Record Control */
844#define A_SPRC 0x6c
845/* Delayed Interrupt Counter & Enable */
846#define A_DICE 0x6d
847/* Tank Table Base */
848#define A_TTB 0x6e
849/* Tank Delay Offset */
850#define A_TDOF 0x6f
851
852/* This is the MPU port on the card (via the game port) */
853#define A_MUDATA1 0x70
854#define A_MUCMD1 0x71
855#define A_MUSTAT1 A_MUCMD1
856
857/* This is the MPU port on the Audigy Drive */
858#define A_MUDATA2 0x72
859#define A_MUCMD2 0x73
860#define A_MUSTAT2 A_MUCMD2
861
862/* The next two are the Audigy equivalent of FXWC */
863/* the Audigy can record any output (16bit, 48kHz, up to 64 channel simultaneously) */
864/* Each bit selects a channel for recording */
865#define A_FXWC1 0x74 /* Selects 0x7f-0x60 for FX recording */
866#define A_FXWC2 0x75 /* Selects 0x9f-0x80 for FX recording */
867
868/* Extended Hardware Control */
869#define A_SPDIF_SAMPLERATE 0x76 /* Set the sample rate of SPDIF output */
870#define A_SAMPLE_RATE 0x76 /* Various sample rate settings. */
871#define A_SAMPLE_RATE_NOT_USED 0x0ffc111e /* Bits that are not used and cannot be set. */
872#define A_SAMPLE_RATE_UNKNOWN 0xf0030001 /* Bits that can be set, but have unknown use. */
873#define A_SPDIF_RATE_MASK 0x000000e0 /* Any other values for rates, just use 48000 */
874#define A_SPDIF_48000 0x00000000
875#define A_SPDIF_192000 0x00000020
876#define A_SPDIF_96000 0x00000040
877#define A_SPDIF_44100 0x00000080
878
879#define A_I2S_CAPTURE_RATE_MASK 0x00000e00 /* This sets the capture PCM rate, but it is */
880#define A_I2S_CAPTURE_48000 0x00000000 /* unclear if this sets the ADC rate as well. */
881#define A_I2S_CAPTURE_192000 0x00000200
882#define A_I2S_CAPTURE_96000 0x00000400
883#define A_I2S_CAPTURE_44100 0x00000800
884
885#define A_PCM_RATE_MASK 0x0000e000 /* This sets the playback PCM rate on the P16V */
886#define A_PCM_48000 0x00000000
887#define A_PCM_192000 0x00002000
888#define A_PCM_96000 0x00004000
889#define A_PCM_44100 0x00008000
890
891/* I2S0 Sample Rate Tracker Status */
892#define A_SRT3 0x77
893
894/* I2S1 Sample Rate Tracker Status */
895#define A_SRT4 0x78
896
897/* I2S2 Sample Rate Tracker Status */
898#define A_SRT5 0x79
899/* - default to 0x01080000 on my audigy 2 ZS --rlrevell */
900
901/* Tank Table DMA Address */
902#define A_TTDA 0x7a
903/* Tank Table DMA Data */
904#define A_TTDD 0x7b
905
906#define A_FXRT2 0x7c
907#define A_FXRT_CHANNELE 0x0000003f /* Effects send bus number for channel's effects send E */
908#define A_FXRT_CHANNELF 0x00003f00 /* Effects send bus number for channel's effects send F */
909#define A_FXRT_CHANNELG 0x003f0000 /* Effects send bus number for channel's effects send G */
910#define A_FXRT_CHANNELH 0x3f000000 /* Effects send bus number for channel's effects send H */
911
912#define A_SENDAMOUNTS 0x7d
913#define A_FXSENDAMOUNT_E_MASK 0xFF000000
914#define A_FXSENDAMOUNT_F_MASK 0x00FF0000
915#define A_FXSENDAMOUNT_G_MASK 0x0000FF00
916#define A_FXSENDAMOUNT_H_MASK 0x000000FF
917/* 0x7c, 0x7e "high bit is used for filtering" */
918 
919/* The send amounts for this one are the same as used with the emu10k1 */
920#define A_FXRT1 0x7e
921#define A_FXRT_CHANNELA 0x0000003f
922#define A_FXRT_CHANNELB 0x00003f00
923#define A_FXRT_CHANNELC 0x003f0000
924#define A_FXRT_CHANNELD 0x3f000000
925
926/* 0x7f: Not used */
927/* Each FX general purpose register is 32 bits in length, all bits are used */
928#define FXGPREGBASE 0x100 /* FX general purpose registers base */
929#define A_FXGPREGBASE 0x400 /* Audigy GPRs, 0x400 to 0x5ff */
930
931#define A_TANKMEMCTLREGBASE 0x100 /* Tank memory control registers base - only for Audigy */
932#define A_TANKMEMCTLREG_MASK 0x1f /* only 5 bits used - only for Audigy */
933
934/* Tank audio data is logarithmically compressed down to 16 bits before writing to TRAM and is */
935/* decompressed back to 20 bits on a read. There are a total of 160 locations, the last 32 */
936/* locations are for external TRAM. */
937#define TANKMEMDATAREGBASE 0x200 /* Tank memory data registers base */
938#define TANKMEMDATAREG_MASK 0x000fffff /* 20 bit tank audio data field */
939
940/* Combined address field and memory opcode or flag field. 160 locations, last 32 are external */
941#define TANKMEMADDRREGBASE 0x300 /* Tank memory address registers base */
942#define TANKMEMADDRREG_ADDR_MASK 0x000fffff /* 20 bit tank address field */
943#define TANKMEMADDRREG_CLEAR 0x00800000 /* Clear tank memory */
944#define TANKMEMADDRREG_ALIGN 0x00400000 /* Align read or write relative to tank access */
945#define TANKMEMADDRREG_WRITE 0x00200000 /* Write to tank memory */
946#define TANKMEMADDRREG_READ 0x00100000 /* Read from tank memory */
947
948#define MICROCODEBASE 0x400 /* Microcode data base address */
949
950/* Each DSP microcode instruction is mapped into 2 doublewords */
951/* NOTE: When writing, always write the LO doubleword first. Reads can be in either order. */
952#define LOWORD_OPX_MASK 0x000ffc00 /* Instruction operand X */
953#define LOWORD_OPY_MASK 0x000003ff /* Instruction operand Y */
954#define HIWORD_OPCODE_MASK 0x00f00000 /* Instruction opcode */
955#define HIWORD_RESULT_MASK 0x000ffc00 /* Instruction result */
956#define HIWORD_OPA_MASK 0x000003ff /* Instruction operand A */
957
958
959/* Audigy Soundcard have a different instruction format */
960#define A_MICROCODEBASE 0x600
961#define A_LOWORD_OPY_MASK 0x000007ff
962#define A_LOWORD_OPX_MASK 0x007ff000
963#define A_HIWORD_OPCODE_MASK 0x0f000000
964#define A_HIWORD_RESULT_MASK 0x007ff000
965#define A_HIWORD_OPA_MASK 0x000007ff
966
967/************************************************************************************************/
968/* EMU1010m HANA FPGA registers */
969/************************************************************************************************/
970#define EMU_HANA_DESTHI 0x00 /* 0000xxx 3 bits Link Destination */
971#define EMU_HANA_DESTLO 0x01 /* 00xxxxx 5 bits */
972#define EMU_HANA_SRCHI 0x02 /* 0000xxx 3 bits Link Source */
973#define EMU_HANA_SRCLO 0x03 /* 00xxxxx 5 bits */
974#define EMU_HANA_DOCK_PWR 0x04 /* 000000x 1 bits Audio Dock power */
975#define EMU_HANA_DOCK_PWR_ON 0x01 /* Audio Dock power on */
976#define EMU_HANA_WCLOCK 0x05 /* 0000xxx 3 bits Word Clock source select */
977                    /* Must be written after power on to reset DLL */
978                    /* One is unable to detect the Audio dock without this */
979#define EMU_HANA_WCLOCK_SRC_MASK 0x07
980#define EMU_HANA_WCLOCK_INT_48K 0x00
981#define EMU_HANA_WCLOCK_INT_44_1K 0x01
982#define EMU_HANA_WCLOCK_HANA_SPDIF_IN 0x02
983#define EMU_HANA_WCLOCK_HANA_ADAT_IN 0x03
984#define EMU_HANA_WCLOCK_SYNC_BNCN 0x04
985#define EMU_HANA_WCLOCK_2ND_HANA 0x05
986#define EMU_HANA_WCLOCK_SRC_RESERVED 0x06
987#define EMU_HANA_WCLOCK_OFF 0x07 /* For testing, forces fallback to DEFCLOCK */
988#define EMU_HANA_WCLOCK_MULT_MASK 0x18
989#define EMU_HANA_WCLOCK_1X 0x00
990#define EMU_HANA_WCLOCK_2X 0x08
991#define EMU_HANA_WCLOCK_4X 0x10
992#define EMU_HANA_WCLOCK_MULT_RESERVED 0x18
993
994#define EMU_HANA_DEFCLOCK 0x06 /* 000000x 1 bits Default Word Clock */
995#define EMU_HANA_DEFCLOCK_48K 0x00
996#define EMU_HANA_DEFCLOCK_44_1K 0x01
997
998#define EMU_HANA_UNMUTE 0x07 /* 000000x 1 bits Mute all audio outputs */
999#define EMU_MUTE 0x00
1000#define EMU_UNMUTE 0x01
1001
1002#define EMU_HANA_FPGA_CONFIG 0x08 /* 00000xx 2 bits Config control of FPGAs */
1003#define EMU_HANA_FPGA_CONFIG_AUDIODOCK 0x01 /* Set in order to program FPGA on Audio Dock */
1004#define EMU_HANA_FPGA_CONFIG_HANA 0x02 /* Set in order to program FPGA on Hana */
1005
1006#define EMU_HANA_IRQ_ENABLE 0x09 /* 000xxxx 4 bits IRQ Enable */
1007#define EMU_HANA_IRQ_WCLK_CHANGED 0x01
1008#define EMU_HANA_IRQ_ADAT 0x02
1009#define EMU_HANA_IRQ_DOCK 0x04
1010#define EMU_HANA_IRQ_DOCK_LOST 0x08
1011
1012#define EMU_HANA_SPDIF_MODE 0x0a /* 00xxxxx 5 bits SPDIF MODE */
1013#define EMU_HANA_SPDIF_MODE_TX_COMSUMER 0x00
1014#define EMU_HANA_SPDIF_MODE_TX_PRO 0x01
1015#define EMU_HANA_SPDIF_MODE_TX_NOCOPY 0x02
1016#define EMU_HANA_SPDIF_MODE_RX_COMSUMER 0x00
1017#define EMU_HANA_SPDIF_MODE_RX_PRO 0x04
1018#define EMU_HANA_SPDIF_MODE_RX_NOCOPY 0x08
1019#define EMU_HANA_SPDIF_MODE_RX_INVALID 0x10
1020
1021#define EMU_HANA_OPTICAL_TYPE 0x0b /* 00000xx 2 bits ADAT or SPDIF in/out */
1022#define EMU_HANA_OPTICAL_IN_SPDIF 0x00
1023#define EMU_HANA_OPTICAL_IN_ADAT 0x01
1024#define EMU_HANA_OPTICAL_OUT_SPDIF 0x00
1025#define EMU_HANA_OPTICAL_OUT_ADAT 0x02
1026
1027#define EMU_HANA_MIDI_IN 0x0c /* 000000x 1 bit Control MIDI */
1028#define EMU_HANA_MIDI_IN_FROM_HAMOA 0x00 /* HAMOA MIDI in to Alice 2 MIDI B */
1029#define EMU_HANA_MIDI_IN_FROM_DOCK 0x01 /* Audio Dock MIDI in to Alice 2 MIDI B */
1030
1031#define EMU_HANA_DOCK_LEDS_1 0x0d /* 000xxxx 4 bit Audio Dock LEDs */
1032#define EMU_HANA_DOCK_LEDS_1_MIDI1 0x01 /* MIDI 1 LED on */
1033#define EMU_HANA_DOCK_LEDS_1_MIDI2 0x02 /* MIDI 2 LED on */
1034#define EMU_HANA_DOCK_LEDS_1_SMPTE_IN 0x04 /* SMPTE IN LED on */
1035#define EMU_HANA_DOCK_LEDS_1_SMPTE_OUT 0x08 /* SMPTE OUT LED on */
1036
1037#define EMU_HANA_DOCK_LEDS_2 0x0e /* 0xxxxxx 6 bit Audio Dock LEDs */
1038#define EMU_HANA_DOCK_LEDS_2_44K 0x01 /* 44.1 kHz LED on */
1039#define EMU_HANA_DOCK_LEDS_2_48K 0x02 /* 48 kHz LED on */
1040#define EMU_HANA_DOCK_LEDS_2_96K 0x04 /* 96 kHz LED on */
1041#define EMU_HANA_DOCK_LEDS_2_192K 0x08 /* 192 kHz LED on */
1042#define EMU_HANA_DOCK_LEDS_2_LOCK 0x10 /* LOCK LED on */
1043#define EMU_HANA_DOCK_LEDS_2_EXT 0x20 /* EXT LED on */
1044
1045#define EMU_HANA_DOCK_LEDS_3 0x0f /* 0xxxxxx 6 bit Audio Dock LEDs */
1046#define EMU_HANA_DOCK_LEDS_3_CLIP_A 0x01 /* Mic A Clip LED on */
1047#define EMU_HANA_DOCK_LEDS_3_CLIP_B 0x02 /* Mic B Clip LED on */
1048#define EMU_HANA_DOCK_LEDS_3_SIGNAL_A 0x04 /* Signal A Clip LED on */
1049#define EMU_HANA_DOCK_LEDS_3_SIGNAL_B 0x08 /* Signal B Clip LED on */
1050#define EMU_HANA_DOCK_LEDS_3_MANUAL_CLIP 0x10 /* Manual Clip detection */
1051#define EMU_HANA_DOCK_LEDS_3_MANUAL_SIGNAL 0x20 /* Manual Signal detection */
1052
1053#define EMU_HANA_ADC_PADS 0x10 /* 0000xxx 3 bit Audio Dock ADC 14dB pads */
1054#define EMU_HANA_DOCK_ADC_PAD1 0x01 /* 14dB Attenuation on Audio Dock ADC 1 */
1055#define EMU_HANA_DOCK_ADC_PAD2 0x02 /* 14dB Attenuation on Audio Dock ADC 2 */
1056#define EMU_HANA_DOCK_ADC_PAD3 0x04 /* 14dB Attenuation on Audio Dock ADC 3 */
1057#define EMU_HANA_0202_ADC_PAD1 0x08 /* 14dB Attenuation on 0202 ADC 1 */
1058
1059#define EMU_HANA_DOCK_MISC 0x11 /* 0xxxxxx 6 bit Audio Dock misc bits */
1060#define EMU_HANA_DOCK_DAC1_MUTE 0x01 /* DAC 1 Mute */
1061#define EMU_HANA_DOCK_DAC2_MUTE 0x02 /* DAC 2 Mute */
1062#define EMU_HANA_DOCK_DAC3_MUTE 0x04 /* DAC 3 Mute */
1063#define EMU_HANA_DOCK_DAC4_MUTE 0x08 /* DAC 4 Mute */
1064#define EMU_HANA_DOCK_PHONES_192_DAC1 0x00 /* DAC 1 Headphones source at 192kHz */
1065#define EMU_HANA_DOCK_PHONES_192_DAC2 0x10 /* DAC 2 Headphones source at 192kHz */
1066#define EMU_HANA_DOCK_PHONES_192_DAC3 0x20 /* DAC 3 Headphones source at 192kHz */
1067#define EMU_HANA_DOCK_PHONES_192_DAC4 0x30 /* DAC 4 Headphones source at 192kHz */
1068
1069#define EMU_HANA_MIDI_OUT 0x12 /* 00xxxxx 5 bit Source for each MIDI out port */
1070#define EMU_HANA_MIDI_OUT_0202 0x01 /* 0202 MIDI from Alice 2. 0 = A, 1 = B */
1071#define EMU_HANA_MIDI_OUT_DOCK1 0x02 /* Audio Dock MIDI1 front, from Alice 2. 0 = A, 1 = B */
1072#define EMU_HANA_MIDI_OUT_DOCK2 0x04 /* Audio Dock MIDI2 rear, from Alice 2. 0 = A, 1 = B */
1073#define EMU_HANA_MIDI_OUT_SYNC2 0x08 /* Sync card. Not the actual MIDI out jack. 0 = A, 1 = B */
1074#define EMU_HANA_MIDI_OUT_LOOP 0x10 /* 0 = bits (3:0) normal. 1 = MIDI loopback enabled. */
1075
1076#define EMU_HANA_DAC_PADS 0x13 /* 00xxxxx 5 bit DAC 14dB attenuation pads */
1077#define EMU_HANA_DOCK_DAC_PAD1 0x01 /* 14dB Attenuation on AudioDock DAC 1. Left and Right */
1078#define EMU_HANA_DOCK_DAC_PAD2 0x02 /* 14dB Attenuation on AudioDock DAC 2. Left and Right */
1079#define EMU_HANA_DOCK_DAC_PAD3 0x04 /* 14dB Attenuation on AudioDock DAC 3. Left and Right */
1080#define EMU_HANA_DOCK_DAC_PAD4 0x08 /* 14dB Attenuation on AudioDock DAC 4. Left and Right */
1081#define EMU_HANA_0202_DAC_PAD1 0x10 /* 14dB Attenuation on 0202 DAC 1. Left and Right */
1082
1083/* 0x14 - 0x1f Unused R/W registers */
1084#define EMU_HANA_IRQ_STATUS 0x20 /* 000xxxx 4 bits IRQ Status */
1085#if 0 /* Already defined for reg 0x09 IRQ_ENABLE */
1086#define EMU_HANA_IRQ_WCLK_CHANGED 0x01
1087#define EMU_HANA_IRQ_ADAT 0x02
1088#define EMU_HANA_IRQ_DOCK 0x04
1089#define EMU_HANA_IRQ_DOCK_LOST 0x08
1090#endif
1091
1092#define EMU_HANA_OPTION_CARDS 0x21 /* 000xxxx 4 bits Presence of option cards */
1093#define EMU_HANA_OPTION_HAMOA 0x01 /* HAMOA card present */
1094#define EMU_HANA_OPTION_SYNC 0x02 /* Sync card present */
1095#define EMU_HANA_OPTION_DOCK_ONLINE 0x04 /* Audio Dock online and FPGA configured */
1096#define EMU_HANA_OPTION_DOCK_OFFLINE 0x08 /* Audio Dock online and FPGA not configured */
1097
1098#define EMU_HANA_ID 0x22 /* 1010101 7 bits ID byte & 0x7f = 0x55 */
1099
1100#define EMU_HANA_MAJOR_REV 0x23 /* 0000xxx 3 bit Hana FPGA Major rev */
1101#define EMU_HANA_MINOR_REV 0x24 /* 0000xxx 3 bit Hana FPGA Minor rev */
1102
1103#define EMU_DOCK_MAJOR_REV 0x25 /* 0000xxx 3 bit Audio Dock FPGA Major rev */
1104#define EMU_DOCK_MINOR_REV 0x26 /* 0000xxx 3 bit Audio Dock FPGA Minor rev */
1105
1106#define EMU_DOCK_BOARD_ID 0x27 /* 00000xx 2 bits Audio Dock ID pins */
1107#define EMU_DOCK_BOARD_ID0 0x00 /* ID bit 0 */
1108#define EMU_DOCK_BOARD_ID1 0x03 /* ID bit 1 */
1109
1110#define EMU_HANA_WC_SPDIF_HI 0x28 /* 0xxxxxx 6 bit SPDIF IN Word clock, upper 6 bits */
1111#define EMU_HANA_WC_SPDIF_LO 0x29 /* 0xxxxxx 6 bit SPDIF IN Word clock, lower 6 bits */
1112
1113#define EMU_HANA_WC_ADAT_HI 0x2a /* 0xxxxxx 6 bit ADAT IN Word clock, upper 6 bits */
1114#define EMU_HANA_WC_ADAT_LO 0x2b /* 0xxxxxx 6 bit ADAT IN Word clock, lower 6 bits */
1115
1116#define EMU_HANA_WC_BNC_LO 0x2c /* 0xxxxxx 6 bit BNC IN Word clock, lower 6 bits */
1117#define EMU_HANA_WC_BNC_HI 0x2d /* 0xxxxxx 6 bit BNC IN Word clock, upper 6 bits */
1118
1119#define EMU_HANA2_WC_SPDIF_HI 0x2e /* 0xxxxxx 6 bit HANA2 SPDIF IN Word clock, upper 6 bits */
1120#define EMU_HANA2_WC_SPDIF_LO 0x2f /* 0xxxxxx 6 bit HANA2 SPDIF IN Word clock, lower 6 bits */
1121/* 0x30 - 0x3f Unused Read only registers */
1122
1123/************************************************************************************************/
1124/* EMU1010m HANA Destinations */
1125/************************************************************************************************/
1126/* Hana, original 1010,1212,1820 using Alice2
1127 * Destiniations for SRATEX = 1X rates: 44.1 kHz or 48 kHz
1128 * 0x00, 0x00-0x0f: 16 EMU32 channels to Alice2
1129 * 0x01, 0x10-0x1f: 32 Elink channels to Audio Dock
1130 * 0x01, 0x00: Dock DAC 1 Left
1131 * 0x01, 0x04: Dock DAC 1 Right
1132 * 0x01, 0x08: Dock DAC 2 Left
1133 * 0x01, 0x0c: Dock DAC 2 Right
1134 * 0x01, 0x10: Dock DAC 3 Left
1135 * 0x01, 0x12: PHONES Left
1136 * 0x01, 0x14: Dock DAC 3 Right
1137 * 0x01, 0x16: PHONES Right
1138 * 0x01, 0x18: Dock DAC 4 Left
1139 * 0x01, 0x1a: S/PDIF Left
1140 * 0x01, 0x1c: Dock DAC 4 Right
1141 * 0x01, 0x1e: S/PDIF Right
1142 * 0x02, 0x00: Hana S/PDIF Left
1143 * 0x02, 0x01: Hana S/PDIF Right
1144 * 0x03, 0x00: Hanoa DAC Left
1145 * 0x03, 0x01: Hanoa DAC Right
1146 * 0x04, 0x00-0x07: Hana ADAT
1147 * 0x05, 0x00: I2S0 Left to Alice2
1148 * 0x05, 0x01: I2S0 Right to Alice2
1149 * 0x06, 0x00: I2S0 Left to Alice2
1150 * 0x06, 0x01: I2S0 Right to Alice2
1151 * 0x07, 0x00: I2S0 Left to Alice2
1152 * 0x07, 0x01: I2S0 Right to Alice2
1153 *
1154 * Hana2 never released, but used Tina
1155 * Not needed.
1156 *
1157 * Hana3, rev2 1010,1212,1616 using Tina
1158 * Destinations for SRATEX = 1X rates: 44.1 kHz or 48 kHz
1159 * 0x00, 0x00-0x0f: 16 EMU32A channels to Tina
1160 * 0x01, 0x10-0x1f: 32 EDI channels to Micro Dock
1161 * 0x01, 0x00: Dock DAC 1 Left
1162 * 0x01, 0x04: Dock DAC 1 Right
1163 * 0x01, 0x08: Dock DAC 2 Left
1164 * 0x01, 0x0c: Dock DAC 2 Right
1165 * 0x01, 0x10: Dock DAC 3 Left
1166 * 0x01, 0x12: Dock S/PDIF Left
1167 * 0x01, 0x14: Dock DAC 3 Right
1168 * 0x01, 0x16: Dock S/PDIF Right
1169 * 0x01, 0x18-0x1f: Dock ADAT 0-7
1170 * 0x02, 0x00: Hana3 S/PDIF Left
1171 * 0x02, 0x01: Hana3 S/PDIF Right
1172 * 0x03, 0x00: Hanoa DAC Left
1173 * 0x03, 0x01: Hanoa DAC Right
1174 * 0x04, 0x00-0x07: Hana3 ADAT 0-7
1175 * 0x05, 0x00-0x0f: 16 EMU32B channels to Tina
1176 * 0x06-0x07: Not used
1177 *
1178 * HanaLite, rev1 0404 using Alice2
1179 * Destiniations for SRATEX = 1X rates: 44.1 kHz or 48 kHz
1180 * 0x00, 0x00-0x0f: 16 EMU32 channels to Alice2
1181 * 0x01: Not used
1182 * 0x02, 0x00: S/PDIF Left
1183 * 0x02, 0x01: S/PDIF Right
1184 * 0x03, 0x00: DAC Left
1185 * 0x03, 0x01: DAC Right
1186 * 0x04-0x07: Not used
1187 *
1188 * HanaLiteLite, rev2 0404 using Alice2
1189 * Destiniations for SRATEX = 1X rates: 44.1 kHz or 48 kHz
1190 * 0x00, 0x00-0x0f: 16 EMU32 channels to Alice2
1191 * 0x01: Not used
1192 * 0x02, 0x00: S/PDIF Left
1193 * 0x02, 0x01: S/PDIF Right
1194 * 0x03, 0x00: DAC Left
1195 * 0x03, 0x01: DAC Right
1196 * 0x04-0x07: Not used
1197 *
1198 * Mana, Cardbus 1616 using Tina2
1199 * Destinations for SRATEX = 1X rates: 44.1 kHz or 48 kHz
1200 * 0x00, 0x00-0x0f: 16 EMU32A channels to Tina2
1201 * 0x01, 0x10-0x1f: 32 EDI channels to Micro Dock
1202 * 0x01, 0x00: Dock DAC 1 Left
1203 * 0x01, 0x04: Dock DAC 1 Right
1204 * 0x01, 0x08: Dock DAC 2 Left
1205 * 0x01, 0x0c: Dock DAC 2 Right
1206 * 0x01, 0x10: Dock DAC 3 Left
1207 * 0x01, 0x12: Dock S/PDIF Left
1208 * 0x01, 0x14: Dock DAC 3 Right
1209 * 0x01, 0x16: Dock S/PDIF Right
1210 * 0x01, 0x18-0x1f: Dock ADAT 0-7
1211 * 0x02: Not used
1212 * 0x03, 0x00: Mana DAC Left
1213 * 0x03, 0x01: Mana DAC Right
1214 * 0x04, 0x00-0x0f: 16 EMU32B channels to Tina2
1215 * 0x05-0x07: Not used
1216 *
1217 *
1218 */
1219/* 32-bit destinations of signal in the Hana FPGA. Destinations are either
1220 * physical outputs of Hana, or outputs going to Alice2 (audigy) for capture
1221 * - 16 x EMU_DST_ALICE2_EMU32_X.
1222 */
1223/* EMU32 = 32-bit serial channel between Alice2 (audigy) and Hana (FPGA) */
1224/* EMU_DST_ALICE2_EMU32_X - data channels from Hana to Alice2 used for capture.
1225 * Which data is fed into a EMU_DST_ALICE2_EMU32_X channel in Hana depends on
1226 * setup of mixer control for each destination - see emumixer.c -
1227 * snd_emu1010_output_enum_ctls[], snd_emu1010_input_enum_ctls[]
1228 */
1229#define EMU_DST_ALICE2_EMU32_0 0x000f /* 16 EMU32 channels to Alice2 +0 to +0xf */
1230#define EMU_DST_ALICE2_EMU32_1 0x0000 /* 16 EMU32 channels to Alice2 +0 to +0xf */
1231#define EMU_DST_ALICE2_EMU32_2 0x0001 /* 16 EMU32 channels to Alice2 +0 to +0xf */
1232#define EMU_DST_ALICE2_EMU32_3 0x0002 /* 16 EMU32 channels to Alice2 +0 to +0xf */
1233#define EMU_DST_ALICE2_EMU32_4 0x0003 /* 16 EMU32 channels to Alice2 +0 to +0xf */
1234#define EMU_DST_ALICE2_EMU32_5 0x0004 /* 16 EMU32 channels to Alice2 +0 to +0xf */
1235#define EMU_DST_ALICE2_EMU32_6 0x0005 /* 16 EMU32 channels to Alice2 +0 to +0xf */
1236#define EMU_DST_ALICE2_EMU32_7 0x0006 /* 16 EMU32 channels to Alice2 +0 to +0xf */
1237#define EMU_DST_ALICE2_EMU32_8 0x0007 /* 16 EMU32 channels to Alice2 +0 to +0xf */
1238#define EMU_DST_ALICE2_EMU32_9 0x0008 /* 16 EMU32 channels to Alice2 +0 to +0xf */
1239#define EMU_DST_ALICE2_EMU32_A 0x0009 /* 16 EMU32 channels to Alice2 +0 to +0xf */
1240#define EMU_DST_ALICE2_EMU32_B 0x000a /* 16 EMU32 channels to Alice2 +0 to +0xf */
1241#define EMU_DST_ALICE2_EMU32_C 0x000b /* 16 EMU32 channels to Alice2 +0 to +0xf */
1242#define EMU_DST_ALICE2_EMU32_D 0x000c /* 16 EMU32 channels to Alice2 +0 to +0xf */
1243#define EMU_DST_ALICE2_EMU32_E 0x000d /* 16 EMU32 channels to Alice2 +0 to +0xf */
1244#define EMU_DST_ALICE2_EMU32_F 0x000e /* 16 EMU32 channels to Alice2 +0 to +0xf */
1245#define EMU_DST_DOCK_DAC1_LEFT1 0x0100 /* Audio Dock DAC1 Left, 1st or 48kHz only */
1246#define EMU_DST_DOCK_DAC1_LEFT2 0x0101 /* Audio Dock DAC1 Left, 2nd or 96kHz */
1247#define EMU_DST_DOCK_DAC1_LEFT3 0x0102 /* Audio Dock DAC1 Left, 3rd or 192kHz */
1248#define EMU_DST_DOCK_DAC1_LEFT4 0x0103 /* Audio Dock DAC1 Left, 4th or 192kHz */
1249#define EMU_DST_DOCK_DAC1_RIGHT1 0x0104 /* Audio Dock DAC1 Right, 1st or 48kHz only */
1250#define EMU_DST_DOCK_DAC1_RIGHT2 0x0105 /* Audio Dock DAC1 Right, 2nd or 96kHz */
1251#define EMU_DST_DOCK_DAC1_RIGHT3 0x0106 /* Audio Dock DAC1 Right, 3rd or 192kHz */
1252#define EMU_DST_DOCK_DAC1_RIGHT4 0x0107 /* Audio Dock DAC1 Right, 4th or 192kHz */
1253#define EMU_DST_DOCK_DAC2_LEFT1 0x0108 /* Audio Dock DAC2 Left, 1st or 48kHz only */
1254#define EMU_DST_DOCK_DAC2_LEFT2 0x0109 /* Audio Dock DAC2 Left, 2nd or 96kHz */
1255#define EMU_DST_DOCK_DAC2_LEFT3 0x010a /* Audio Dock DAC2 Left, 3rd or 192kHz */
1256#define EMU_DST_DOCK_DAC2_LEFT4 0x010b /* Audio Dock DAC2 Left, 4th or 192kHz */
1257#define EMU_DST_DOCK_DAC2_RIGHT1 0x010c /* Audio Dock DAC2 Right, 1st or 48kHz only */
1258#define EMU_DST_DOCK_DAC2_RIGHT2 0x010d /* Audio Dock DAC2 Right, 2nd or 96kHz */
1259#define EMU_DST_DOCK_DAC2_RIGHT3 0x010e /* Audio Dock DAC2 Right, 3rd or 192kHz */
1260#define EMU_DST_DOCK_DAC2_RIGHT4 0x010f /* Audio Dock DAC2 Right, 4th or 192kHz */
1261#define EMU_DST_DOCK_DAC3_LEFT1 0x0110 /* Audio Dock DAC1 Left, 1st or 48kHz only */
1262#define EMU_DST_DOCK_DAC3_LEFT2 0x0111 /* Audio Dock DAC1 Left, 2nd or 96kHz */
1263#define EMU_DST_DOCK_DAC3_LEFT3 0x0112 /* Audio Dock DAC1 Left, 3rd or 192kHz */
1264#define EMU_DST_DOCK_DAC3_LEFT4 0x0113 /* Audio Dock DAC1 Left, 4th or 192kHz */
1265#define EMU_DST_DOCK_PHONES_LEFT1 0x0112 /* Audio Dock PHONES Left, 1st or 48kHz only */
1266#define EMU_DST_DOCK_PHONES_LEFT2 0x0113 /* Audio Dock PHONES Left, 2nd or 96kHz */
1267#define EMU_DST_DOCK_DAC3_RIGHT1 0x0114 /* Audio Dock DAC1 Right, 1st or 48kHz only */
1268#define EMU_DST_DOCK_DAC3_RIGHT2 0x0115 /* Audio Dock DAC1 Right, 2nd or 96kHz */
1269#define EMU_DST_DOCK_DAC3_RIGHT3 0x0116 /* Audio Dock DAC1 Right, 3rd or 192kHz */
1270#define EMU_DST_DOCK_DAC3_RIGHT4 0x0117 /* Audio Dock DAC1 Right, 4th or 192kHz */
1271#define EMU_DST_DOCK_PHONES_RIGHT1 0x0116 /* Audio Dock PHONES Right, 1st or 48kHz only */
1272#define EMU_DST_DOCK_PHONES_RIGHT2 0x0117 /* Audio Dock PHONES Right, 2nd or 96kHz */
1273#define EMU_DST_DOCK_DAC4_LEFT1 0x0118 /* Audio Dock DAC2 Left, 1st or 48kHz only */
1274#define EMU_DST_DOCK_DAC4_LEFT2 0x0119 /* Audio Dock DAC2 Left, 2nd or 96kHz */
1275#define EMU_DST_DOCK_DAC4_LEFT3 0x011a /* Audio Dock DAC2 Left, 3rd or 192kHz */
1276#define EMU_DST_DOCK_DAC4_LEFT4 0x011b /* Audio Dock DAC2 Left, 4th or 192kHz */
1277#define EMU_DST_DOCK_SPDIF_LEFT1 0x011a /* Audio Dock SPDIF Left, 1st or 48kHz only */
1278#define EMU_DST_DOCK_SPDIF_LEFT2 0x011b /* Audio Dock SPDIF Left, 2nd or 96kHz */
1279#define EMU_DST_DOCK_DAC4_RIGHT1 0x011c /* Audio Dock DAC2 Right, 1st or 48kHz only */
1280#define EMU_DST_DOCK_DAC4_RIGHT2 0x011d /* Audio Dock DAC2 Right, 2nd or 96kHz */
1281#define EMU_DST_DOCK_DAC4_RIGHT3 0x011e /* Audio Dock DAC2 Right, 3rd or 192kHz */
1282#define EMU_DST_DOCK_DAC4_RIGHT4 0x011f /* Audio Dock DAC2 Right, 4th or 192kHz */
1283#define EMU_DST_DOCK_SPDIF_RIGHT1 0x011e /* Audio Dock SPDIF Right, 1st or 48kHz only */
1284#define EMU_DST_DOCK_SPDIF_RIGHT2 0x011f /* Audio Dock SPDIF Right, 2nd or 96kHz */
1285#define EMU_DST_HANA_SPDIF_LEFT1 0x0200 /* Hana SPDIF Left, 1st or 48kHz only */
1286#define EMU_DST_HANA_SPDIF_LEFT2 0x0202 /* Hana SPDIF Left, 2nd or 96kHz */
1287#define EMU_DST_HANA_SPDIF_RIGHT1 0x0201 /* Hana SPDIF Right, 1st or 48kHz only */
1288#define EMU_DST_HANA_SPDIF_RIGHT2 0x0203 /* Hana SPDIF Right, 2nd or 96kHz */
1289#define EMU_DST_HAMOA_DAC_LEFT1 0x0300 /* Hamoa DAC Left, 1st or 48kHz only */
1290#define EMU_DST_HAMOA_DAC_LEFT2 0x0302 /* Hamoa DAC Left, 2nd or 96kHz */
1291#define EMU_DST_HAMOA_DAC_LEFT3 0x0304 /* Hamoa DAC Left, 3rd or 192kHz */
1292#define EMU_DST_HAMOA_DAC_LEFT4 0x0306 /* Hamoa DAC Left, 4th or 192kHz */
1293#define EMU_DST_HAMOA_DAC_RIGHT1 0x0301 /* Hamoa DAC Right, 1st or 48kHz only */
1294#define EMU_DST_HAMOA_DAC_RIGHT2 0x0303 /* Hamoa DAC Right, 2nd or 96kHz */
1295#define EMU_DST_HAMOA_DAC_RIGHT3 0x0305 /* Hamoa DAC Right, 3rd or 192kHz */
1296#define EMU_DST_HAMOA_DAC_RIGHT4 0x0307 /* Hamoa DAC Right, 4th or 192kHz */
1297#define EMU_DST_HANA_ADAT 0x0400 /* Hana ADAT 8 channel out +0 to +7 */
1298#define EMU_DST_ALICE_I2S0_LEFT 0x0500 /* Alice2 I2S0 Left */
1299#define EMU_DST_ALICE_I2S0_RIGHT 0x0501 /* Alice2 I2S0 Right */
1300#define EMU_DST_ALICE_I2S1_LEFT 0x0600 /* Alice2 I2S1 Left */
1301#define EMU_DST_ALICE_I2S1_RIGHT 0x0601 /* Alice2 I2S1 Right */
1302#define EMU_DST_ALICE_I2S2_LEFT 0x0700 /* Alice2 I2S2 Left */
1303#define EMU_DST_ALICE_I2S2_RIGHT 0x0701 /* Alice2 I2S2 Right */
1304
1305/* Additional destinations for 1616(M)/Microdock */
1306/* Microdock S/PDIF OUT Left, 1st or 48kHz only */
1307#define EMU_DST_MDOCK_SPDIF_LEFT1 0x0112
1308/* Microdock S/PDIF OUT Left, 2nd or 96kHz */
1309#define EMU_DST_MDOCK_SPDIF_LEFT2 0x0113
1310/* Microdock S/PDIF OUT Right, 1st or 48kHz only */
1311#define EMU_DST_MDOCK_SPDIF_RIGHT1 0x0116
1312/* Microdock S/PDIF OUT Right, 2nd or 96kHz */
1313#define EMU_DST_MDOCK_SPDIF_RIGHT2 0x0117
1314/* Microdock S/PDIF ADAT 8 channel out +8 to +f */
1315#define EMU_DST_MDOCK_ADAT 0x0118
1316
1317/* Headphone jack on 1010 cardbus? 44.1/48kHz only? */
1318#define EMU_DST_MANA_DAC_LEFT 0x0300
1319/* Headphone jack on 1010 cardbus? 44.1/48kHz only? */
1320#define EMU_DST_MANA_DAC_RIGHT 0x0301
1321
1322/************************************************************************************************/
1323/* EMU1010m HANA Sources */
1324/************************************************************************************************/
1325/* Hana, original 1010,1212,1820 using Alice2
1326 * Sources SRATEX = 1X rates: 44.1 kHz or 48 kHz
1327 * 0x00,0x00-0x1f: Silence
1328 * 0x01, 0x10-0x1f: 32 Elink channels from Audio Dock
1329 * 0x01, 0x00: Dock Mic A
1330 * 0x01, 0x04: Dock Mic B
1331 * 0x01, 0x08: Dock ADC 1 Left
1332 * 0x01, 0x0c: Dock ADC 1 Right
1333 * 0x01, 0x10: Dock ADC 2 Left
1334 * 0x01, 0x14: Dock ADC 2 Right
1335 * 0x01, 0x18: Dock ADC 3 Left
1336 * 0x01, 0x1c: Dock ADC 3 Right
1337 * 0x02, 0x00: Hana ADC Left
1338 * 0x02, 0x01: Hana ADC Right
1339 * 0x03, 0x00-0x0f: 16 inputs from Alice2 Emu32A output
1340 * 0x03, 0x10-0x1f: 16 inputs from Alice2 Emu32B output
1341 * 0x04, 0x00-0x07: Hana ADAT
1342 * 0x05, 0x00: Hana S/PDIF Left
1343 * 0x05, 0x01: Hana S/PDIF Right
1344 * 0x06-0x07: Not used
1345 *
1346 * Hana2 never released, but used Tina
1347 * Not needed.
1348 *
1349 * Hana3, rev2 1010,1212,1616 using Tina
1350 * Sources SRATEX = 1X rates: 44.1 kHz or 48 kHz
1351 * 0x00,0x00-0x1f: Silence
1352 * 0x01, 0x10-0x1f: 32 Elink channels from Audio Dock
1353 * 0x01, 0x00: Dock Mic A
1354 * 0x01, 0x04: Dock Mic B
1355 * 0x01, 0x08: Dock ADC 1 Left
1356 * 0x01, 0x0c: Dock ADC 1 Right
1357 * 0x01, 0x10: Dock ADC 2 Left
1358 * 0x01, 0x12: Dock S/PDIF Left
1359 * 0x01, 0x14: Dock ADC 2 Right
1360 * 0x01, 0x16: Dock S/PDIF Right
1361 * 0x01, 0x18-0x1f: Dock ADAT 0-7
1362 * 0x01, 0x18: Dock ADC 3 Left
1363 * 0x01, 0x1c: Dock ADC 3 Right
1364 * 0x02, 0x00: Hanoa ADC Left
1365 * 0x02, 0x01: Hanoa ADC Right
1366 * 0x03, 0x00-0x0f: 16 inputs from Tina Emu32A output
1367 * 0x03, 0x10-0x1f: 16 inputs from Tina Emu32B output
1368 * 0x04, 0x00-0x07: Hana3 ADAT
1369 * 0x05, 0x00: Hana3 S/PDIF Left
1370 * 0x05, 0x01: Hana3 S/PDIF Right
1371 * 0x06-0x07: Not used
1372 *
1373 * HanaLite, rev1 0404 using Alice2
1374 * Sources SRATEX = 1X rates: 44.1 kHz or 48 kHz
1375 * 0x00,0x00-0x1f: Silence
1376 * 0x01: Not used
1377 * 0x02, 0x00: ADC Left
1378 * 0x02, 0x01: ADC Right
1379 * 0x03, 0x00-0x0f: 16 inputs from Alice2 Emu32A output
1380 * 0x03, 0x10-0x1f: 16 inputs from Alice2 Emu32B output
1381 * 0x04: Not used
1382 * 0x05, 0x00: S/PDIF Left
1383 * 0x05, 0x01: S/PDIF Right
1384 * 0x06-0x07: Not used
1385 *
1386 * HanaLiteLite, rev2 0404 using Alice2
1387 * Sources SRATEX = 1X rates: 44.1 kHz or 48 kHz
1388 * 0x00,0x00-0x1f: Silence
1389 * 0x01: Not used
1390 * 0x02, 0x00: ADC Left
1391 * 0x02, 0x01: ADC Right
1392 * 0x03, 0x00-0x0f: 16 inputs from Alice2 Emu32A output
1393 * 0x03, 0x10-0x1f: 16 inputs from Alice2 Emu32B output
1394 * 0x04: Not used
1395 * 0x05, 0x00: S/PDIF Left
1396 * 0x05, 0x01: S/PDIF Right
1397 * 0x06-0x07: Not used
1398 *
1399 * Mana, Cardbus 1616 using Tina2
1400 * Sources SRATEX = 1X rates: 44.1 kHz or 48 kHz
1401 * 0x00,0x00-0x1f: Silence
1402 * 0x01, 0x10-0x1f: 32 Elink channels from Audio Dock
1403 * 0x01, 0x00: Dock Mic A
1404 * 0x01, 0x04: Dock Mic B
1405 * 0x01, 0x08: Dock ADC 1 Left
1406 * 0x01, 0x0c: Dock ADC 1 Right
1407 * 0x01, 0x10: Dock ADC 2 Left
1408 * 0x01, 0x12: Dock S/PDIF Left
1409 * 0x01, 0x14: Dock ADC 2 Right
1410 * 0x01, 0x16: Dock S/PDIF Right
1411 * 0x01, 0x18-0x1f: Dock ADAT 0-7
1412 * 0x01, 0x18: Dock ADC 3 Left
1413 * 0x01, 0x1c: Dock ADC 3 Right
1414 * 0x02: Not used
1415 * 0x03, 0x00-0x0f: 16 inputs from Tina Emu32A output
1416 * 0x03, 0x10-0x1f: 16 inputs from Tina Emu32B output
1417 * 0x04-0x07: Not used
1418 *
1419 */
1420
1421/* 32-bit sources of signal in the Hana FPGA. The sources are routed to
1422 * destinations using mixer control for each destination - see emumixer.c
1423 * Sources are either physical inputs of FPGA,
1424 * or outputs from Alice (audigy) - 16 x EMU_SRC_ALICE_EMU32A +
1425 * 16 x EMU_SRC_ALICE_EMU32B
1426 */
1427#define EMU_SRC_SILENCE 0x0000 /* Silence */
1428#define EMU_SRC_DOCK_MIC_A1 0x0100 /* Audio Dock Mic A, 1st or 48kHz only */
1429#define EMU_SRC_DOCK_MIC_A2 0x0101 /* Audio Dock Mic A, 2nd or 96kHz */
1430#define EMU_SRC_DOCK_MIC_A3 0x0102 /* Audio Dock Mic A, 3rd or 192kHz */
1431#define EMU_SRC_DOCK_MIC_A4 0x0103 /* Audio Dock Mic A, 4th or 192kHz */
1432#define EMU_SRC_DOCK_MIC_B1 0x0104 /* Audio Dock Mic B, 1st or 48kHz only */
1433#define EMU_SRC_DOCK_MIC_B2 0x0105 /* Audio Dock Mic B, 2nd or 96kHz */
1434#define EMU_SRC_DOCK_MIC_B3 0x0106 /* Audio Dock Mic B, 3rd or 192kHz */
1435#define EMU_SRC_DOCK_MIC_B4 0x0107 /* Audio Dock Mic B, 4th or 192kHz */
1436#define EMU_SRC_DOCK_ADC1_LEFT1 0x0108 /* Audio Dock ADC1 Left, 1st or 48kHz only */
1437#define EMU_SRC_DOCK_ADC1_LEFT2 0x0109 /* Audio Dock ADC1 Left, 2nd or 96kHz */
1438#define EMU_SRC_DOCK_ADC1_LEFT3 0x010a /* Audio Dock ADC1 Left, 3rd or 192kHz */
1439#define EMU_SRC_DOCK_ADC1_LEFT4 0x010b /* Audio Dock ADC1 Left, 4th or 192kHz */
1440#define EMU_SRC_DOCK_ADC1_RIGHT1 0x010c /* Audio Dock ADC1 Right, 1st or 48kHz only */
1441#define EMU_SRC_DOCK_ADC1_RIGHT2 0x010d /* Audio Dock ADC1 Right, 2nd or 96kHz */
1442#define EMU_SRC_DOCK_ADC1_RIGHT3 0x010e /* Audio Dock ADC1 Right, 3rd or 192kHz */
1443#define EMU_SRC_DOCK_ADC1_RIGHT4 0x010f /* Audio Dock ADC1 Right, 4th or 192kHz */
1444#define EMU_SRC_DOCK_ADC2_LEFT1 0x0110 /* Audio Dock ADC2 Left, 1st or 48kHz only */
1445#define EMU_SRC_DOCK_ADC2_LEFT2 0x0111 /* Audio Dock ADC2 Left, 2nd or 96kHz */
1446#define EMU_SRC_DOCK_ADC2_LEFT3 0x0112 /* Audio Dock ADC2 Left, 3rd or 192kHz */
1447#define EMU_SRC_DOCK_ADC2_LEFT4 0x0113 /* Audio Dock ADC2 Left, 4th or 192kHz */
1448#define EMU_SRC_DOCK_ADC2_RIGHT1 0x0114 /* Audio Dock ADC2 Right, 1st or 48kHz only */
1449#define EMU_SRC_DOCK_ADC2_RIGHT2 0x0115 /* Audio Dock ADC2 Right, 2nd or 96kHz */
1450#define EMU_SRC_DOCK_ADC2_RIGHT3 0x0116 /* Audio Dock ADC2 Right, 3rd or 192kHz */
1451#define EMU_SRC_DOCK_ADC2_RIGHT4 0x0117 /* Audio Dock ADC2 Right, 4th or 192kHz */
1452#define EMU_SRC_DOCK_ADC3_LEFT1 0x0118 /* Audio Dock ADC3 Left, 1st or 48kHz only */
1453#define EMU_SRC_DOCK_ADC3_LEFT2 0x0119 /* Audio Dock ADC3 Left, 2nd or 96kHz */
1454#define EMU_SRC_DOCK_ADC3_LEFT3 0x011a /* Audio Dock ADC3 Left, 3rd or 192kHz */
1455#define EMU_SRC_DOCK_ADC3_LEFT4 0x011b /* Audio Dock ADC3 Left, 4th or 192kHz */
1456#define EMU_SRC_DOCK_ADC3_RIGHT1 0x011c /* Audio Dock ADC3 Right, 1st or 48kHz only */
1457#define EMU_SRC_DOCK_ADC3_RIGHT2 0x011d /* Audio Dock ADC3 Right, 2nd or 96kHz */
1458#define EMU_SRC_DOCK_ADC3_RIGHT3 0x011e /* Audio Dock ADC3 Right, 3rd or 192kHz */
1459#define EMU_SRC_DOCK_ADC3_RIGHT4 0x011f /* Audio Dock ADC3 Right, 4th or 192kHz */
1460#define EMU_SRC_HAMOA_ADC_LEFT1 0x0200 /* Hamoa ADC Left, 1st or 48kHz only */
1461#define EMU_SRC_HAMOA_ADC_LEFT2 0x0202 /* Hamoa ADC Left, 2nd or 96kHz */
1462#define EMU_SRC_HAMOA_ADC_LEFT3 0x0204 /* Hamoa ADC Left, 3rd or 192kHz */
1463#define EMU_SRC_HAMOA_ADC_LEFT4 0x0206 /* Hamoa ADC Left, 4th or 192kHz */
1464#define EMU_SRC_HAMOA_ADC_RIGHT1 0x0201 /* Hamoa ADC Right, 1st or 48kHz only */
1465#define EMU_SRC_HAMOA_ADC_RIGHT2 0x0203 /* Hamoa ADC Right, 2nd or 96kHz */
1466#define EMU_SRC_HAMOA_ADC_RIGHT3 0x0205 /* Hamoa ADC Right, 3rd or 192kHz */
1467#define EMU_SRC_HAMOA_ADC_RIGHT4 0x0207 /* Hamoa ADC Right, 4th or 192kHz */
1468#define EMU_SRC_ALICE_EMU32A 0x0300 /* Alice2 EMU32a 16 outputs. +0 to +0xf */
1469#define EMU_SRC_ALICE_EMU32B 0x0310 /* Alice2 EMU32b 16 outputs. +0 to +0xf */
1470#define EMU_SRC_HANA_ADAT 0x0400 /* Hana ADAT 8 channel in +0 to +7 */
1471#define EMU_SRC_HANA_SPDIF_LEFT1 0x0500 /* Hana SPDIF Left, 1st or 48kHz only */
1472#define EMU_SRC_HANA_SPDIF_LEFT2 0x0502 /* Hana SPDIF Left, 2nd or 96kHz */
1473#define EMU_SRC_HANA_SPDIF_RIGHT1 0x0501 /* Hana SPDIF Right, 1st or 48kHz only */
1474#define EMU_SRC_HANA_SPDIF_RIGHT2 0x0503 /* Hana SPDIF Right, 2nd or 96kHz */
1475
1476/* Additional inputs for 1616(M)/Microdock */
1477/* Microdock S/PDIF Left, 1st or 48kHz only */
1478#define EMU_SRC_MDOCK_SPDIF_LEFT1 0x0112
1479/* Microdock S/PDIF Left, 2nd or 96kHz */
1480#define EMU_SRC_MDOCK_SPDIF_LEFT2 0x0113
1481/* Microdock S/PDIF Right, 1st or 48kHz only */
1482#define EMU_SRC_MDOCK_SPDIF_RIGHT1 0x0116
1483/* Microdock S/PDIF Right, 2nd or 96kHz */
1484#define EMU_SRC_MDOCK_SPDIF_RIGHT2 0x0117
1485/* Microdock ADAT 8 channel in +8 to +f */
1486#define EMU_SRC_MDOCK_ADAT 0x0118
1487
1488/* 0x600 and 0x700 no used */
1489
1490/* ------------------- STRUCTURES -------------------- */
1491
1492enum {
1493    EMU10K1_EFX,
1494    EMU10K1_PCM,
1495    EMU10K1_SYNTH,
1496    EMU10K1_MIDI
1497};
1498
1499struct snd_emu10k1;
1500
1501struct snd_emu10k1_voice {
1502    struct snd_emu10k1 *emu;
1503    int number;
1504    unsigned int use: 1,
1505        pcm: 1,
1506        efx: 1,
1507        synth: 1,
1508        midi: 1;
1509    void (*interrupt)(struct snd_emu10k1 *emu, struct snd_emu10k1_voice *pvoice);
1510
1511    struct snd_emu10k1_pcm *epcm;
1512};
1513
1514enum {
1515    PLAYBACK_EMUVOICE,
1516    PLAYBACK_EFX,
1517    CAPTURE_AC97ADC,
1518    CAPTURE_AC97MIC,
1519    CAPTURE_EFX
1520};
1521
1522struct snd_emu10k1_pcm {
1523    struct snd_emu10k1 *emu;
1524    int type;
1525    struct snd_pcm_substream *substream;
1526    struct snd_emu10k1_voice *voices[NUM_EFX_PLAYBACK];
1527    struct snd_emu10k1_voice *extra;
1528    unsigned short running;
1529    unsigned short first_ptr;
1530    struct snd_util_memblk *memblk;
1531    unsigned int start_addr;
1532    unsigned int ccca_start_addr;
1533    unsigned int capture_ipr; /* interrupt acknowledge mask */
1534    unsigned int capture_inte; /* interrupt enable mask */
1535    unsigned int capture_ba_reg; /* buffer address register */
1536    unsigned int capture_bs_reg; /* buffer size register */
1537    unsigned int capture_idx_reg; /* buffer index register */
1538    unsigned int capture_cr_val; /* control value */
1539    unsigned int capture_cr_val2; /* control value2 (for audigy) */
1540    unsigned int capture_bs_val; /* buffer size value */
1541    unsigned int capture_bufsize; /* buffer size in bytes */
1542};
1543
1544struct snd_emu10k1_pcm_mixer {
1545    /* mono, left, right x 8 sends (4 on emu10k1) */
1546    unsigned char send_routing[3][8];
1547    unsigned char send_volume[3][8];
1548    unsigned short attn[3];
1549    struct snd_emu10k1_pcm *epcm;
1550};
1551
1552#define snd_emu10k1_compose_send_routing(route) \
1553((route[0] | (route[1] << 4) | (route[2] << 8) | (route[3] << 12)) << 16)
1554
1555#define snd_emu10k1_compose_audigy_fxrt1(route) \
1556((unsigned int)route[0] | ((unsigned int)route[1] << 8) | ((unsigned int)route[2] << 16) | ((unsigned int)route[3] << 24))
1557
1558#define snd_emu10k1_compose_audigy_fxrt2(route) \
1559((unsigned int)route[4] | ((unsigned int)route[5] << 8) | ((unsigned int)route[6] << 16) | ((unsigned int)route[7] << 24))
1560
1561struct snd_emu10k1_memblk {
1562    struct snd_util_memblk mem;
1563    /* private part */
1564    int first_page, last_page, pages, mapped_page;
1565    unsigned int map_locked;
1566    struct list_head mapped_link;
1567    struct list_head mapped_order_link;
1568};
1569
1570#define snd_emu10k1_memblk_offset(blk) (((blk)->mapped_page << PAGE_SHIFT) | ((blk)->mem.offset & (PAGE_SIZE - 1)))
1571
1572#define EMU10K1_MAX_TRAM_BLOCKS_PER_CODE 16
1573
1574struct snd_emu10k1_fx8010_ctl {
1575    struct list_head list; /* list link container */
1576    unsigned int vcount;
1577    unsigned int count; /* count of GPR (1..16) */
1578    unsigned short gpr[32]; /* GPR number(s) */
1579    unsigned int value[32];
1580    unsigned int min; /* minimum range */
1581    unsigned int max; /* maximum range */
1582    unsigned int translation; /* translation type (EMU10K1_GPR_TRANSLATION*) */
1583    struct snd_kcontrol *kcontrol;
1584};
1585
1586typedef void (snd_fx8010_irq_handler_t)(struct snd_emu10k1 *emu, void *private_data);
1587
1588struct snd_emu10k1_fx8010_irq {
1589    struct snd_emu10k1_fx8010_irq *next;
1590    snd_fx8010_irq_handler_t *handler;
1591    unsigned short gpr_running;
1592    void *private_data;
1593};
1594
1595struct snd_emu10k1_fx8010_pcm {
1596    unsigned int valid: 1,
1597             opened: 1,
1598             active: 1;
1599    unsigned int channels; /* 16-bit channels count */
1600    unsigned int tram_start; /* initial ring buffer position in TRAM (in samples) */
1601    unsigned int buffer_size; /* count of buffered samples */
1602    unsigned short gpr_size; /* GPR containing size of ring buffer in samples (host) */
1603    unsigned short gpr_ptr; /* GPR containing current pointer in the ring buffer (host = reset, FX8010) */
1604    unsigned short gpr_count; /* GPR containing count of samples between two interrupts (host) */
1605    unsigned short gpr_tmpcount; /* GPR containing current count of samples to interrupt (host = set, FX8010) */
1606    unsigned short gpr_trigger; /* GPR containing trigger (activate) information (host) */
1607    unsigned short gpr_running; /* GPR containing info if PCM is running (FX8010) */
1608    unsigned char etram[32]; /* external TRAM address & data */
1609    struct snd_pcm_indirect pcm_rec;
1610    unsigned int tram_pos;
1611    unsigned int tram_shift;
1612    struct snd_emu10k1_fx8010_irq *irq;
1613};
1614
1615struct snd_emu10k1_fx8010 {
1616    unsigned short fxbus_mask; /* used FX buses (bitmask) */
1617    unsigned short extin_mask; /* used external inputs (bitmask) */
1618    unsigned short extout_mask; /* used external outputs (bitmask) */
1619    unsigned short pad1;
1620    unsigned int itram_size; /* internal TRAM size in samples */
1621    struct snd_dma_buffer etram_pages; /* external TRAM pages and size */
1622    unsigned int dbg; /* FX debugger register */
1623    unsigned char name[128];
1624    int gpr_size; /* size of allocated GPR controls */
1625    int gpr_count; /* count of used kcontrols */
1626    struct list_head gpr_ctl; /* GPR controls */
1627    struct mutex lock;
1628    struct snd_emu10k1_fx8010_pcm pcm[8];
1629    spinlock_t irq_lock;
1630    struct snd_emu10k1_fx8010_irq *irq_handlers;
1631};
1632
1633struct snd_emu10k1_midi {
1634    struct snd_emu10k1 *emu;
1635    struct snd_rawmidi *rmidi;
1636    struct snd_rawmidi_substream *substream_input;
1637    struct snd_rawmidi_substream *substream_output;
1638    unsigned int midi_mode;
1639    spinlock_t input_lock;
1640    spinlock_t output_lock;
1641    spinlock_t open_lock;
1642    int tx_enable, rx_enable;
1643    int port;
1644    int ipr_tx, ipr_rx;
1645    void (*interrupt)(struct snd_emu10k1 *emu, unsigned int status);
1646};
1647
1648enum {
1649    EMU_MODEL_SB,
1650    EMU_MODEL_EMU1010,
1651    EMU_MODEL_EMU1010B,
1652    EMU_MODEL_EMU1616,
1653    EMU_MODEL_EMU0404,
1654};
1655
1656struct snd_emu_chip_details {
1657    u32 vendor;
1658    u32 device;
1659    u32 subsystem;
1660    unsigned char revision;
1661    unsigned char emu10k1_chip; /* Original SB Live. Not SB Live 24bit. */
1662    unsigned char emu10k2_chip; /* Audigy 1 or Audigy 2. */
1663    unsigned char ca0102_chip; /* Audigy 1 or Audigy 2. Not SB Audigy 2 Value. */
1664    unsigned char ca0108_chip; /* Audigy 2 Value */
1665    unsigned char ca_cardbus_chip; /* Audigy 2 ZS Notebook */
1666    unsigned char ca0151_chip; /* P16V */
1667    unsigned char spk71; /* Has 7.1 speakers */
1668    unsigned char sblive51; /* SBLive! 5.1 - extout 0x11 -> center, 0x12 -> lfe */
1669    unsigned char spdif_bug; /* Has Spdif phasing bug */
1670    unsigned char ac97_chip; /* Has an AC97 chip: 1 = mandatory, 2 = optional */
1671    unsigned char ecard; /* APS EEPROM */
1672    unsigned char emu_model; /* EMU model type */
1673    unsigned char spi_dac; /* SPI interface for DAC */
1674    unsigned char i2c_adc; /* I2C interface for ADC */
1675    unsigned char adc_1361t; /* Use Philips 1361T ADC */
1676    unsigned char invert_shared_spdif; /* analog/digital switch inverted */
1677    const char *driver;
1678    const char *name;
1679    const char *id; /* for backward compatibility - can be NULL if not needed */
1680};
1681
1682struct snd_emu1010 {
1683    unsigned int output_source[64];
1684    unsigned int input_source[64];
1685    unsigned int adc_pads; /* bit mask */
1686    unsigned int dac_pads; /* bit mask */
1687    unsigned int internal_clock; /* 44100 or 48000 */
1688    unsigned int optical_in; /* 0:SPDIF, 1:ADAT */
1689    unsigned int optical_out; /* 0:SPDIF, 1:ADAT */
1690    struct task_struct *firmware_thread;
1691};
1692
1693struct snd_emu10k1 {
1694    int irq;
1695
1696    unsigned long port; /* I/O port number */
1697    unsigned int tos_link: 1, /* tos link detected */
1698        rear_ac97: 1, /* rear channels are on AC'97 */
1699        enable_ir: 1;
1700    unsigned int support_tlv :1;
1701    /* Contains profile of card capabilities */
1702    const struct snd_emu_chip_details *card_capabilities;
1703    unsigned int audigy; /* is Audigy? */
1704    unsigned int revision; /* chip revision */
1705    unsigned int serial; /* serial number */
1706    unsigned short model; /* subsystem id */
1707    unsigned int card_type; /* EMU10K1_CARD_* */
1708    unsigned int ecard_ctrl; /* ecard control bits */
1709    unsigned long dma_mask; /* PCI DMA mask */
1710    unsigned int delay_pcm_irq; /* in samples */
1711    int max_cache_pages; /* max memory size / PAGE_SIZE */
1712    struct snd_dma_buffer silent_page; /* silent page */
1713    struct snd_dma_buffer ptb_pages; /* page table pages */
1714    struct snd_dma_device p16v_dma_dev;
1715    struct snd_dma_buffer p16v_buffer;
1716
1717    struct snd_util_memhdr *memhdr; /* page allocation list */
1718    struct snd_emu10k1_memblk *reserved_page; /* reserved page */
1719
1720    struct list_head mapped_link_head;
1721    struct list_head mapped_order_link_head;
1722    void **page_ptr_table;
1723    unsigned long *page_addr_table;
1724    spinlock_t memblk_lock;
1725
1726    unsigned int spdif_bits[3]; /* s/pdif out setup */
1727    unsigned int i2c_capture_source;
1728    u8 i2c_capture_volume[4][2];
1729
1730    struct snd_emu10k1_fx8010 fx8010; /* FX8010 info */
1731    int gpr_base;
1732    
1733    struct snd_ac97 *ac97;
1734
1735    struct pci_dev *pci;
1736    struct snd_card *card;
1737    struct snd_pcm *pcm;
1738    struct snd_pcm *pcm_mic;
1739    struct snd_pcm *pcm_efx;
1740    struct snd_pcm *pcm_multi;
1741    struct snd_pcm *pcm_p16v;
1742
1743    spinlock_t synth_lock;
1744    void *synth;
1745    int (*get_synth_voice)(struct snd_emu10k1 *emu);
1746
1747    spinlock_t reg_lock;
1748    spinlock_t emu_lock;
1749    spinlock_t voice_lock;
1750    spinlock_t spi_lock; /* serialises access to spi port */
1751    spinlock_t i2c_lock; /* serialises access to i2c port */
1752
1753    struct snd_emu10k1_voice voices[NUM_G];
1754    struct snd_emu10k1_voice p16v_voices[4];
1755    struct snd_emu10k1_voice p16v_capture_voice;
1756    int p16v_device_offset;
1757    u32 p16v_capture_source;
1758    u32 p16v_capture_channel;
1759        struct snd_emu1010 emu1010;
1760    struct snd_emu10k1_pcm_mixer pcm_mixer[32];
1761    struct snd_emu10k1_pcm_mixer efx_pcm_mixer[NUM_EFX_PLAYBACK];
1762    struct snd_kcontrol *ctl_send_routing;
1763    struct snd_kcontrol *ctl_send_volume;
1764    struct snd_kcontrol *ctl_attn;
1765    struct snd_kcontrol *ctl_efx_send_routing;
1766    struct snd_kcontrol *ctl_efx_send_volume;
1767    struct snd_kcontrol *ctl_efx_attn;
1768
1769    void (*hwvol_interrupt)(struct snd_emu10k1 *emu, unsigned int status);
1770    void (*capture_interrupt)(struct snd_emu10k1 *emu, unsigned int status);
1771    void (*capture_mic_interrupt)(struct snd_emu10k1 *emu, unsigned int status);
1772    void (*capture_efx_interrupt)(struct snd_emu10k1 *emu, unsigned int status);
1773    void (*spdif_interrupt)(struct snd_emu10k1 *emu, unsigned int status);
1774    void (*dsp_interrupt)(struct snd_emu10k1 *emu);
1775
1776    struct snd_pcm_substream *pcm_capture_substream;
1777    struct snd_pcm_substream *pcm_capture_mic_substream;
1778    struct snd_pcm_substream *pcm_capture_efx_substream;
1779    struct snd_pcm_substream *pcm_playback_efx_substream;
1780
1781    struct snd_timer *timer;
1782
1783    struct snd_emu10k1_midi midi;
1784    struct snd_emu10k1_midi midi2; /* for audigy */
1785
1786    unsigned int efx_voices_mask[2];
1787    unsigned int next_free_voice;
1788
1789    const struct firmware *firmware;
1790    const struct firmware *dock_fw;
1791
1792#ifdef CONFIG_PM_SLEEP
1793    unsigned int *saved_ptr;
1794    unsigned int *saved_gpr;
1795    unsigned int *tram_val_saved;
1796    unsigned int *tram_addr_saved;
1797    unsigned int *saved_icode;
1798    unsigned int *p16v_saved;
1799    unsigned int saved_a_iocfg, saved_hcfg;
1800    bool suspend;
1801#endif
1802
1803};
1804
1805int snd_emu10k1_create(struct snd_card *card,
1806               struct pci_dev *pci,
1807               unsigned short extin_mask,
1808               unsigned short extout_mask,
1809               long max_cache_bytes,
1810               int enable_ir,
1811               uint subsystem,
1812               struct snd_emu10k1 ** remu);
1813
1814int snd_emu10k1_pcm(struct snd_emu10k1 * emu, int device, struct snd_pcm ** rpcm);
1815int snd_emu10k1_pcm_mic(struct snd_emu10k1 * emu, int device, struct snd_pcm ** rpcm);
1816int snd_emu10k1_pcm_efx(struct snd_emu10k1 * emu, int device, struct snd_pcm ** rpcm);
1817int snd_p16v_pcm(struct snd_emu10k1 * emu, int device, struct snd_pcm ** rpcm);
1818int snd_p16v_free(struct snd_emu10k1 * emu);
1819int snd_p16v_mixer(struct snd_emu10k1 * emu);
1820int snd_emu10k1_pcm_multi(struct snd_emu10k1 * emu, int device, struct snd_pcm ** rpcm);
1821int snd_emu10k1_fx8010_pcm(struct snd_emu10k1 * emu, int device, struct snd_pcm ** rpcm);
1822int snd_emu10k1_mixer(struct snd_emu10k1 * emu, int pcm_device, int multi_device);
1823int snd_emu10k1_timer(struct snd_emu10k1 * emu, int device);
1824int snd_emu10k1_fx8010_new(struct snd_emu10k1 *emu, int device, struct snd_hwdep ** rhwdep);
1825
1826irqreturn_t snd_emu10k1_interrupt(int irq, void *dev_id);
1827
1828void snd_emu10k1_voice_init(struct snd_emu10k1 * emu, int voice);
1829int snd_emu10k1_init_efx(struct snd_emu10k1 *emu);
1830void snd_emu10k1_free_efx(struct snd_emu10k1 *emu);
1831int snd_emu10k1_fx8010_tram_setup(struct snd_emu10k1 *emu, u32 size);
1832int snd_emu10k1_done(struct snd_emu10k1 * emu);
1833
1834/* I/O functions */
1835unsigned int snd_emu10k1_ptr_read(struct snd_emu10k1 * emu, unsigned int reg, unsigned int chn);
1836void snd_emu10k1_ptr_write(struct snd_emu10k1 *emu, unsigned int reg, unsigned int chn, unsigned int data);
1837unsigned int snd_emu10k1_ptr20_read(struct snd_emu10k1 * emu, unsigned int reg, unsigned int chn);
1838void snd_emu10k1_ptr20_write(struct snd_emu10k1 *emu, unsigned int reg, unsigned int chn, unsigned int data);
1839int snd_emu10k1_spi_write(struct snd_emu10k1 * emu, unsigned int data);
1840int snd_emu10k1_i2c_write(struct snd_emu10k1 *emu, u32 reg, u32 value);
1841int snd_emu1010_fpga_write(struct snd_emu10k1 * emu, u32 reg, u32 value);
1842int snd_emu1010_fpga_read(struct snd_emu10k1 * emu, u32 reg, u32 *value);
1843int snd_emu1010_fpga_link_dst_src_write(struct snd_emu10k1 * emu, u32 dst, u32 src);
1844unsigned int snd_emu10k1_efx_read(struct snd_emu10k1 *emu, unsigned int pc);
1845void snd_emu10k1_intr_enable(struct snd_emu10k1 *emu, unsigned int intrenb);
1846void snd_emu10k1_intr_disable(struct snd_emu10k1 *emu, unsigned int intrenb);
1847void snd_emu10k1_voice_intr_enable(struct snd_emu10k1 *emu, unsigned int voicenum);
1848void snd_emu10k1_voice_intr_disable(struct snd_emu10k1 *emu, unsigned int voicenum);
1849void snd_emu10k1_voice_intr_ack(struct snd_emu10k1 *emu, unsigned int voicenum);
1850void snd_emu10k1_voice_half_loop_intr_enable(struct snd_emu10k1 *emu, unsigned int voicenum);
1851void snd_emu10k1_voice_half_loop_intr_disable(struct snd_emu10k1 *emu, unsigned int voicenum);
1852void snd_emu10k1_voice_half_loop_intr_ack(struct snd_emu10k1 *emu, unsigned int voicenum);
1853void snd_emu10k1_voice_set_loop_stop(struct snd_emu10k1 *emu, unsigned int voicenum);
1854void snd_emu10k1_voice_clear_loop_stop(struct snd_emu10k1 *emu, unsigned int voicenum);
1855void snd_emu10k1_wait(struct snd_emu10k1 *emu, unsigned int wait);
1856static inline unsigned int snd_emu10k1_wc(struct snd_emu10k1 *emu) { return (inl(emu->port + WC) >> 6) & 0xfffff; }
1857unsigned short snd_emu10k1_ac97_read(struct snd_ac97 *ac97, unsigned short reg);
1858void snd_emu10k1_ac97_write(struct snd_ac97 *ac97, unsigned short reg, unsigned short data);
1859unsigned int snd_emu10k1_rate_to_pitch(unsigned int rate);
1860
1861#ifdef CONFIG_PM_SLEEP
1862void snd_emu10k1_suspend_regs(struct snd_emu10k1 *emu);
1863void snd_emu10k1_resume_init(struct snd_emu10k1 *emu);
1864void snd_emu10k1_resume_regs(struct snd_emu10k1 *emu);
1865int snd_emu10k1_efx_alloc_pm_buffer(struct snd_emu10k1 *emu);
1866void snd_emu10k1_efx_free_pm_buffer(struct snd_emu10k1 *emu);
1867void snd_emu10k1_efx_suspend(struct snd_emu10k1 *emu);
1868void snd_emu10k1_efx_resume(struct snd_emu10k1 *emu);
1869int snd_p16v_alloc_pm_buffer(struct snd_emu10k1 *emu);
1870void snd_p16v_free_pm_buffer(struct snd_emu10k1 *emu);
1871void snd_p16v_suspend(struct snd_emu10k1 *emu);
1872void snd_p16v_resume(struct snd_emu10k1 *emu);
1873#endif
1874
1875/* memory allocation */
1876struct snd_util_memblk *snd_emu10k1_alloc_pages(struct snd_emu10k1 *emu, struct snd_pcm_substream *substream);
1877int snd_emu10k1_free_pages(struct snd_emu10k1 *emu, struct snd_util_memblk *blk);
1878struct snd_util_memblk *snd_emu10k1_synth_alloc(struct snd_emu10k1 *emu, unsigned int size);
1879int snd_emu10k1_synth_free(struct snd_emu10k1 *emu, struct snd_util_memblk *blk);
1880int snd_emu10k1_synth_bzero(struct snd_emu10k1 *emu, struct snd_util_memblk *blk, int offset, int size);
1881int snd_emu10k1_synth_copy_from_user(struct snd_emu10k1 *emu, struct snd_util_memblk *blk, int offset, const char __user *data, int size);
1882int snd_emu10k1_memblk_map(struct snd_emu10k1 *emu, struct snd_emu10k1_memblk *blk);
1883
1884/* voice allocation */
1885int snd_emu10k1_voice_alloc(struct snd_emu10k1 *emu, int type, int pair, struct snd_emu10k1_voice **rvoice);
1886int snd_emu10k1_voice_free(struct snd_emu10k1 *emu, struct snd_emu10k1_voice *pvoice);
1887
1888/* MIDI uart */
1889int snd_emu10k1_midi(struct snd_emu10k1 * emu);
1890int snd_emu10k1_audigy_midi(struct snd_emu10k1 * emu);
1891
1892/* proc interface */
1893int snd_emu10k1_proc_init(struct snd_emu10k1 * emu);
1894
1895/* fx8010 irq handler */
1896int snd_emu10k1_fx8010_register_irq_handler(struct snd_emu10k1 *emu,
1897                        snd_fx8010_irq_handler_t *handler,
1898                        unsigned char gpr_running,
1899                        void *private_data,
1900                        struct snd_emu10k1_fx8010_irq **r_irq);
1901int snd_emu10k1_fx8010_unregister_irq_handler(struct snd_emu10k1 *emu,
1902                          struct snd_emu10k1_fx8010_irq *irq);
1903
1904#endif /* __SOUND_EMU10K1_H */
1905

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