Root/Documentation/pinctrl.txt

1PINCTRL (PIN CONTROL) subsystem
2This document outlines the pin control subsystem in Linux
3
4This subsystem deals with:
5
6- Enumerating and naming controllable pins
7
8- Multiplexing of pins, pads, fingers (etc) see below for details
9
10- Configuration of pins, pads, fingers (etc), such as software-controlled
11  biasing and driving mode specific pins, such as pull-up/down, open drain,
12  load capacitance etc.
13
14Top-level interface
15===================
16
17Definition of PIN CONTROLLER:
18
19- A pin controller is a piece of hardware, usually a set of registers, that
20  can control PINs. It may be able to multiplex, bias, set load capacitance,
21  set drive strength, etc. for individual pins or groups of pins.
22
23Definition of PIN:
24
25- PINS are equal to pads, fingers, balls or whatever packaging input or
26  output line you want to control and these are denoted by unsigned integers
27  in the range 0..maxpin. This numberspace is local to each PIN CONTROLLER, so
28  there may be several such number spaces in a system. This pin space may
29  be sparse - i.e. there may be gaps in the space with numbers where no
30  pin exists.
31
32When a PIN CONTROLLER is instantiated, it will register a descriptor to the
33pin control framework, and this descriptor contains an array of pin descriptors
34describing the pins handled by this specific pin controller.
35
36Here is an example of a PGA (Pin Grid Array) chip seen from underneath:
37
38        A B C D E F G H
39
40   8 o o o o o o o o
41
42   7 o o o o o o o o
43
44   6 o o o o o o o o
45
46   5 o o o o o o o o
47
48   4 o o o o o o o o
49
50   3 o o o o o o o o
51
52   2 o o o o o o o o
53
54   1 o o o o o o o o
55
56To register a pin controller and name all the pins on this package we can do
57this in our driver:
58
59#include <linux/pinctrl/pinctrl.h>
60
61const struct pinctrl_pin_desc foo_pins[] = {
62      PINCTRL_PIN(0, "A8"),
63      PINCTRL_PIN(1, "B8"),
64      PINCTRL_PIN(2, "C8"),
65      ...
66      PINCTRL_PIN(61, "F1"),
67      PINCTRL_PIN(62, "G1"),
68      PINCTRL_PIN(63, "H1"),
69};
70
71static struct pinctrl_desc foo_desc = {
72    .name = "foo",
73    .pins = foo_pins,
74    .npins = ARRAY_SIZE(foo_pins),
75    .maxpin = 63,
76    .owner = THIS_MODULE,
77};
78
79int __init foo_probe(void)
80{
81    struct pinctrl_dev *pctl;
82
83    pctl = pinctrl_register(&foo_desc, <PARENT>, NULL);
84    if (!pctl)
85        pr_err("could not register foo pin driver\n");
86}
87
88To enable the pinctrl subsystem and the subgroups for PINMUX and PINCONF and
89selected drivers, you need to select them from your machine's Kconfig entry,
90since these are so tightly integrated with the machines they are used on.
91See for example arch/arm/mach-u300/Kconfig for an example.
92
93Pins usually have fancier names than this. You can find these in the datasheet
94for your chip. Notice that the core pinctrl.h file provides a fancy macro
95called PINCTRL_PIN() to create the struct entries. As you can see I enumerated
96the pins from 0 in the upper left corner to 63 in the lower right corner.
97This enumeration was arbitrarily chosen, in practice you need to think
98through your numbering system so that it matches the layout of registers
99and such things in your driver, or the code may become complicated. You must
100also consider matching of offsets to the GPIO ranges that may be handled by
101the pin controller.
102
103For a padring with 467 pads, as opposed to actual pins, I used an enumeration
104like this, walking around the edge of the chip, which seems to be industry
105standard too (all these pads had names, too):
106
107
108     0 ..... 104
109   466 105
110     . .
111     . .
112   358 224
113    357 .... 225
114
115
116Pin groups
117==========
118
119Many controllers need to deal with groups of pins, so the pin controller
120subsystem has a mechanism for enumerating groups of pins and retrieving the
121actual enumerated pins that are part of a certain group.
122
123For example, say that we have a group of pins dealing with an SPI interface
124on { 0, 8, 16, 24 }, and a group of pins dealing with an I2C interface on pins
125on { 24, 25 }.
126
127These two groups are presented to the pin control subsystem by implementing
128some generic pinctrl_ops like this:
129
130#include <linux/pinctrl/pinctrl.h>
131
132struct foo_group {
133    const char *name;
134    const unsigned int *pins;
135    const unsigned num_pins;
136};
137
138static const unsigned int spi0_pins[] = { 0, 8, 16, 24 };
139static const unsigned int i2c0_pins[] = { 24, 25 };
140
141static const struct foo_group foo_groups[] = {
142    {
143        .name = "spi0_grp",
144        .pins = spi0_pins,
145        .num_pins = ARRAY_SIZE(spi0_pins),
146    },
147    {
148        .name = "i2c0_grp",
149        .pins = i2c0_pins,
150        .num_pins = ARRAY_SIZE(i2c0_pins),
151    },
152};
153
154
155static int foo_get_groups_count(struct pinctrl_dev *pctldev)
156{
157    return ARRAY_SIZE(foo_groups);
158}
159
160static const char *foo_get_group_name(struct pinctrl_dev *pctldev,
161                       unsigned selector)
162{
163    return foo_groups[selector].name;
164}
165
166static int foo_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
167                   unsigned ** const pins,
168                   unsigned * const num_pins)
169{
170    *pins = (unsigned *) foo_groups[selector].pins;
171    *num_pins = foo_groups[selector].num_pins;
172    return 0;
173}
174
175static struct pinctrl_ops foo_pctrl_ops = {
176    .get_groups_count = foo_get_groups_count,
177    .get_group_name = foo_get_group_name,
178    .get_group_pins = foo_get_group_pins,
179};
180
181
182static struct pinctrl_desc foo_desc = {
183       ...
184       .pctlops = &foo_pctrl_ops,
185};
186
187The pin control subsystem will call the .get_groups_count() function to
188determine the total number of legal selectors, then it will call the other functions
189to retrieve the name and pins of the group. Maintaining the data structure of
190the groups is up to the driver, this is just a simple example - in practice you
191may need more entries in your group structure, for example specific register
192ranges associated with each group and so on.
193
194
195Pin configuration
196=================
197
198Pins can sometimes be software-configured in various ways, mostly related
199to their electronic properties when used as inputs or outputs. For example you
200may be able to make an output pin high impedance, or "tristate" meaning it is
201effectively disconnected. You may be able to connect an input pin to VDD or GND
202using a certain resistor value - pull up and pull down - so that the pin has a
203stable value when nothing is driving the rail it is connected to, or when it's
204unconnected.
205
206Pin configuration can be programmed by adding configuration entries into the
207mapping table; see section "Board/machine configuration" below.
208
209The format and meaning of the configuration parameter, PLATFORM_X_PULL_UP
210above, is entirely defined by the pin controller driver.
211
212The pin configuration driver implements callbacks for changing pin
213configuration in the pin controller ops like this:
214
215#include <linux/pinctrl/pinctrl.h>
216#include <linux/pinctrl/pinconf.h>
217#include "platform_x_pindefs.h"
218
219static int foo_pin_config_get(struct pinctrl_dev *pctldev,
220            unsigned offset,
221            unsigned long *config)
222{
223    struct my_conftype conf;
224
225    ... Find setting for pin @ offset ...
226
227    *config = (unsigned long) conf;
228}
229
230static int foo_pin_config_set(struct pinctrl_dev *pctldev,
231            unsigned offset,
232            unsigned long config)
233{
234    struct my_conftype *conf = (struct my_conftype *) config;
235
236    switch (conf) {
237        case PLATFORM_X_PULL_UP:
238        ...
239        }
240    }
241}
242
243static int foo_pin_config_group_get (struct pinctrl_dev *pctldev,
244            unsigned selector,
245            unsigned long *config)
246{
247    ...
248}
249
250static int foo_pin_config_group_set (struct pinctrl_dev *pctldev,
251            unsigned selector,
252            unsigned long config)
253{
254    ...
255}
256
257static struct pinconf_ops foo_pconf_ops = {
258    .pin_config_get = foo_pin_config_get,
259    .pin_config_set = foo_pin_config_set,
260    .pin_config_group_get = foo_pin_config_group_get,
261    .pin_config_group_set = foo_pin_config_group_set,
262};
263
264/* Pin config operations are handled by some pin controller */
265static struct pinctrl_desc foo_desc = {
266    ...
267    .confops = &foo_pconf_ops,
268};
269
270Since some controllers have special logic for handling entire groups of pins
271they can exploit the special whole-group pin control function. The
272pin_config_group_set() callback is allowed to return the error code -EAGAIN,
273for groups it does not want to handle, or if it just wants to do some
274group-level handling and then fall through to iterate over all pins, in which
275case each individual pin will be treated by separate pin_config_set() calls as
276well.
277
278
279Interaction with the GPIO subsystem
280===================================
281
282The GPIO drivers may want to perform operations of various types on the same
283physical pins that are also registered as pin controller pins.
284
285First and foremost, the two subsystems can be used as completely orthogonal,
286see the section named "pin control requests from drivers" and
287"drivers needing both pin control and GPIOs" below for details. But in some
288situations a cross-subsystem mapping between pins and GPIOs is needed.
289
290Since the pin controller subsystem have its pinspace local to the pin
291controller we need a mapping so that the pin control subsystem can figure out
292which pin controller handles control of a certain GPIO pin. Since a single
293pin controller may be muxing several GPIO ranges (typically SoCs that have
294one set of pins, but internally several GPIO silicon blocks, each modelled as
295a struct gpio_chip) any number of GPIO ranges can be added to a pin controller
296instance like this:
297
298struct gpio_chip chip_a;
299struct gpio_chip chip_b;
300
301static struct pinctrl_gpio_range gpio_range_a = {
302    .name = "chip a",
303    .id = 0,
304    .base = 32,
305    .pin_base = 32,
306    .npins = 16,
307    .gc = &chip_a;
308};
309
310static struct pinctrl_gpio_range gpio_range_b = {
311    .name = "chip b",
312    .id = 0,
313    .base = 48,
314    .pin_base = 64,
315    .npins = 8,
316    .gc = &chip_b;
317};
318
319{
320    struct pinctrl_dev *pctl;
321    ...
322    pinctrl_add_gpio_range(pctl, &gpio_range_a);
323    pinctrl_add_gpio_range(pctl, &gpio_range_b);
324}
325
326So this complex system has one pin controller handling two different
327GPIO chips. "chip a" has 16 pins and "chip b" has 8 pins. The "chip a" and
328"chip b" have different .pin_base, which means a start pin number of the
329GPIO range.
330
331The GPIO range of "chip a" starts from the GPIO base of 32 and actual
332pin range also starts from 32. However "chip b" has different starting
333offset for the GPIO range and pin range. The GPIO range of "chip b" starts
334from GPIO number 48, while the pin range of "chip b" starts from 64.
335
336We can convert a gpio number to actual pin number using this "pin_base".
337They are mapped in the global GPIO pin space at:
338
339chip a:
340 - GPIO range : [32 .. 47]
341 - pin range : [32 .. 47]
342chip b:
343 - GPIO range : [48 .. 55]
344 - pin range : [64 .. 71]
345
346The above examples assume the mapping between the GPIOs and pins is
347linear. If the mapping is sparse or haphazard, an array of arbitrary pin
348numbers can be encoded in the range like this:
349
350static const unsigned range_pins[] = { 14, 1, 22, 17, 10, 8, 6, 2 };
351
352static struct pinctrl_gpio_range gpio_range = {
353    .name = "chip",
354    .id = 0,
355    .base = 32,
356    .pins = &range_pins,
357    .npins = ARRAY_SIZE(range_pins),
358    .gc = &chip;
359};
360
361In this case the pin_base property will be ignored. If the name of a pin
362group is known, the pins and npins elements of the above structure can be
363initialised using the function pinctrl_get_group_pins(), e.g. for pin
364group "foo":
365
366pinctrl_get_group_pins(pctl, "foo", &gpio_range.pins, &gpio_range.npins);
367
368When GPIO-specific functions in the pin control subsystem are called, these
369ranges will be used to look up the appropriate pin controller by inspecting
370and matching the pin to the pin ranges across all controllers. When a
371pin controller handling the matching range is found, GPIO-specific functions
372will be called on that specific pin controller.
373
374For all functionalities dealing with pin biasing, pin muxing etc, the pin
375controller subsystem will look up the corresponding pin number from the passed
376in gpio number, and use the range's internals to retrieve a pin number. After
377that, the subsystem passes it on to the pin control driver, so the driver
378will get a pin number into its handled number range. Further it is also passed
379the range ID value, so that the pin controller knows which range it should
380deal with.
381
382Calling pinctrl_add_gpio_range from pinctrl driver is DEPRECATED. Please see
383section 2.1 of Documentation/devicetree/bindings/gpio/gpio.txt on how to bind
384pinctrl and gpio drivers.
385
386
387PINMUX interfaces
388=================
389
390These calls use the pinmux_* naming prefix. No other calls should use that
391prefix.
392
393
394What is pinmuxing?
395==================
396
397PINMUX, also known as padmux, ballmux, alternate functions or mission modes
398is a way for chip vendors producing some kind of electrical packages to use
399a certain physical pin (ball, pad, finger, etc) for multiple mutually exclusive
400functions, depending on the application. By "application" in this context
401we usually mean a way of soldering or wiring the package into an electronic
402system, even though the framework makes it possible to also change the function
403at runtime.
404
405Here is an example of a PGA (Pin Grid Array) chip seen from underneath:
406
407        A B C D E F G H
408      +---+
409   8 | o | o o o o o o o
410      | |
411   7 | o | o o o o o o o
412      | |
413   6 | o | o o o o o o o
414      +---+---+
415   5 | o | o | o o o o o o
416      +---+---+ +---+
417   4 o o o o o o | o | o
418                              | |
419   3 o o o o o o | o | o
420                              | |
421   2 o o o o o o | o | o
422      +-------+-------+-------+---+---+
423   1 | o o | o o | o o | o | o |
424      +-------+-------+-------+---+---+
425
426This is not tetris. The game to think of is chess. Not all PGA/BGA packages
427are chessboard-like, big ones have "holes" in some arrangement according to
428different design patterns, but we're using this as a simple example. Of the
429pins you see some will be taken by things like a few VCC and GND to feed power
430to the chip, and quite a few will be taken by large ports like an external
431memory interface. The remaining pins will often be subject to pin multiplexing.
432
433The example 8x8 PGA package above will have pin numbers 0 through 63 assigned
434to its physical pins. It will name the pins { A1, A2, A3 ... H6, H7, H8 } using
435pinctrl_register_pins() and a suitable data set as shown earlier.
436
437In this 8x8 BGA package the pins { A8, A7, A6, A5 } can be used as an SPI port
438(these are four pins: CLK, RXD, TXD, FRM). In that case, pin B5 can be used as
439some general-purpose GPIO pin. However, in another setting, pins { A5, B5 } can
440be used as an I2C port (these are just two pins: SCL, SDA). Needless to say,
441we cannot use the SPI port and I2C port at the same time. However in the inside
442of the package the silicon performing the SPI logic can alternatively be routed
443out on pins { G4, G3, G2, G1 }.
444
445On the bottom row at { A1, B1, C1, D1, E1, F1, G1, H1 } we have something
446special - it's an external MMC bus that can be 2, 4 or 8 bits wide, and it will
447consume 2, 4 or 8 pins respectively, so either { A1, B1 } are taken or
448{ A1, B1, C1, D1 } or all of them. If we use all 8 bits, we cannot use the SPI
449port on pins { G4, G3, G2, G1 } of course.
450
451This way the silicon blocks present inside the chip can be multiplexed "muxed"
452out on different pin ranges. Often contemporary SoC (systems on chip) will
453contain several I2C, SPI, SDIO/MMC, etc silicon blocks that can be routed to
454different pins by pinmux settings.
455
456Since general-purpose I/O pins (GPIO) are typically always in shortage, it is
457common to be able to use almost any pin as a GPIO pin if it is not currently
458in use by some other I/O port.
459
460
461Pinmux conventions
462==================
463
464The purpose of the pinmux functionality in the pin controller subsystem is to
465abstract and provide pinmux settings to the devices you choose to instantiate
466in your machine configuration. It is inspired by the clk, GPIO and regulator
467subsystems, so devices will request their mux setting, but it's also possible
468to request a single pin for e.g. GPIO.
469
470Definitions:
471
472- FUNCTIONS can be switched in and out by a driver residing with the pin
473  control subsystem in the drivers/pinctrl/* directory of the kernel. The
474  pin control driver knows the possible functions. In the example above you can
475  identify three pinmux functions, one for spi, one for i2c and one for mmc.
476
477- FUNCTIONS are assumed to be enumerable from zero in a one-dimensional array.
478  In this case the array could be something like: { spi0, i2c0, mmc0 }
479  for the three available functions.
480
481- FUNCTIONS have PIN GROUPS as defined on the generic level - so a certain
482  function is *always* associated with a certain set of pin groups, could
483  be just a single one, but could also be many. In the example above the
484  function i2c is associated with the pins { A5, B5 }, enumerated as
485  { 24, 25 } in the controller pin space.
486
487  The Function spi is associated with pin groups { A8, A7, A6, A5 }
488  and { G4, G3, G2, G1 }, which are enumerated as { 0, 8, 16, 24 } and
489  { 38, 46, 54, 62 } respectively.
490
491  Group names must be unique per pin controller, no two groups on the same
492  controller may have the same name.
493
494- The combination of a FUNCTION and a PIN GROUP determine a certain function
495  for a certain set of pins. The knowledge of the functions and pin groups
496  and their machine-specific particulars are kept inside the pinmux driver,
497  from the outside only the enumerators are known, and the driver core can:
498
499  - Request the name of a function with a certain selector (>= 0)
500  - A list of groups associated with a certain function
501  - Request that a certain group in that list to be activated for a certain
502    function
503
504  As already described above, pin groups are in turn self-descriptive, so
505  the core will retrieve the actual pin range in a certain group from the
506  driver.
507
508- FUNCTIONS and GROUPS on a certain PIN CONTROLLER are MAPPED to a certain
509  device by the board file, device tree or similar machine setup configuration
510  mechanism, similar to how regulators are connected to devices, usually by
511  name. Defining a pin controller, function and group thus uniquely identify
512  the set of pins to be used by a certain device. (If only one possible group
513  of pins is available for the function, no group name need to be supplied -
514  the core will simply select the first and only group available.)
515
516  In the example case we can define that this particular machine shall
517  use device spi0 with pinmux function fspi0 group gspi0 and i2c0 on function
518  fi2c0 group gi2c0, on the primary pin controller, we get mappings
519  like these:
520
521  {
522    {"map-spi0", spi0, pinctrl0, fspi0, gspi0},
523    {"map-i2c0", i2c0, pinctrl0, fi2c0, gi2c0}
524  }
525
526  Every map must be assigned a state name, pin controller, device and
527  function. The group is not compulsory - if it is omitted the first group
528  presented by the driver as applicable for the function will be selected,
529  which is useful for simple cases.
530
531  It is possible to map several groups to the same combination of device,
532  pin controller and function. This is for cases where a certain function on
533  a certain pin controller may use different sets of pins in different
534  configurations.
535
536- PINS for a certain FUNCTION using a certain PIN GROUP on a certain
537  PIN CONTROLLER are provided on a first-come first-serve basis, so if some
538  other device mux setting or GPIO pin request has already taken your physical
539  pin, you will be denied the use of it. To get (activate) a new setting, the
540  old one has to be put (deactivated) first.
541
542Sometimes the documentation and hardware registers will be oriented around
543pads (or "fingers") rather than pins - these are the soldering surfaces on the
544silicon inside the package, and may or may not match the actual number of
545pins/balls underneath the capsule. Pick some enumeration that makes sense to
546you. Define enumerators only for the pins you can control if that makes sense.
547
548Assumptions:
549
550We assume that the number of possible function maps to pin groups is limited by
551the hardware. I.e. we assume that there is no system where any function can be
552mapped to any pin, like in a phone exchange. So the available pin groups for
553a certain function will be limited to a few choices (say up to eight or so),
554not hundreds or any amount of choices. This is the characteristic we have found
555by inspecting available pinmux hardware, and a necessary assumption since we
556expect pinmux drivers to present *all* possible function vs pin group mappings
557to the subsystem.
558
559
560Pinmux drivers
561==============
562
563The pinmux core takes care of preventing conflicts on pins and calling
564the pin controller driver to execute different settings.
565
566It is the responsibility of the pinmux driver to impose further restrictions
567(say for example infer electronic limitations due to load, etc.) to determine
568whether or not the requested function can actually be allowed, and in case it
569is possible to perform the requested mux setting, poke the hardware so that
570this happens.
571
572Pinmux drivers are required to supply a few callback functions, some are
573optional. Usually the enable() and disable() functions are implemented,
574writing values into some certain registers to activate a certain mux setting
575for a certain pin.
576
577A simple driver for the above example will work by setting bits 0, 1, 2, 3 or 4
578into some register named MUX to select a certain function with a certain
579group of pins would work something like this:
580
581#include <linux/pinctrl/pinctrl.h>
582#include <linux/pinctrl/pinmux.h>
583
584struct foo_group {
585    const char *name;
586    const unsigned int *pins;
587    const unsigned num_pins;
588};
589
590static const unsigned spi0_0_pins[] = { 0, 8, 16, 24 };
591static const unsigned spi0_1_pins[] = { 38, 46, 54, 62 };
592static const unsigned i2c0_pins[] = { 24, 25 };
593static const unsigned mmc0_1_pins[] = { 56, 57 };
594static const unsigned mmc0_2_pins[] = { 58, 59 };
595static const unsigned mmc0_3_pins[] = { 60, 61, 62, 63 };
596
597static const struct foo_group foo_groups[] = {
598    {
599        .name = "spi0_0_grp",
600        .pins = spi0_0_pins,
601        .num_pins = ARRAY_SIZE(spi0_0_pins),
602    },
603    {
604        .name = "spi0_1_grp",
605        .pins = spi0_1_pins,
606        .num_pins = ARRAY_SIZE(spi0_1_pins),
607    },
608    {
609        .name = "i2c0_grp",
610        .pins = i2c0_pins,
611        .num_pins = ARRAY_SIZE(i2c0_pins),
612    },
613    {
614        .name = "mmc0_1_grp",
615        .pins = mmc0_1_pins,
616        .num_pins = ARRAY_SIZE(mmc0_1_pins),
617    },
618    {
619        .name = "mmc0_2_grp",
620        .pins = mmc0_2_pins,
621        .num_pins = ARRAY_SIZE(mmc0_2_pins),
622    },
623    {
624        .name = "mmc0_3_grp",
625        .pins = mmc0_3_pins,
626        .num_pins = ARRAY_SIZE(mmc0_3_pins),
627    },
628};
629
630
631static int foo_get_groups_count(struct pinctrl_dev *pctldev)
632{
633    return ARRAY_SIZE(foo_groups);
634}
635
636static const char *foo_get_group_name(struct pinctrl_dev *pctldev,
637                       unsigned selector)
638{
639    return foo_groups[selector].name;
640}
641
642static int foo_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
643                   unsigned ** const pins,
644                   unsigned * const num_pins)
645{
646    *pins = (unsigned *) foo_groups[selector].pins;
647    *num_pins = foo_groups[selector].num_pins;
648    return 0;
649}
650
651static struct pinctrl_ops foo_pctrl_ops = {
652    .get_groups_count = foo_get_groups_count,
653    .get_group_name = foo_get_group_name,
654    .get_group_pins = foo_get_group_pins,
655};
656
657struct foo_pmx_func {
658    const char *name;
659    const char * const *groups;
660    const unsigned num_groups;
661};
662
663static const char * const spi0_groups[] = { "spi0_0_grp", "spi0_1_grp" };
664static const char * const i2c0_groups[] = { "i2c0_grp" };
665static const char * const mmc0_groups[] = { "mmc0_1_grp", "mmc0_2_grp",
666                    "mmc0_3_grp" };
667
668static const struct foo_pmx_func foo_functions[] = {
669    {
670        .name = "spi0",
671        .groups = spi0_groups,
672        .num_groups = ARRAY_SIZE(spi0_groups),
673    },
674    {
675        .name = "i2c0",
676        .groups = i2c0_groups,
677        .num_groups = ARRAY_SIZE(i2c0_groups),
678    },
679    {
680        .name = "mmc0",
681        .groups = mmc0_groups,
682        .num_groups = ARRAY_SIZE(mmc0_groups),
683    },
684};
685
686int foo_get_functions_count(struct pinctrl_dev *pctldev)
687{
688    return ARRAY_SIZE(foo_functions);
689}
690
691const char *foo_get_fname(struct pinctrl_dev *pctldev, unsigned selector)
692{
693    return foo_functions[selector].name;
694}
695
696static int foo_get_groups(struct pinctrl_dev *pctldev, unsigned selector,
697              const char * const **groups,
698              unsigned * const num_groups)
699{
700    *groups = foo_functions[selector].groups;
701    *num_groups = foo_functions[selector].num_groups;
702    return 0;
703}
704
705int foo_enable(struct pinctrl_dev *pctldev, unsigned selector,
706        unsigned group)
707{
708    u8 regbit = (1 << selector + group);
709
710    writeb((readb(MUX)|regbit), MUX)
711    return 0;
712}
713
714void foo_disable(struct pinctrl_dev *pctldev, unsigned selector,
715        unsigned group)
716{
717    u8 regbit = (1 << selector + group);
718
719    writeb((readb(MUX) & ~(regbit)), MUX)
720    return 0;
721}
722
723struct pinmux_ops foo_pmxops = {
724    .get_functions_count = foo_get_functions_count,
725    .get_function_name = foo_get_fname,
726    .get_function_groups = foo_get_groups,
727    .enable = foo_enable,
728    .disable = foo_disable,
729};
730
731/* Pinmux operations are handled by some pin controller */
732static struct pinctrl_desc foo_desc = {
733    ...
734    .pctlops = &foo_pctrl_ops,
735    .pmxops = &foo_pmxops,
736};
737
738In the example activating muxing 0 and 1 at the same time setting bits
7390 and 1, uses one pin in common so they would collide.
740
741The beauty of the pinmux subsystem is that since it keeps track of all
742pins and who is using them, it will already have denied an impossible
743request like that, so the driver does not need to worry about such
744things - when it gets a selector passed in, the pinmux subsystem makes
745sure no other device or GPIO assignment is already using the selected
746pins. Thus bits 0 and 1 in the control register will never be set at the
747same time.
748
749All the above functions are mandatory to implement for a pinmux driver.
750
751
752Pin control interaction with the GPIO subsystem
753===============================================
754
755Note that the following implies that the use case is to use a certain pin
756from the Linux kernel using the API in <linux/gpio.h> with gpio_request()
757and similar functions. There are cases where you may be using something
758that your datasheet calls "GPIO mode", but actually is just an electrical
759configuration for a certain device. See the section below named
760"GPIO mode pitfalls" for more details on this scenario.
761
762The public pinmux API contains two functions named pinctrl_request_gpio()
763and pinctrl_free_gpio(). These two functions shall *ONLY* be called from
764gpiolib-based drivers as part of their gpio_request() and
765gpio_free() semantics. Likewise the pinctrl_gpio_direction_[input|output]
766shall only be called from within respective gpio_direction_[input|output]
767gpiolib implementation.
768
769NOTE that platforms and individual drivers shall *NOT* request GPIO pins to be
770controlled e.g. muxed in. Instead, implement a proper gpiolib driver and have
771that driver request proper muxing and other control for its pins.
772
773The function list could become long, especially if you can convert every
774individual pin into a GPIO pin independent of any other pins, and then try
775the approach to define every pin as a function.
776
777In this case, the function array would become 64 entries for each GPIO
778setting and then the device functions.
779
780For this reason there are two functions a pin control driver can implement
781to enable only GPIO on an individual pin: .gpio_request_enable() and
782.gpio_disable_free().
783
784This function will pass in the affected GPIO range identified by the pin
785controller core, so you know which GPIO pins are being affected by the request
786operation.
787
788If your driver needs to have an indication from the framework of whether the
789GPIO pin shall be used for input or output you can implement the
790.gpio_set_direction() function. As described this shall be called from the
791gpiolib driver and the affected GPIO range, pin offset and desired direction
792will be passed along to this function.
793
794Alternatively to using these special functions, it is fully allowed to use
795named functions for each GPIO pin, the pinctrl_request_gpio() will attempt to
796obtain the function "gpioN" where "N" is the global GPIO pin number if no
797special GPIO-handler is registered.
798
799
800GPIO mode pitfalls
801==================
802
803Due to the naming conventions used by hardware engineers, where "GPIO"
804is taken to mean different things than what the kernel does, the developer
805may be confused by a datasheet talking about a pin being possible to set
806into "GPIO mode". It appears that what hardware engineers mean with
807"GPIO mode" is not necessarily the use case that is implied in the kernel
808interface <linux/gpio.h>: a pin that you grab from kernel code and then
809either listen for input or drive high/low to assert/deassert some
810external line.
811
812Rather hardware engineers think that "GPIO mode" means that you can
813software-control a few electrical properties of the pin that you would
814not be able to control if the pin was in some other mode, such as muxed in
815for a device.
816
817The GPIO portions of a pin and its relation to a certain pin controller
818configuration and muxing logic can be constructed in several ways. Here
819are two examples:
820
821(A)
822                       pin config
823                       logic regs
824                       | +- SPI
825     Physical pins --- pad --- pinmux -+- I2C
826                               | +- mmc
827                               | +- GPIO
828                               pin
829                               multiplex
830                               logic regs
831
832Here some electrical properties of the pin can be configured no matter
833whether the pin is used for GPIO or not. If you multiplex a GPIO onto a
834pin, you can also drive it high/low from "GPIO" registers.
835Alternatively, the pin can be controlled by a certain peripheral, while
836still applying desired pin config properties. GPIO functionality is thus
837orthogonal to any other device using the pin.
838
839In this arrangement the registers for the GPIO portions of the pin controller,
840or the registers for the GPIO hardware module are likely to reside in a
841separate memory range only intended for GPIO driving, and the register
842range dealing with pin config and pin multiplexing get placed into a
843different memory range and a separate section of the data sheet.
844
845(B)
846
847                       pin config
848                       logic regs
849                       | +- SPI
850     Physical pins --- pad --- pinmux -+- I2C
851                       | | +- mmc
852                       | |
853                       GPIO pin
854                               multiplex
855                               logic regs
856
857In this arrangement, the GPIO functionality can always be enabled, such that
858e.g. a GPIO input can be used to "spy" on the SPI/I2C/MMC signal while it is
859pulsed out. It is likely possible to disrupt the traffic on the pin by doing
860wrong things on the GPIO block, as it is never really disconnected. It is
861possible that the GPIO, pin config and pin multiplex registers are placed into
862the same memory range and the same section of the data sheet, although that
863need not be the case.
864
865From a kernel point of view, however, these are different aspects of the
866hardware and shall be put into different subsystems:
867
868- Registers (or fields within registers) that control electrical
869  properties of the pin such as biasing and drive strength should be
870  exposed through the pinctrl subsystem, as "pin configuration" settings.
871
872- Registers (or fields within registers) that control muxing of signals
873  from various other HW blocks (e.g. I2C, MMC, or GPIO) onto pins should
874  be exposed through the pinctrl subsystem, as mux functions.
875
876- Registers (or fields within registers) that control GPIO functionality
877  such as setting a GPIO's output value, reading a GPIO's input value, or
878  setting GPIO pin direction should be exposed through the GPIO subsystem,
879  and if they also support interrupt capabilities, through the irqchip
880  abstraction.
881
882Depending on the exact HW register design, some functions exposed by the
883GPIO subsystem may call into the pinctrl subsystem in order to
884co-ordinate register settings across HW modules. In particular, this may
885be needed for HW with separate GPIO and pin controller HW modules, where
886e.g. GPIO direction is determined by a register in the pin controller HW
887module rather than the GPIO HW module.
888
889Electrical properties of the pin such as biasing and drive strength
890may be placed at some pin-specific register in all cases or as part
891of the GPIO register in case (B) especially. This doesn't mean that such
892properties necessarily pertain to what the Linux kernel calls "GPIO".
893
894Example: a pin is usually muxed in to be used as a UART TX line. But during
895system sleep, we need to put this pin into "GPIO mode" and ground it.
896
897If you make a 1-to-1 map to the GPIO subsystem for this pin, you may start
898to think that you need to come up with something really complex, that the
899pin shall be used for UART TX and GPIO at the same time, that you will grab
900a pin control handle and set it to a certain state to enable UART TX to be
901muxed in, then twist it over to GPIO mode and use gpio_direction_output()
902to drive it low during sleep, then mux it over to UART TX again when you
903wake up and maybe even gpio_request/gpio_free as part of this cycle. This
904all gets very complicated.
905
906The solution is to not think that what the datasheet calls "GPIO mode"
907has to be handled by the <linux/gpio.h> interface. Instead view this as
908a certain pin config setting. Look in e.g. <linux/pinctrl/pinconf-generic.h>
909and you find this in the documentation:
910
911  PIN_CONFIG_OUTPUT: this will configure the pin in output, use argument
912     1 to indicate high level, argument 0 to indicate low level.
913
914So it is perfectly possible to push a pin into "GPIO mode" and drive the
915line low as part of the usual pin control map. So for example your UART
916driver may look like this:
917
918#include <linux/pinctrl/consumer.h>
919
920struct pinctrl *pinctrl;
921struct pinctrl_state *pins_default;
922struct pinctrl_state *pins_sleep;
923
924pins_default = pinctrl_lookup_state(uap->pinctrl, PINCTRL_STATE_DEFAULT);
925pins_sleep = pinctrl_lookup_state(uap->pinctrl, PINCTRL_STATE_SLEEP);
926
927/* Normal mode */
928retval = pinctrl_select_state(pinctrl, pins_default);
929/* Sleep mode */
930retval = pinctrl_select_state(pinctrl, pins_sleep);
931
932And your machine configuration may look like this:
933--------------------------------------------------
934
935static unsigned long uart_default_mode[] = {
936    PIN_CONF_PACKED(PIN_CONFIG_DRIVE_PUSH_PULL, 0),
937};
938
939static unsigned long uart_sleep_mode[] = {
940    PIN_CONF_PACKED(PIN_CONFIG_OUTPUT, 0),
941};
942
943static struct pinctrl_map pinmap[] __initdata = {
944    PIN_MAP_MUX_GROUP("uart", PINCTRL_STATE_DEFAULT, "pinctrl-foo",
945                      "u0_group", "u0"),
946    PIN_MAP_CONFIGS_PIN("uart", PINCTRL_STATE_DEFAULT, "pinctrl-foo",
947                        "UART_TX_PIN", uart_default_mode),
948    PIN_MAP_MUX_GROUP("uart", PINCTRL_STATE_SLEEP, "pinctrl-foo",
949                      "u0_group", "gpio-mode"),
950    PIN_MAP_CONFIGS_PIN("uart", PINCTRL_STATE_SLEEP, "pinctrl-foo",
951                        "UART_TX_PIN", uart_sleep_mode),
952};
953
954foo_init(void) {
955    pinctrl_register_mappings(pinmap, ARRAY_SIZE(pinmap));
956}
957
958Here the pins we want to control are in the "u0_group" and there is some
959function called "u0" that can be enabled on this group of pins, and then
960everything is UART business as usual. But there is also some function
961named "gpio-mode" that can be mapped onto the same pins to move them into
962GPIO mode.
963
964This will give the desired effect without any bogus interaction with the
965GPIO subsystem. It is just an electrical configuration used by that device
966when going to sleep, it might imply that the pin is set into something the
967datasheet calls "GPIO mode", but that is not the point: it is still used
968by that UART device to control the pins that pertain to that very UART
969driver, putting them into modes needed by the UART. GPIO in the Linux
970kernel sense are just some 1-bit line, and is a different use case.
971
972How the registers are poked to attain the push or pull, and output low
973configuration and the muxing of the "u0" or "gpio-mode" group onto these
974pins is a question for the driver.
975
976Some datasheets will be more helpful and refer to the "GPIO mode" as
977"low power mode" rather than anything to do with GPIO. This often means
978the same thing electrically speaking, but in this latter case the
979software engineers will usually quickly identify that this is some
980specific muxing or configuration rather than anything related to the GPIO
981API.
982
983
984Board/machine configuration
985==================================
986
987Boards and machines define how a certain complete running system is put
988together, including how GPIOs and devices are muxed, how regulators are
989constrained and how the clock tree looks. Of course pinmux settings are also
990part of this.
991
992A pin controller configuration for a machine looks pretty much like a simple
993regulator configuration, so for the example array above we want to enable i2c
994and spi on the second function mapping:
995
996#include <linux/pinctrl/machine.h>
997
998static const struct pinctrl_map mapping[] __initconst = {
999    {
1000        .dev_name = "foo-spi.0",
1001        .name = PINCTRL_STATE_DEFAULT,
1002        .type = PIN_MAP_TYPE_MUX_GROUP,
1003        .ctrl_dev_name = "pinctrl-foo",
1004        .data.mux.function = "spi0",
1005    },
1006    {
1007        .dev_name = "foo-i2c.0",
1008        .name = PINCTRL_STATE_DEFAULT,
1009        .type = PIN_MAP_TYPE_MUX_GROUP,
1010        .ctrl_dev_name = "pinctrl-foo",
1011        .data.mux.function = "i2c0",
1012    },
1013    {
1014        .dev_name = "foo-mmc.0",
1015        .name = PINCTRL_STATE_DEFAULT,
1016        .type = PIN_MAP_TYPE_MUX_GROUP,
1017        .ctrl_dev_name = "pinctrl-foo",
1018        .data.mux.function = "mmc0",
1019    },
1020};
1021
1022The dev_name here matches to the unique device name that can be used to look
1023up the device struct (just like with clockdev or regulators). The function name
1024must match a function provided by the pinmux driver handling this pin range.
1025
1026As you can see we may have several pin controllers on the system and thus
1027we need to specify which one of them contains the functions we wish to map.
1028
1029You register this pinmux mapping to the pinmux subsystem by simply:
1030
1031       ret = pinctrl_register_mappings(mapping, ARRAY_SIZE(mapping));
1032
1033Since the above construct is pretty common there is a helper macro to make
1034it even more compact which assumes you want to use pinctrl-foo and position
10350 for mapping, for example:
1036
1037static struct pinctrl_map mapping[] __initdata = {
1038    PIN_MAP_MUX_GROUP("foo-i2c.o", PINCTRL_STATE_DEFAULT, "pinctrl-foo", NULL, "i2c0"),
1039};
1040
1041The mapping table may also contain pin configuration entries. It's common for
1042each pin/group to have a number of configuration entries that affect it, so
1043the table entries for configuration reference an array of config parameters
1044and values. An example using the convenience macros is shown below:
1045
1046static unsigned long i2c_grp_configs[] = {
1047    FOO_PIN_DRIVEN,
1048    FOO_PIN_PULLUP,
1049};
1050
1051static unsigned long i2c_pin_configs[] = {
1052    FOO_OPEN_COLLECTOR,
1053    FOO_SLEW_RATE_SLOW,
1054};
1055
1056static struct pinctrl_map mapping[] __initdata = {
1057    PIN_MAP_MUX_GROUP("foo-i2c.0", PINCTRL_STATE_DEFAULT, "pinctrl-foo", "i2c0", "i2c0"),
1058    PIN_MAP_CONFIGS_GROUP("foo-i2c.0", PINCTRL_STATE_DEFAULT, "pinctrl-foo", "i2c0", i2c_grp_configs),
1059    PIN_MAP_CONFIGS_PIN("foo-i2c.0", PINCTRL_STATE_DEFAULT, "pinctrl-foo", "i2c0scl", i2c_pin_configs),
1060    PIN_MAP_CONFIGS_PIN("foo-i2c.0", PINCTRL_STATE_DEFAULT, "pinctrl-foo", "i2c0sda", i2c_pin_configs),
1061};
1062
1063Finally, some devices expect the mapping table to contain certain specific
1064named states. When running on hardware that doesn't need any pin controller
1065configuration, the mapping table must still contain those named states, in
1066order to explicitly indicate that the states were provided and intended to
1067be empty. Table entry macro PIN_MAP_DUMMY_STATE serves the purpose of defining
1068a named state without causing any pin controller to be programmed:
1069
1070static struct pinctrl_map mapping[] __initdata = {
1071    PIN_MAP_DUMMY_STATE("foo-i2c.0", PINCTRL_STATE_DEFAULT),
1072};
1073
1074
1075Complex mappings
1076================
1077
1078As it is possible to map a function to different groups of pins an optional
1079.group can be specified like this:
1080
1081...
1082{
1083    .dev_name = "foo-spi.0",
1084    .name = "spi0-pos-A",
1085    .type = PIN_MAP_TYPE_MUX_GROUP,
1086    .ctrl_dev_name = "pinctrl-foo",
1087    .function = "spi0",
1088    .group = "spi0_0_grp",
1089},
1090{
1091    .dev_name = "foo-spi.0",
1092    .name = "spi0-pos-B",
1093    .type = PIN_MAP_TYPE_MUX_GROUP,
1094    .ctrl_dev_name = "pinctrl-foo",
1095    .function = "spi0",
1096    .group = "spi0_1_grp",
1097},
1098...
1099
1100This example mapping is used to switch between two positions for spi0 at
1101runtime, as described further below under the heading "Runtime pinmuxing".
1102
1103Further it is possible for one named state to affect the muxing of several
1104groups of pins, say for example in the mmc0 example above, where you can
1105additively expand the mmc0 bus from 2 to 4 to 8 pins. If we want to use all
1106three groups for a total of 2+2+4 = 8 pins (for an 8-bit MMC bus as is the
1107case), we define a mapping like this:
1108
1109...
1110{
1111    .dev_name = "foo-mmc.0",
1112    .name = "2bit"
1113    .type = PIN_MAP_TYPE_MUX_GROUP,
1114    .ctrl_dev_name = "pinctrl-foo",
1115    .function = "mmc0",
1116    .group = "mmc0_1_grp",
1117},
1118{
1119    .dev_name = "foo-mmc.0",
1120    .name = "4bit"
1121    .type = PIN_MAP_TYPE_MUX_GROUP,
1122    .ctrl_dev_name = "pinctrl-foo",
1123    .function = "mmc0",
1124    .group = "mmc0_1_grp",
1125},
1126{
1127    .dev_name = "foo-mmc.0",
1128    .name = "4bit"
1129    .type = PIN_MAP_TYPE_MUX_GROUP,
1130    .ctrl_dev_name = "pinctrl-foo",
1131    .function = "mmc0",
1132    .group = "mmc0_2_grp",
1133},
1134{
1135    .dev_name = "foo-mmc.0",
1136    .name = "8bit"
1137    .type = PIN_MAP_TYPE_MUX_GROUP,
1138    .ctrl_dev_name = "pinctrl-foo",
1139    .function = "mmc0",
1140    .group = "mmc0_1_grp",
1141},
1142{
1143    .dev_name = "foo-mmc.0",
1144    .name = "8bit"
1145    .type = PIN_MAP_TYPE_MUX_GROUP,
1146    .ctrl_dev_name = "pinctrl-foo",
1147    .function = "mmc0",
1148    .group = "mmc0_2_grp",
1149},
1150{
1151    .dev_name = "foo-mmc.0",
1152    .name = "8bit"
1153    .type = PIN_MAP_TYPE_MUX_GROUP,
1154    .ctrl_dev_name = "pinctrl-foo",
1155    .function = "mmc0",
1156    .group = "mmc0_3_grp",
1157},
1158...
1159
1160The result of grabbing this mapping from the device with something like
1161this (see next paragraph):
1162
1163    p = devm_pinctrl_get(dev);
1164    s = pinctrl_lookup_state(p, "8bit");
1165    ret = pinctrl_select_state(p, s);
1166
1167or more simply:
1168
1169    p = devm_pinctrl_get_select(dev, "8bit");
1170
1171Will be that you activate all the three bottom records in the mapping at
1172once. Since they share the same name, pin controller device, function and
1173device, and since we allow multiple groups to match to a single device, they
1174all get selected, and they all get enabled and disable simultaneously by the
1175pinmux core.
1176
1177
1178Pin control requests from drivers
1179=================================
1180
1181When a device driver is about to probe the device core will automatically
1182attempt to issue pinctrl_get_select_default() on these devices.
1183This way driver writers do not need to add any of the boilerplate code
1184of the type found below. However when doing fine-grained state selection
1185and not using the "default" state, you may have to do some device driver
1186handling of the pinctrl handles and states.
1187
1188So if you just want to put the pins for a certain device into the default
1189state and be done with it, there is nothing you need to do besides
1190providing the proper mapping table. The device core will take care of
1191the rest.
1192
1193Generally it is discouraged to let individual drivers get and enable pin
1194control. So if possible, handle the pin control in platform code or some other
1195place where you have access to all the affected struct device * pointers. In
1196some cases where a driver needs to e.g. switch between different mux mappings
1197at runtime this is not possible.
1198
1199A typical case is if a driver needs to switch bias of pins from normal
1200operation and going to sleep, moving from the PINCTRL_STATE_DEFAULT to
1201PINCTRL_STATE_SLEEP at runtime, re-biasing or even re-muxing pins to save
1202current in sleep mode.
1203
1204A driver may request a certain control state to be activated, usually just the
1205default state like this:
1206
1207#include <linux/pinctrl/consumer.h>
1208
1209struct foo_state {
1210       struct pinctrl *p;
1211       struct pinctrl_state *s;
1212       ...
1213};
1214
1215foo_probe()
1216{
1217    /* Allocate a state holder named "foo" etc */
1218    struct foo_state *foo = ...;
1219
1220    foo->p = devm_pinctrl_get(&device);
1221    if (IS_ERR(foo->p)) {
1222        /* FIXME: clean up "foo" here */
1223        return PTR_ERR(foo->p);
1224    }
1225
1226    foo->s = pinctrl_lookup_state(foo->p, PINCTRL_STATE_DEFAULT);
1227    if (IS_ERR(foo->s)) {
1228        /* FIXME: clean up "foo" here */
1229        return PTR_ERR(s);
1230    }
1231
1232    ret = pinctrl_select_state(foo->s);
1233    if (ret < 0) {
1234        /* FIXME: clean up "foo" here */
1235        return ret;
1236    }
1237}
1238
1239This get/lookup/select/put sequence can just as well be handled by bus drivers
1240if you don't want each and every driver to handle it and you know the
1241arrangement on your bus.
1242
1243The semantics of the pinctrl APIs are:
1244
1245- pinctrl_get() is called in process context to obtain a handle to all pinctrl
1246  information for a given client device. It will allocate a struct from the
1247  kernel memory to hold the pinmux state. All mapping table parsing or similar
1248  slow operations take place within this API.
1249
1250- devm_pinctrl_get() is a variant of pinctrl_get() that causes pinctrl_put()
1251  to be called automatically on the retrieved pointer when the associated
1252  device is removed. It is recommended to use this function over plain
1253  pinctrl_get().
1254
1255- pinctrl_lookup_state() is called in process context to obtain a handle to a
1256  specific state for a client device. This operation may be slow, too.
1257
1258- pinctrl_select_state() programs pin controller hardware according to the
1259  definition of the state as given by the mapping table. In theory, this is a
1260  fast-path operation, since it only involved blasting some register settings
1261  into hardware. However, note that some pin controllers may have their
1262  registers on a slow/IRQ-based bus, so client devices should not assume they
1263  can call pinctrl_select_state() from non-blocking contexts.
1264
1265- pinctrl_put() frees all information associated with a pinctrl handle.
1266
1267- devm_pinctrl_put() is a variant of pinctrl_put() that may be used to
1268  explicitly destroy a pinctrl object returned by devm_pinctrl_get().
1269  However, use of this function will be rare, due to the automatic cleanup
1270  that will occur even without calling it.
1271
1272  pinctrl_get() must be paired with a plain pinctrl_put().
1273  pinctrl_get() may not be paired with devm_pinctrl_put().
1274  devm_pinctrl_get() can optionally be paired with devm_pinctrl_put().
1275  devm_pinctrl_get() may not be paired with plain pinctrl_put().
1276
1277Usually the pin control core handled the get/put pair and call out to the
1278device drivers bookkeeping operations, like checking available functions and
1279the associated pins, whereas the enable/disable pass on to the pin controller
1280driver which takes care of activating and/or deactivating the mux setting by
1281quickly poking some registers.
1282
1283The pins are allocated for your device when you issue the devm_pinctrl_get()
1284call, after this you should be able to see this in the debugfs listing of all
1285pins.
1286
1287NOTE: the pinctrl system will return -EPROBE_DEFER if it cannot find the
1288requested pinctrl handles, for example if the pinctrl driver has not yet
1289registered. Thus make sure that the error path in your driver gracefully
1290cleans up and is ready to retry the probing later in the startup process.
1291
1292
1293Drivers needing both pin control and GPIOs
1294==========================================
1295
1296Again, it is discouraged to let drivers lookup and select pin control states
1297themselves, but again sometimes this is unavoidable.
1298
1299So say that your driver is fetching its resources like this:
1300
1301#include <linux/pinctrl/consumer.h>
1302#include <linux/gpio.h>
1303
1304struct pinctrl *pinctrl;
1305int gpio;
1306
1307pinctrl = devm_pinctrl_get_select_default(&dev);
1308gpio = devm_gpio_request(&dev, 14, "foo");
1309
1310Here we first request a certain pin state and then request GPIO 14 to be
1311used. If you're using the subsystems orthogonally like this, you should
1312nominally always get your pinctrl handle and select the desired pinctrl
1313state BEFORE requesting the GPIO. This is a semantic convention to avoid
1314situations that can be electrically unpleasant, you will certainly want to
1315mux in and bias pins in a certain way before the GPIO subsystems starts to
1316deal with them.
1317
1318The above can be hidden: using the device core, the pinctrl core may be
1319setting up the config and muxing for the pins right before the device is
1320probing, nevertheless orthogonal to the GPIO subsystem.
1321
1322But there are also situations where it makes sense for the GPIO subsystem
1323to communicate directly with the pinctrl subsystem, using the latter as a
1324back-end. This is when the GPIO driver may call out to the functions
1325described in the section "Pin control interaction with the GPIO subsystem"
1326above. This only involves per-pin multiplexing, and will be completely
1327hidden behind the gpio_*() function namespace. In this case, the driver
1328need not interact with the pin control subsystem at all.
1329
1330If a pin control driver and a GPIO driver is dealing with the same pins
1331and the use cases involve multiplexing, you MUST implement the pin controller
1332as a back-end for the GPIO driver like this, unless your hardware design
1333is such that the GPIO controller can override the pin controller's
1334multiplexing state through hardware without the need to interact with the
1335pin control system.
1336
1337
1338System pin control hogging
1339==========================
1340
1341Pin control map entries can be hogged by the core when the pin controller
1342is registered. This means that the core will attempt to call pinctrl_get(),
1343lookup_state() and select_state() on it immediately after the pin control
1344device has been registered.
1345
1346This occurs for mapping table entries where the client device name is equal
1347to the pin controller device name, and the state name is PINCTRL_STATE_DEFAULT.
1348
1349{
1350    .dev_name = "pinctrl-foo",
1351    .name = PINCTRL_STATE_DEFAULT,
1352    .type = PIN_MAP_TYPE_MUX_GROUP,
1353    .ctrl_dev_name = "pinctrl-foo",
1354    .function = "power_func",
1355},
1356
1357Since it may be common to request the core to hog a few always-applicable
1358mux settings on the primary pin controller, there is a convenience macro for
1359this:
1360
1361PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-foo", NULL /* group */, "power_func")
1362
1363This gives the exact same result as the above construction.
1364
1365
1366Runtime pinmuxing
1367=================
1368
1369It is possible to mux a certain function in and out at runtime, say to move
1370an SPI port from one set of pins to another set of pins. Say for example for
1371spi0 in the example above, we expose two different groups of pins for the same
1372function, but with different named in the mapping as described under
1373"Advanced mapping" above. So that for an SPI device, we have two states named
1374"pos-A" and "pos-B".
1375
1376This snippet first muxes the function in the pins defined by group A, enables
1377it, disables and releases it, and muxes it in on the pins defined by group B:
1378
1379#include <linux/pinctrl/consumer.h>
1380
1381struct pinctrl *p;
1382struct pinctrl_state *s1, *s2;
1383
1384foo_probe()
1385{
1386    /* Setup */
1387    p = devm_pinctrl_get(&device);
1388    if (IS_ERR(p))
1389        ...
1390
1391    s1 = pinctrl_lookup_state(foo->p, "pos-A");
1392    if (IS_ERR(s1))
1393        ...
1394
1395    s2 = pinctrl_lookup_state(foo->p, "pos-B");
1396    if (IS_ERR(s2))
1397        ...
1398}
1399
1400foo_switch()
1401{
1402    /* Enable on position A */
1403    ret = pinctrl_select_state(s1);
1404    if (ret < 0)
1405        ...
1406
1407    ...
1408
1409    /* Enable on position B */
1410    ret = pinctrl_select_state(s2);
1411    if (ret < 0)
1412        ...
1413
1414    ...
1415}
1416
1417The above has to be done from process context. The reservation of the pins
1418will be done when the state is activated, so in effect one specific pin
1419can be used by different functions at different times on a running system.
1420

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