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1 | /* |
2 | * Sonics Silicon Backplane |
3 | * Bus scanning |
4 | * |
5 | * Copyright (C) 2005-2007 Michael Buesch <m@bues.ch> |
6 | * Copyright (C) 2005 Martin Langer <martin-langer@gmx.de> |
7 | * Copyright (C) 2005 Stefano Brivio <st3@riseup.net> |
8 | * Copyright (C) 2005 Danny van Dyk <kugelfang@gentoo.org> |
9 | * Copyright (C) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch> |
10 | * Copyright (C) 2006 Broadcom Corporation. |
11 | * |
12 | * Licensed under the GNU/GPL. See COPYING for details. |
13 | */ |
14 | |
15 | #include <linux/ssb/ssb.h> |
16 | #include <linux/ssb/ssb_regs.h> |
17 | #include <linux/pci.h> |
18 | #include <linux/io.h> |
19 | |
20 | #include <pcmcia/cistpl.h> |
21 | #include <pcmcia/ds.h> |
22 | |
23 | #include "ssb_private.h" |
24 | |
25 | |
26 | const char *ssb_core_name(u16 coreid) |
27 | { |
28 | switch (coreid) { |
29 | case SSB_DEV_CHIPCOMMON: |
30 | return "ChipCommon"; |
31 | case SSB_DEV_ILINE20: |
32 | return "ILine 20"; |
33 | case SSB_DEV_SDRAM: |
34 | return "SDRAM"; |
35 | case SSB_DEV_PCI: |
36 | return "PCI"; |
37 | case SSB_DEV_MIPS: |
38 | return "MIPS"; |
39 | case SSB_DEV_ETHERNET: |
40 | return "Fast Ethernet"; |
41 | case SSB_DEV_V90: |
42 | return "V90"; |
43 | case SSB_DEV_USB11_HOSTDEV: |
44 | return "USB 1.1 Hostdev"; |
45 | case SSB_DEV_ADSL: |
46 | return "ADSL"; |
47 | case SSB_DEV_ILINE100: |
48 | return "ILine 100"; |
49 | case SSB_DEV_IPSEC: |
50 | return "IPSEC"; |
51 | case SSB_DEV_PCMCIA: |
52 | return "PCMCIA"; |
53 | case SSB_DEV_INTERNAL_MEM: |
54 | return "Internal Memory"; |
55 | case SSB_DEV_MEMC_SDRAM: |
56 | return "MEMC SDRAM"; |
57 | case SSB_DEV_EXTIF: |
58 | return "EXTIF"; |
59 | case SSB_DEV_80211: |
60 | return "IEEE 802.11"; |
61 | case SSB_DEV_MIPS_3302: |
62 | return "MIPS 3302"; |
63 | case SSB_DEV_USB11_HOST: |
64 | return "USB 1.1 Host"; |
65 | case SSB_DEV_USB11_DEV: |
66 | return "USB 1.1 Device"; |
67 | case SSB_DEV_USB20_HOST: |
68 | return "USB 2.0 Host"; |
69 | case SSB_DEV_USB20_DEV: |
70 | return "USB 2.0 Device"; |
71 | case SSB_DEV_SDIO_HOST: |
72 | return "SDIO Host"; |
73 | case SSB_DEV_ROBOSWITCH: |
74 | return "Roboswitch"; |
75 | case SSB_DEV_PARA_ATA: |
76 | return "PATA"; |
77 | case SSB_DEV_SATA_XORDMA: |
78 | return "SATA XOR-DMA"; |
79 | case SSB_DEV_ETHERNET_GBIT: |
80 | return "GBit Ethernet"; |
81 | case SSB_DEV_PCIE: |
82 | return "PCI-E"; |
83 | case SSB_DEV_MIMO_PHY: |
84 | return "MIMO PHY"; |
85 | case SSB_DEV_SRAM_CTRLR: |
86 | return "SRAM Controller"; |
87 | case SSB_DEV_MINI_MACPHY: |
88 | return "Mini MACPHY"; |
89 | case SSB_DEV_ARM_1176: |
90 | return "ARM 1176"; |
91 | case SSB_DEV_ARM_7TDMI: |
92 | return "ARM 7TDMI"; |
93 | } |
94 | return "UNKNOWN"; |
95 | } |
96 | |
97 | static u16 pcidev_to_chipid(struct pci_dev *pci_dev) |
98 | { |
99 | u16 chipid_fallback = 0; |
100 | |
101 | switch (pci_dev->device) { |
102 | case 0x4301: |
103 | chipid_fallback = 0x4301; |
104 | break; |
105 | case 0x4305 ... 0x4307: |
106 | chipid_fallback = 0x4307; |
107 | break; |
108 | case 0x4403: |
109 | chipid_fallback = 0x4402; |
110 | break; |
111 | case 0x4610 ... 0x4615: |
112 | chipid_fallback = 0x4610; |
113 | break; |
114 | case 0x4710 ... 0x4715: |
115 | chipid_fallback = 0x4710; |
116 | break; |
117 | case 0x4320 ... 0x4325: |
118 | chipid_fallback = 0x4309; |
119 | break; |
120 | case PCI_DEVICE_ID_BCM4401: |
121 | case PCI_DEVICE_ID_BCM4401B0: |
122 | case PCI_DEVICE_ID_BCM4401B1: |
123 | chipid_fallback = 0x4401; |
124 | break; |
125 | default: |
126 | ssb_printk(KERN_ERR PFX |
127 | "PCI-ID not in fallback list\n"); |
128 | } |
129 | |
130 | return chipid_fallback; |
131 | } |
132 | |
133 | static u8 chipid_to_nrcores(u16 chipid) |
134 | { |
135 | switch (chipid) { |
136 | case 0x5365: |
137 | return 7; |
138 | case 0x4306: |
139 | return 6; |
140 | case 0x4310: |
141 | return 8; |
142 | case 0x4307: |
143 | case 0x4301: |
144 | return 5; |
145 | case 0x4401: |
146 | case 0x4402: |
147 | return 3; |
148 | case 0x4710: |
149 | case 0x4610: |
150 | case 0x4704: |
151 | return 9; |
152 | default: |
153 | ssb_printk(KERN_ERR PFX |
154 | "CHIPID not in nrcores fallback list\n"); |
155 | } |
156 | |
157 | return 1; |
158 | } |
159 | |
160 | static u32 scan_read32(struct ssb_bus *bus, u8 current_coreidx, |
161 | u16 offset) |
162 | { |
163 | u32 lo, hi; |
164 | |
165 | switch (bus->bustype) { |
166 | case SSB_BUSTYPE_SSB: |
167 | offset += current_coreidx * SSB_CORE_SIZE; |
168 | break; |
169 | case SSB_BUSTYPE_PCI: |
170 | break; |
171 | case SSB_BUSTYPE_PCMCIA: |
172 | if (offset >= 0x800) { |
173 | ssb_pcmcia_switch_segment(bus, 1); |
174 | offset -= 0x800; |
175 | } else |
176 | ssb_pcmcia_switch_segment(bus, 0); |
177 | lo = readw(bus->mmio + offset); |
178 | hi = readw(bus->mmio + offset + 2); |
179 | return lo | (hi << 16); |
180 | case SSB_BUSTYPE_SDIO: |
181 | offset += current_coreidx * SSB_CORE_SIZE; |
182 | return ssb_sdio_scan_read32(bus, offset); |
183 | } |
184 | return readl(bus->mmio + offset); |
185 | } |
186 | |
187 | static int scan_switchcore(struct ssb_bus *bus, u8 coreidx) |
188 | { |
189 | switch (bus->bustype) { |
190 | case SSB_BUSTYPE_SSB: |
191 | break; |
192 | case SSB_BUSTYPE_PCI: |
193 | return ssb_pci_switch_coreidx(bus, coreidx); |
194 | case SSB_BUSTYPE_PCMCIA: |
195 | return ssb_pcmcia_switch_coreidx(bus, coreidx); |
196 | case SSB_BUSTYPE_SDIO: |
197 | return ssb_sdio_scan_switch_coreidx(bus, coreidx); |
198 | } |
199 | return 0; |
200 | } |
201 | |
202 | void ssb_iounmap(struct ssb_bus *bus) |
203 | { |
204 | switch (bus->bustype) { |
205 | case SSB_BUSTYPE_SSB: |
206 | case SSB_BUSTYPE_PCMCIA: |
207 | iounmap(bus->mmio); |
208 | break; |
209 | case SSB_BUSTYPE_PCI: |
210 | #ifdef CONFIG_SSB_PCIHOST |
211 | pci_iounmap(bus->host_pci, bus->mmio); |
212 | #else |
213 | SSB_BUG_ON(1); /* Can't reach this code. */ |
214 | #endif |
215 | break; |
216 | case SSB_BUSTYPE_SDIO: |
217 | break; |
218 | } |
219 | bus->mmio = NULL; |
220 | bus->mapped_device = NULL; |
221 | } |
222 | |
223 | static void __iomem *ssb_ioremap(struct ssb_bus *bus, |
224 | unsigned long baseaddr) |
225 | { |
226 | void __iomem *mmio = NULL; |
227 | |
228 | switch (bus->bustype) { |
229 | case SSB_BUSTYPE_SSB: |
230 | /* Only map the first core for now. */ |
231 | /* fallthrough... */ |
232 | case SSB_BUSTYPE_PCMCIA: |
233 | mmio = ioremap(baseaddr, SSB_CORE_SIZE); |
234 | break; |
235 | case SSB_BUSTYPE_PCI: |
236 | #ifdef CONFIG_SSB_PCIHOST |
237 | mmio = pci_iomap(bus->host_pci, 0, ~0UL); |
238 | #else |
239 | SSB_BUG_ON(1); /* Can't reach this code. */ |
240 | #endif |
241 | break; |
242 | case SSB_BUSTYPE_SDIO: |
243 | /* Nothing to ioremap in the SDIO case, just fake it */ |
244 | mmio = (void __iomem *)baseaddr; |
245 | break; |
246 | } |
247 | |
248 | return mmio; |
249 | } |
250 | |
251 | static int we_support_multiple_80211_cores(struct ssb_bus *bus) |
252 | { |
253 | /* More than one 802.11 core is only supported by special chips. |
254 | * There are chips with two 802.11 cores, but with dangling |
255 | * pins on the second core. Be careful and reject them here. |
256 | */ |
257 | |
258 | #ifdef CONFIG_SSB_PCIHOST |
259 | if (bus->bustype == SSB_BUSTYPE_PCI) { |
260 | if (bus->host_pci->vendor == PCI_VENDOR_ID_BROADCOM && |
261 | ((bus->host_pci->device == 0x4313) || |
262 | (bus->host_pci->device == 0x431A) || |
263 | (bus->host_pci->device == 0x4321) || |
264 | (bus->host_pci->device == 0x4324))) |
265 | return 1; |
266 | } |
267 | #endif /* CONFIG_SSB_PCIHOST */ |
268 | return 0; |
269 | } |
270 | |
271 | int ssb_bus_scan(struct ssb_bus *bus, |
272 | unsigned long baseaddr) |
273 | { |
274 | int err = -ENOMEM; |
275 | void __iomem *mmio; |
276 | u32 idhi, cc, rev, tmp; |
277 | int dev_i, i; |
278 | struct ssb_device *dev; |
279 | int nr_80211_cores = 0; |
280 | |
281 | mmio = ssb_ioremap(bus, baseaddr); |
282 | if (!mmio) |
283 | goto out; |
284 | bus->mmio = mmio; |
285 | |
286 | err = scan_switchcore(bus, 0); /* Switch to first core */ |
287 | if (err) |
288 | goto err_unmap; |
289 | |
290 | idhi = scan_read32(bus, 0, SSB_IDHIGH); |
291 | cc = (idhi & SSB_IDHIGH_CC) >> SSB_IDHIGH_CC_SHIFT; |
292 | rev = (idhi & SSB_IDHIGH_RCLO); |
293 | rev |= (idhi & SSB_IDHIGH_RCHI) >> SSB_IDHIGH_RCHI_SHIFT; |
294 | |
295 | bus->nr_devices = 0; |
296 | if (cc == SSB_DEV_CHIPCOMMON) { |
297 | tmp = scan_read32(bus, 0, SSB_CHIPCO_CHIPID); |
298 | |
299 | bus->chip_id = (tmp & SSB_CHIPCO_IDMASK); |
300 | bus->chip_rev = (tmp & SSB_CHIPCO_REVMASK) >> |
301 | SSB_CHIPCO_REVSHIFT; |
302 | bus->chip_package = (tmp & SSB_CHIPCO_PACKMASK) >> |
303 | SSB_CHIPCO_PACKSHIFT; |
304 | if (rev >= 4) { |
305 | bus->nr_devices = (tmp & SSB_CHIPCO_NRCORESMASK) >> |
306 | SSB_CHIPCO_NRCORESSHIFT; |
307 | } |
308 | tmp = scan_read32(bus, 0, SSB_CHIPCO_CAP); |
309 | bus->chipco.capabilities = tmp; |
310 | } else { |
311 | if (bus->bustype == SSB_BUSTYPE_PCI) { |
312 | bus->chip_id = pcidev_to_chipid(bus->host_pci); |
313 | bus->chip_rev = bus->host_pci->revision; |
314 | bus->chip_package = 0; |
315 | } else { |
316 | bus->chip_id = 0x4710; |
317 | bus->chip_rev = 0; |
318 | bus->chip_package = 0; |
319 | } |
320 | } |
321 | ssb_printk(KERN_INFO PFX "Found chip with id 0x%04X, rev 0x%02X and " |
322 | "package 0x%02X\n", bus->chip_id, bus->chip_rev, |
323 | bus->chip_package); |
324 | if (!bus->nr_devices) |
325 | bus->nr_devices = chipid_to_nrcores(bus->chip_id); |
326 | if (bus->nr_devices > ARRAY_SIZE(bus->devices)) { |
327 | ssb_printk(KERN_ERR PFX |
328 | "More than %d ssb cores found (%d)\n", |
329 | SSB_MAX_NR_CORES, bus->nr_devices); |
330 | goto err_unmap; |
331 | } |
332 | if (bus->bustype == SSB_BUSTYPE_SSB) { |
333 | /* Now that we know the number of cores, |
334 | * remap the whole IO space for all cores. |
335 | */ |
336 | err = -ENOMEM; |
337 | iounmap(mmio); |
338 | mmio = ioremap(baseaddr, SSB_CORE_SIZE * bus->nr_devices); |
339 | if (!mmio) |
340 | goto out; |
341 | bus->mmio = mmio; |
342 | } |
343 | |
344 | /* Fetch basic information about each core/device */ |
345 | for (i = 0, dev_i = 0; i < bus->nr_devices; i++) { |
346 | err = scan_switchcore(bus, i); |
347 | if (err) |
348 | goto err_unmap; |
349 | dev = &(bus->devices[dev_i]); |
350 | |
351 | idhi = scan_read32(bus, i, SSB_IDHIGH); |
352 | dev->id.coreid = (idhi & SSB_IDHIGH_CC) >> SSB_IDHIGH_CC_SHIFT; |
353 | dev->id.revision = (idhi & SSB_IDHIGH_RCLO); |
354 | dev->id.revision |= (idhi & SSB_IDHIGH_RCHI) >> SSB_IDHIGH_RCHI_SHIFT; |
355 | dev->id.vendor = (idhi & SSB_IDHIGH_VC) >> SSB_IDHIGH_VC_SHIFT; |
356 | dev->core_index = i; |
357 | dev->bus = bus; |
358 | dev->ops = bus->ops; |
359 | |
360 | printk(KERN_DEBUG PFX |
361 | "Core %d found: %s " |
362 | "(cc 0x%03X, rev 0x%02X, vendor 0x%04X)\n", |
363 | i, ssb_core_name(dev->id.coreid), |
364 | dev->id.coreid, dev->id.revision, dev->id.vendor); |
365 | |
366 | switch (dev->id.coreid) { |
367 | case SSB_DEV_80211: |
368 | nr_80211_cores++; |
369 | if (nr_80211_cores > 1) { |
370 | if (!we_support_multiple_80211_cores(bus)) { |
371 | ssb_dprintk(KERN_INFO PFX "Ignoring additional " |
372 | "802.11 core\n"); |
373 | continue; |
374 | } |
375 | } |
376 | break; |
377 | case SSB_DEV_EXTIF: |
378 | #ifdef CONFIG_SSB_DRIVER_EXTIF |
379 | if (bus->extif.dev) { |
380 | ssb_printk(KERN_WARNING PFX |
381 | "WARNING: Multiple EXTIFs found\n"); |
382 | break; |
383 | } |
384 | bus->extif.dev = dev; |
385 | #endif /* CONFIG_SSB_DRIVER_EXTIF */ |
386 | break; |
387 | case SSB_DEV_CHIPCOMMON: |
388 | if (bus->chipco.dev) { |
389 | ssb_printk(KERN_WARNING PFX |
390 | "WARNING: Multiple ChipCommon found\n"); |
391 | break; |
392 | } |
393 | bus->chipco.dev = dev; |
394 | break; |
395 | case SSB_DEV_MIPS: |
396 | case SSB_DEV_MIPS_3302: |
397 | #ifdef CONFIG_SSB_DRIVER_MIPS |
398 | if (bus->mipscore.dev) { |
399 | ssb_printk(KERN_WARNING PFX |
400 | "WARNING: Multiple MIPS cores found\n"); |
401 | break; |
402 | } |
403 | bus->mipscore.dev = dev; |
404 | #endif /* CONFIG_SSB_DRIVER_MIPS */ |
405 | break; |
406 | case SSB_DEV_PCI: |
407 | case SSB_DEV_PCIE: |
408 | #ifdef CONFIG_SSB_DRIVER_PCICORE |
409 | if (bus->bustype == SSB_BUSTYPE_PCI) { |
410 | /* Ignore PCI cores on PCI-E cards. |
411 | * Ignore PCI-E cores on PCI cards. */ |
412 | if (dev->id.coreid == SSB_DEV_PCI) { |
413 | if (pci_is_pcie(bus->host_pci)) |
414 | continue; |
415 | } else { |
416 | if (!pci_is_pcie(bus->host_pci)) |
417 | continue; |
418 | } |
419 | } |
420 | if (bus->pcicore.dev) { |
421 | ssb_printk(KERN_WARNING PFX |
422 | "WARNING: Multiple PCI(E) cores found\n"); |
423 | break; |
424 | } |
425 | bus->pcicore.dev = dev; |
426 | #endif /* CONFIG_SSB_DRIVER_PCICORE */ |
427 | break; |
428 | case SSB_DEV_ETHERNET: |
429 | if (bus->bustype == SSB_BUSTYPE_PCI) { |
430 | if (bus->host_pci->vendor == PCI_VENDOR_ID_BROADCOM && |
431 | (bus->host_pci->device & 0xFF00) == 0x4300) { |
432 | /* This is a dangling ethernet core on a |
433 | * wireless device. Ignore it. */ |
434 | continue; |
435 | } |
436 | } |
437 | break; |
438 | default: |
439 | break; |
440 | } |
441 | |
442 | dev_i++; |
443 | } |
444 | bus->nr_devices = dev_i; |
445 | |
446 | err = 0; |
447 | out: |
448 | return err; |
449 | err_unmap: |
450 | ssb_iounmap(bus); |
451 | goto out; |
452 | } |
453 |
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