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1 | perf-list(1) |
2 | ============ |
3 | |
4 | NAME |
5 | ---- |
6 | perf-list - List all symbolic event types |
7 | |
8 | SYNOPSIS |
9 | -------- |
10 | [verse] |
11 | 'perf list' [hw|sw|cache|tracepoint|event_glob] |
12 | |
13 | DESCRIPTION |
14 | ----------- |
15 | This command displays the symbolic event types which can be selected in the |
16 | various perf commands with the -e option. |
17 | |
18 | EVENT MODIFIERS |
19 | --------------- |
20 | |
21 | Events can optionally have a modifer by appending a colon and one or |
22 | more modifiers. Modifiers allow the user to restrict when events are |
23 | counted with 'u' for user-space, 'k' for kernel, 'h' for hypervisor. |
24 | Additional modifiers are 'G' for guest counting (in KVM guests) and 'H' |
25 | for host counting (not in KVM guests). |
26 | |
27 | The 'p' modifier can be used for specifying how precise the instruction |
28 | address should be. The 'p' modifier is currently only implemented for |
29 | Intel PEBS and can be specified multiple times: |
30 | 0 - SAMPLE_IP can have arbitrary skid |
31 | 1 - SAMPLE_IP must have constant skid |
32 | 2 - SAMPLE_IP requested to have 0 skid |
33 | 3 - SAMPLE_IP must have 0 skid |
34 | |
35 | The PEBS implementation now supports up to 2. |
36 | |
37 | RAW HARDWARE EVENT DESCRIPTOR |
38 | ----------------------------- |
39 | Even when an event is not available in a symbolic form within perf right now, |
40 | it can be encoded in a per processor specific way. |
41 | |
42 | For instance For x86 CPUs NNN represents the raw register encoding with the |
43 | layout of IA32_PERFEVTSELx MSRs (see [Intel® 64 and IA-32 Architectures Software Developer's Manual Volume 3B: System Programming Guide] Figure 30-1 Layout |
44 | of IA32_PERFEVTSELx MSRs) or AMD's PerfEvtSeln (see [AMD64 Architecture Programmer’s Manual Volume 2: System Programming], Page 344, |
45 | Figure 13-7 Performance Event-Select Register (PerfEvtSeln)). |
46 | |
47 | Example: |
48 | |
49 | If the Intel docs for a QM720 Core i7 describe an event as: |
50 | |
51 | Event Umask Event Mask |
52 | Num. Value Mnemonic Description Comment |
53 | |
54 | A8H 01H LSD.UOPS Counts the number of micro-ops Use cmask=1 and |
55 | delivered by loop stream detector invert to count |
56 | cycles |
57 | |
58 | raw encoding of 0x1A8 can be used: |
59 | |
60 | perf stat -e r1a8 -a sleep 1 |
61 | perf record -e r1a8 ... |
62 | |
63 | You should refer to the processor specific documentation for getting these |
64 | details. Some of them are referenced in the SEE ALSO section below. |
65 | |
66 | OPTIONS |
67 | ------- |
68 | |
69 | Without options all known events will be listed. |
70 | |
71 | To limit the list use: |
72 | |
73 | . 'hw' or 'hardware' to list hardware events such as cache-misses, etc. |
74 | |
75 | . 'sw' or 'software' to list software events such as context switches, etc. |
76 | |
77 | . 'cache' or 'hwcache' to list hardware cache events such as L1-dcache-loads, etc. |
78 | |
79 | . 'tracepoint' to list all tracepoint events, alternatively use |
80 | 'subsys_glob:event_glob' to filter by tracepoint subsystems such as sched, |
81 | block, etc. |
82 | |
83 | . If none of the above is matched, it will apply the supplied glob to all |
84 | events, printing the ones that match. |
85 | |
86 | One or more types can be used at the same time, listing the events for the |
87 | types specified. |
88 | |
89 | SEE ALSO |
90 | -------- |
91 | linkperf:perf-stat[1], linkperf:perf-top[1], |
92 | linkperf:perf-record[1], |
93 | http://www.intel.com/Assets/PDF/manual/253669.pdf[Intel® 64 and IA-32 Architectures Software Developer's Manual Volume 3B: System Programming Guide], |
94 | http://support.amd.com/us/Processor_TechDocs/24593.pdf[AMD64 Architecture Programmer’s Manual Volume 2: System Programming] |
95 |
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