Root/drivers/ata/ahci.h

1/*
2 * ahci.h - Common AHCI SATA definitions and declarations
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2004-2005 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
32 *
33 */
34
35#ifndef _AHCI_H
36#define _AHCI_H
37
38#include <linux/libata.h>
39
40/* Enclosure Management Control */
41#define EM_CTRL_MSG_TYPE 0x000f0000
42
43/* Enclosure Management LED Message Type */
44#define EM_MSG_LED_HBA_PORT 0x0000000f
45#define EM_MSG_LED_PMP_SLOT 0x0000ff00
46#define EM_MSG_LED_VALUE 0xffff0000
47#define EM_MSG_LED_VALUE_ACTIVITY 0x00070000
48#define EM_MSG_LED_VALUE_OFF 0xfff80000
49#define EM_MSG_LED_VALUE_ON 0x00010000
50
51enum {
52    AHCI_MAX_PORTS = 32,
53    AHCI_MAX_SG = 168, /* hardware max is 64K */
54    AHCI_DMA_BOUNDARY = 0xffffffff,
55    AHCI_MAX_CMDS = 32,
56    AHCI_CMD_SZ = 32,
57    AHCI_CMD_SLOT_SZ = AHCI_MAX_CMDS * AHCI_CMD_SZ,
58    AHCI_RX_FIS_SZ = 256,
59    AHCI_CMD_TBL_CDB = 0x40,
60    AHCI_CMD_TBL_HDR_SZ = 0x80,
61    AHCI_CMD_TBL_SZ = AHCI_CMD_TBL_HDR_SZ + (AHCI_MAX_SG * 16),
62    AHCI_CMD_TBL_AR_SZ = AHCI_CMD_TBL_SZ * AHCI_MAX_CMDS,
63    AHCI_PORT_PRIV_DMA_SZ = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_AR_SZ +
64                  AHCI_RX_FIS_SZ,
65    AHCI_PORT_PRIV_FBS_DMA_SZ = AHCI_CMD_SLOT_SZ +
66                      AHCI_CMD_TBL_AR_SZ +
67                      (AHCI_RX_FIS_SZ * 16),
68    AHCI_IRQ_ON_SG = (1 << 31),
69    AHCI_CMD_ATAPI = (1 << 5),
70    AHCI_CMD_WRITE = (1 << 6),
71    AHCI_CMD_PREFETCH = (1 << 7),
72    AHCI_CMD_RESET = (1 << 8),
73    AHCI_CMD_CLR_BUSY = (1 << 10),
74
75    RX_FIS_PIO_SETUP = 0x20, /* offset of PIO Setup FIS data */
76    RX_FIS_D2H_REG = 0x40, /* offset of D2H Register FIS data */
77    RX_FIS_SDB = 0x58, /* offset of SDB FIS data */
78    RX_FIS_UNK = 0x60, /* offset of Unknown FIS data */
79
80    /* global controller registers */
81    HOST_CAP = 0x00, /* host capabilities */
82    HOST_CTL = 0x04, /* global host control */
83    HOST_IRQ_STAT = 0x08, /* interrupt status */
84    HOST_PORTS_IMPL = 0x0c, /* bitmap of implemented ports */
85    HOST_VERSION = 0x10, /* AHCI spec. version compliancy */
86    HOST_EM_LOC = 0x1c, /* Enclosure Management location */
87    HOST_EM_CTL = 0x20, /* Enclosure Management Control */
88    HOST_CAP2 = 0x24, /* host capabilities, extended */
89
90    /* HOST_CTL bits */
91    HOST_RESET = (1 << 0), /* reset controller; self-clear */
92    HOST_IRQ_EN = (1 << 1), /* global IRQ enable */
93    HOST_AHCI_EN = (1 << 31), /* AHCI enabled */
94
95    /* HOST_CAP bits */
96    HOST_CAP_SXS = (1 << 5), /* Supports External SATA */
97    HOST_CAP_EMS = (1 << 6), /* Enclosure Management support */
98    HOST_CAP_CCC = (1 << 7), /* Command Completion Coalescing */
99    HOST_CAP_PART = (1 << 13), /* Partial state capable */
100    HOST_CAP_SSC = (1 << 14), /* Slumber state capable */
101    HOST_CAP_PIO_MULTI = (1 << 15), /* PIO multiple DRQ support */
102    HOST_CAP_FBS = (1 << 16), /* FIS-based switching support */
103    HOST_CAP_PMP = (1 << 17), /* Port Multiplier support */
104    HOST_CAP_ONLY = (1 << 18), /* Supports AHCI mode only */
105    HOST_CAP_CLO = (1 << 24), /* Command List Override support */
106    HOST_CAP_LED = (1 << 25), /* Supports activity LED */
107    HOST_CAP_ALPM = (1 << 26), /* Aggressive Link PM support */
108    HOST_CAP_SSS = (1 << 27), /* Staggered Spin-up */
109    HOST_CAP_MPS = (1 << 28), /* Mechanical presence switch */
110    HOST_CAP_SNTF = (1 << 29), /* SNotification register */
111    HOST_CAP_NCQ = (1 << 30), /* Native Command Queueing */
112    HOST_CAP_64 = (1 << 31), /* PCI DAC (64-bit DMA) support */
113
114    /* HOST_CAP2 bits */
115    HOST_CAP2_BOH = (1 << 0), /* BIOS/OS handoff supported */
116    HOST_CAP2_NVMHCI = (1 << 1), /* NVMHCI supported */
117    HOST_CAP2_APST = (1 << 2), /* Automatic partial to slumber */
118
119    /* registers for each SATA port */
120    PORT_LST_ADDR = 0x00, /* command list DMA addr */
121    PORT_LST_ADDR_HI = 0x04, /* command list DMA addr hi */
122    PORT_FIS_ADDR = 0x08, /* FIS rx buf addr */
123    PORT_FIS_ADDR_HI = 0x0c, /* FIS rx buf addr hi */
124    PORT_IRQ_STAT = 0x10, /* interrupt status */
125    PORT_IRQ_MASK = 0x14, /* interrupt enable/disable mask */
126    PORT_CMD = 0x18, /* port command */
127    PORT_TFDATA = 0x20, /* taskfile data */
128    PORT_SIG = 0x24, /* device TF signature */
129    PORT_CMD_ISSUE = 0x38, /* command issue */
130    PORT_SCR_STAT = 0x28, /* SATA phy register: SStatus */
131    PORT_SCR_CTL = 0x2c, /* SATA phy register: SControl */
132    PORT_SCR_ERR = 0x30, /* SATA phy register: SError */
133    PORT_SCR_ACT = 0x34, /* SATA phy register: SActive */
134    PORT_SCR_NTF = 0x3c, /* SATA phy register: SNotification */
135    PORT_FBS = 0x40, /* FIS-based Switching */
136
137    /* PORT_IRQ_{STAT,MASK} bits */
138    PORT_IRQ_COLD_PRES = (1 << 31), /* cold presence detect */
139    PORT_IRQ_TF_ERR = (1 << 30), /* task file error */
140    PORT_IRQ_HBUS_ERR = (1 << 29), /* host bus fatal error */
141    PORT_IRQ_HBUS_DATA_ERR = (1 << 28), /* host bus data error */
142    PORT_IRQ_IF_ERR = (1 << 27), /* interface fatal error */
143    PORT_IRQ_IF_NONFATAL = (1 << 26), /* interface non-fatal error */
144    PORT_IRQ_OVERFLOW = (1 << 24), /* xfer exhausted available S/G */
145    PORT_IRQ_BAD_PMP = (1 << 23), /* incorrect port multiplier */
146
147    PORT_IRQ_PHYRDY = (1 << 22), /* PhyRdy changed */
148    PORT_IRQ_DEV_ILCK = (1 << 7), /* device interlock */
149    PORT_IRQ_CONNECT = (1 << 6), /* port connect change status */
150    PORT_IRQ_SG_DONE = (1 << 5), /* descriptor processed */
151    PORT_IRQ_UNK_FIS = (1 << 4), /* unknown FIS rx'd */
152    PORT_IRQ_SDB_FIS = (1 << 3), /* Set Device Bits FIS rx'd */
153    PORT_IRQ_DMAS_FIS = (1 << 2), /* DMA Setup FIS rx'd */
154    PORT_IRQ_PIOS_FIS = (1 << 1), /* PIO Setup FIS rx'd */
155    PORT_IRQ_D2H_REG_FIS = (1 << 0), /* D2H Register FIS rx'd */
156
157    PORT_IRQ_FREEZE = PORT_IRQ_HBUS_ERR |
158                  PORT_IRQ_IF_ERR |
159                  PORT_IRQ_CONNECT |
160                  PORT_IRQ_PHYRDY |
161                  PORT_IRQ_UNK_FIS |
162                  PORT_IRQ_BAD_PMP,
163    PORT_IRQ_ERROR = PORT_IRQ_FREEZE |
164                  PORT_IRQ_TF_ERR |
165                  PORT_IRQ_HBUS_DATA_ERR,
166    DEF_PORT_IRQ = PORT_IRQ_ERROR | PORT_IRQ_SG_DONE |
167                  PORT_IRQ_SDB_FIS | PORT_IRQ_DMAS_FIS |
168                  PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS,
169
170    /* PORT_CMD bits */
171    PORT_CMD_ASP = (1 << 27), /* Aggressive Slumber/Partial */
172    PORT_CMD_ALPE = (1 << 26), /* Aggressive Link PM enable */
173    PORT_CMD_ATAPI = (1 << 24), /* Device is ATAPI */
174    PORT_CMD_FBSCP = (1 << 22), /* FBS Capable Port */
175    PORT_CMD_PMP = (1 << 17), /* PMP attached */
176    PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */
177    PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */
178    PORT_CMD_FIS_RX = (1 << 4), /* Enable FIS receive DMA engine */
179    PORT_CMD_CLO = (1 << 3), /* Command list override */
180    PORT_CMD_POWER_ON = (1 << 2), /* Power up device */
181    PORT_CMD_SPIN_UP = (1 << 1), /* Spin up device */
182    PORT_CMD_START = (1 << 0), /* Enable port DMA engine */
183
184    PORT_CMD_ICC_MASK = (0xf << 28), /* i/f ICC state mask */
185    PORT_CMD_ICC_ACTIVE = (0x1 << 28), /* Put i/f in active state */
186    PORT_CMD_ICC_PARTIAL = (0x2 << 28), /* Put i/f in partial state */
187    PORT_CMD_ICC_SLUMBER = (0x6 << 28), /* Put i/f in slumber state */
188
189    PORT_FBS_DWE_OFFSET = 16, /* FBS device with error offset */
190    PORT_FBS_ADO_OFFSET = 12, /* FBS active dev optimization offset */
191    PORT_FBS_DEV_OFFSET = 8, /* FBS device to issue offset */
192    PORT_FBS_DEV_MASK = (0xf << PORT_FBS_DEV_OFFSET), /* FBS.DEV */
193    PORT_FBS_SDE = (1 << 2), /* FBS single device error */
194    PORT_FBS_DEC = (1 << 1), /* FBS device error clear */
195    PORT_FBS_EN = (1 << 0), /* Enable FBS */
196
197    /* hpriv->flags bits */
198
199#define AHCI_HFLAGS(flags) .private_data = (void *)(flags)
200
201    AHCI_HFLAG_NO_NCQ = (1 << 0),
202    AHCI_HFLAG_IGN_IRQ_IF_ERR = (1 << 1), /* ignore IRQ_IF_ERR */
203    AHCI_HFLAG_IGN_SERR_INTERNAL = (1 << 2), /* ignore SERR_INTERNAL */
204    AHCI_HFLAG_32BIT_ONLY = (1 << 3), /* force 32bit */
205    AHCI_HFLAG_MV_PATA = (1 << 4), /* PATA port */
206    AHCI_HFLAG_NO_MSI = (1 << 5), /* no PCI MSI */
207    AHCI_HFLAG_NO_PMP = (1 << 6), /* no PMP */
208    AHCI_HFLAG_SECT255 = (1 << 8), /* max 255 sectors */
209    AHCI_HFLAG_YES_NCQ = (1 << 9), /* force NCQ cap on */
210    AHCI_HFLAG_NO_SUSPEND = (1 << 10), /* don't suspend */
211    AHCI_HFLAG_SRST_TOUT_IS_OFFLINE = (1 << 11), /* treat SRST timeout as
212                            link offline */
213    AHCI_HFLAG_NO_SNTF = (1 << 12), /* no sntf */
214    AHCI_HFLAG_NO_FPDMA_AA = (1 << 13), /* no FPDMA AA */
215    AHCI_HFLAG_YES_FBS = (1 << 14), /* force FBS cap on */
216    AHCI_HFLAG_DELAY_ENGINE = (1 << 15), /* do not start engine on
217                                port start (wait until
218                                error-handling stage) */
219
220    /* ap->flags bits */
221
222    AHCI_FLAG_COMMON = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA |
223                      ATA_FLAG_ACPI_SATA | ATA_FLAG_AN,
224
225    ICH_MAP = 0x90, /* ICH MAP register */
226
227    /* em constants */
228    EM_MAX_SLOTS = 8,
229    EM_MAX_RETRY = 5,
230
231    /* em_ctl bits */
232    EM_CTL_RST = (1 << 9), /* Reset */
233    EM_CTL_TM = (1 << 8), /* Transmit Message */
234    EM_CTL_MR = (1 << 0), /* Message Received */
235    EM_CTL_ALHD = (1 << 26), /* Activity LED */
236    EM_CTL_XMT = (1 << 25), /* Transmit Only */
237    EM_CTL_SMB = (1 << 24), /* Single Message Buffer */
238    EM_CTL_SGPIO = (1 << 19), /* SGPIO messages supported */
239    EM_CTL_SES = (1 << 18), /* SES-2 messages supported */
240    EM_CTL_SAFTE = (1 << 17), /* SAF-TE messages supported */
241    EM_CTL_LED = (1 << 16), /* LED messages supported */
242
243    /* em message type */
244    EM_MSG_TYPE_LED = (1 << 0), /* LED */
245    EM_MSG_TYPE_SAFTE = (1 << 1), /* SAF-TE */
246    EM_MSG_TYPE_SES2 = (1 << 2), /* SES-2 */
247    EM_MSG_TYPE_SGPIO = (1 << 3), /* SGPIO */
248};
249
250struct ahci_cmd_hdr {
251    __le32 opts;
252    __le32 status;
253    __le32 tbl_addr;
254    __le32 tbl_addr_hi;
255    __le32 reserved[4];
256};
257
258struct ahci_sg {
259    __le32 addr;
260    __le32 addr_hi;
261    __le32 reserved;
262    __le32 flags_size;
263};
264
265struct ahci_em_priv {
266    enum sw_activity blink_policy;
267    struct timer_list timer;
268    unsigned long saved_activity;
269    unsigned long activity;
270    unsigned long led_state;
271};
272
273struct ahci_port_priv {
274    struct ata_link *active_link;
275    struct ahci_cmd_hdr *cmd_slot;
276    dma_addr_t cmd_slot_dma;
277    void *cmd_tbl;
278    dma_addr_t cmd_tbl_dma;
279    void *rx_fis;
280    dma_addr_t rx_fis_dma;
281    /* for NCQ spurious interrupt analysis */
282    unsigned int ncq_saw_d2h:1;
283    unsigned int ncq_saw_dmas:1;
284    unsigned int ncq_saw_sdb:1;
285    u32 intr_mask; /* interrupts to enable */
286    bool fbs_supported; /* set iff FBS is supported */
287    bool fbs_enabled; /* set iff FBS is enabled */
288    int fbs_last_dev; /* save FBS.DEV of last FIS */
289    /* enclosure management info per PM slot */
290    struct ahci_em_priv em_priv[EM_MAX_SLOTS];
291};
292
293struct ahci_host_priv {
294    void __iomem * mmio; /* bus-independent mem map */
295    unsigned int flags; /* AHCI_HFLAG_* */
296    u32 cap; /* cap to use */
297    u32 cap2; /* cap2 to use */
298    u32 port_map; /* port map to use */
299    u32 saved_cap; /* saved initial cap */
300    u32 saved_cap2; /* saved initial cap2 */
301    u32 saved_port_map; /* saved initial port_map */
302    u32 em_loc; /* enclosure management location */
303    u32 em_buf_sz; /* EM buffer size in byte */
304    u32 em_msg_type; /* EM message type */
305};
306
307extern int ahci_ignore_sss;
308
309extern struct device_attribute *ahci_shost_attrs[];
310extern struct device_attribute *ahci_sdev_attrs[];
311
312#define AHCI_SHT(drv_name) \
313    ATA_NCQ_SHT(drv_name), \
314    .can_queue = AHCI_MAX_CMDS - 1, \
315    .sg_tablesize = AHCI_MAX_SG, \
316    .dma_boundary = AHCI_DMA_BOUNDARY, \
317    .shost_attrs = ahci_shost_attrs, \
318    .sdev_attrs = ahci_sdev_attrs
319
320extern struct ata_port_operations ahci_ops;
321extern struct ata_port_operations ahci_pmp_retry_srst_ops;
322
323unsigned int ahci_dev_classify(struct ata_port *ap);
324void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
325            u32 opts);
326void ahci_save_initial_config(struct device *dev,
327                  struct ahci_host_priv *hpriv,
328                  unsigned int force_port_map,
329                  unsigned int mask_port_map);
330void ahci_init_controller(struct ata_host *host);
331int ahci_reset_controller(struct ata_host *host);
332
333int ahci_do_softreset(struct ata_link *link, unsigned int *class,
334              int pmp, unsigned long deadline,
335              int (*check_ready)(struct ata_link *link));
336
337int ahci_stop_engine(struct ata_port *ap);
338void ahci_start_engine(struct ata_port *ap);
339int ahci_check_ready(struct ata_link *link);
340int ahci_kick_engine(struct ata_port *ap);
341int ahci_port_resume(struct ata_port *ap);
342void ahci_set_em_messages(struct ahci_host_priv *hpriv,
343              struct ata_port_info *pi);
344int ahci_reset_em(struct ata_host *host);
345irqreturn_t ahci_interrupt(int irq, void *dev_instance);
346void ahci_print_info(struct ata_host *host, const char *scc_s);
347
348static inline void __iomem *__ahci_port_base(struct ata_host *host,
349                         unsigned int port_no)
350{
351    struct ahci_host_priv *hpriv = host->private_data;
352    void __iomem *mmio = hpriv->mmio;
353
354    return mmio + 0x100 + (port_no * 0x80);
355}
356
357static inline void __iomem *ahci_port_base(struct ata_port *ap)
358{
359    return __ahci_port_base(ap->host, ap->port_no);
360}
361
362static inline int ahci_nr_ports(u32 cap)
363{
364    return (cap & 0x1f) + 1;
365}
366
367#endif /* _AHCI_H */
368

Archive Download this file

Branches:
ben-wpan
ben-wpan-stefan
javiroman/ks7010
jz-2.6.34
jz-2.6.34-rc5
jz-2.6.34-rc6
jz-2.6.34-rc7
jz-2.6.35
jz-2.6.36
jz-2.6.37
jz-2.6.38
jz-2.6.39
jz-3.0
jz-3.1
jz-3.11
jz-3.12
jz-3.13
jz-3.15
jz-3.16
jz-3.18-dt
jz-3.2
jz-3.3
jz-3.4
jz-3.5
jz-3.6
jz-3.6-rc2-pwm
jz-3.9
jz-3.9-clk
jz-3.9-rc8
jz47xx
jz47xx-2.6.38
master

Tags:
od-2011-09-04
od-2011-09-18
v2.6.34-rc5
v2.6.34-rc6
v2.6.34-rc7
v3.9



interactive