Root/drivers/ata/pata_at32.c

1/*
2 * AVR32 SMC/CFC PATA Driver
3 *
4 * Copyright (C) 2007 Atmel Norway
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License version
8 * 2 as published by the Free Software Foundation.
9 */
10
11#define DEBUG
12
13#include <linux/kernel.h>
14#include <linux/module.h>
15#include <linux/init.h>
16#include <linux/device.h>
17#include <linux/platform_device.h>
18#include <linux/delay.h>
19#include <linux/interrupt.h>
20#include <linux/irq.h>
21#include <linux/slab.h>
22#include <scsi/scsi_host.h>
23#include <linux/ata.h>
24#include <linux/libata.h>
25#include <linux/err.h>
26#include <linux/io.h>
27
28#include <mach/board.h>
29#include <mach/smc.h>
30
31#define DRV_NAME "pata_at32"
32#define DRV_VERSION "0.0.3"
33
34/*
35 * CompactFlash controller memory layout relative to the base address:
36 *
37 * Attribute memory: 0000 0000 -> 003f ffff
38 * Common memory: 0040 0000 -> 007f ffff
39 * I/O memory: 0080 0000 -> 00bf ffff
40 * True IDE Mode: 00c0 0000 -> 00df ffff
41 * Alt IDE Mode: 00e0 0000 -> 00ff ffff
42 *
43 * Only True IDE and Alt True IDE mode are needed for this driver.
44 *
45 * True IDE mode => CS0 = 0, CS1 = 1 (cmd, error, stat, etc)
46 * Alt True IDE mode => CS0 = 1, CS1 = 0 (ctl, alt_stat)
47 */
48#define CF_IDE_OFFSET 0x00c00000
49#define CF_ALT_IDE_OFFSET 0x00e00000
50#define CF_RES_SIZE 2048
51
52/*
53 * Define DEBUG_BUS if you are doing debugging of your own EBI -> PATA
54 * adaptor with a logic analyzer or similar.
55 */
56#undef DEBUG_BUS
57
58/*
59 * ATA PIO modes
60 *
61 * Name | Mb/s | Min cycle time | Mask
62 * --------+-------+----------------+--------
63 * Mode 0 | 3.3 | 600 ns | 0x01
64 * Mode 1 | 5.2 | 383 ns | 0x03
65 * Mode 2 | 8.3 | 240 ns | 0x07
66 * Mode 3 | 11.1 | 180 ns | 0x0f
67 * Mode 4 | 16.7 | 120 ns | 0x1f
68 *
69 * Alter PIO_MASK below according to table to set maximal PIO mode.
70 */
71enum {
72  PIO_MASK = ATA_PIO4,
73};
74
75/*
76 * Struct containing private information about device.
77 */
78struct at32_ide_info {
79    unsigned int irq;
80    struct resource res_ide;
81    struct resource res_alt;
82    void __iomem *ide_addr;
83    void __iomem *alt_addr;
84    unsigned int cs;
85    struct smc_config smc;
86};
87
88/*
89 * Setup SMC for the given ATA timing.
90 */
91static int pata_at32_setup_timing(struct device *dev,
92                  struct at32_ide_info *info,
93                  const struct ata_timing *ata)
94{
95    struct smc_config *smc = &info->smc;
96    struct smc_timing timing;
97
98    int active;
99    int recover;
100
101    memset(&timing, 0, sizeof(struct smc_timing));
102
103    /* Total cycle time */
104    timing.read_cycle = ata->cyc8b;
105
106    /* DIOR <= CFIOR timings */
107    timing.nrd_setup = ata->setup;
108    timing.nrd_pulse = ata->act8b;
109    timing.nrd_recover = ata->rec8b;
110
111    /* Convert nanosecond timing to clock cycles */
112    smc_set_timing(smc, &timing);
113
114    /* Add one extra cycle setup due to signal ring */
115    smc->nrd_setup = smc->nrd_setup + 1;
116
117    active = smc->nrd_setup + smc->nrd_pulse;
118    recover = smc->read_cycle - active;
119
120    /* Need at least two cycles recovery */
121    if (recover < 2)
122      smc->read_cycle = active + 2;
123
124    /* (CS0, CS1, DIR, OE) <= (CFCE1, CFCE2, CFRNW, NCSX) timings */
125    smc->ncs_read_setup = 1;
126    smc->ncs_read_pulse = smc->read_cycle - 2;
127
128    /* Write timings same as read timings */
129    smc->write_cycle = smc->read_cycle;
130    smc->nwe_setup = smc->nrd_setup;
131    smc->nwe_pulse = smc->nrd_pulse;
132    smc->ncs_write_setup = smc->ncs_read_setup;
133    smc->ncs_write_pulse = smc->ncs_read_pulse;
134
135    /* Do some debugging output of ATA and SMC timings */
136    dev_dbg(dev, "ATA: C=%d S=%d P=%d R=%d\n",
137        ata->cyc8b, ata->setup, ata->act8b, ata->rec8b);
138
139    dev_dbg(dev, "SMC: C=%d S=%d P=%d NS=%d NP=%d\n",
140        smc->read_cycle, smc->nrd_setup, smc->nrd_pulse,
141        smc->ncs_read_setup, smc->ncs_read_pulse);
142
143    /* Finally, configure the SMC */
144    return smc_set_configuration(info->cs, smc);
145}
146
147/*
148 * Procedures for libATA.
149 */
150static void pata_at32_set_piomode(struct ata_port *ap, struct ata_device *adev)
151{
152    struct ata_timing timing;
153    struct at32_ide_info *info = ap->host->private_data;
154
155    int ret;
156
157    /* Compute ATA timing */
158    ret = ata_timing_compute(adev, adev->pio_mode, &timing, 1000, 0);
159    if (ret) {
160        dev_warn(ap->dev, "Failed to compute ATA timing %d\n", ret);
161        return;
162    }
163
164    /* Setup SMC to ATA timing */
165    ret = pata_at32_setup_timing(ap->dev, info, &timing);
166    if (ret) {
167        dev_warn(ap->dev, "Failed to setup ATA timing %d\n", ret);
168        return;
169    }
170}
171
172static struct scsi_host_template at32_sht = {
173    ATA_PIO_SHT(DRV_NAME),
174};
175
176static struct ata_port_operations at32_port_ops = {
177    .inherits = &ata_sff_port_ops,
178    .cable_detect = ata_cable_40wire,
179    .set_piomode = pata_at32_set_piomode,
180};
181
182static int __init pata_at32_init_one(struct device *dev,
183                     struct at32_ide_info *info)
184{
185    struct ata_host *host;
186    struct ata_port *ap;
187
188    host = ata_host_alloc(dev, 1);
189    if (!host)
190        return -ENOMEM;
191
192    ap = host->ports[0];
193
194    /* Setup ATA bindings */
195    ap->ops = &at32_port_ops;
196    ap->pio_mask = PIO_MASK;
197    ap->flags |= ATA_FLAG_SLAVE_POSS;
198
199    /*
200     * Since all 8-bit taskfile transfers has to go on the lower
201     * byte of the data bus and there is a bug in the SMC that
202     * makes it impossible to alter the bus width during runtime,
203     * we need to hardwire the address signals as follows:
204     *
205     * A_IDE(2:0) <= A_EBI(3:1)
206     *
207     * This makes all addresses on the EBI even, thus all data
208     * will be on the lower byte of the data bus. All addresses
209     * used by libATA need to be altered according to this.
210     */
211    ap->ioaddr.altstatus_addr = info->alt_addr + (0x06 << 1);
212    ap->ioaddr.ctl_addr = info->alt_addr + (0x06 << 1);
213
214    ap->ioaddr.data_addr = info->ide_addr + (ATA_REG_DATA << 1);
215    ap->ioaddr.error_addr = info->ide_addr + (ATA_REG_ERR << 1);
216    ap->ioaddr.feature_addr = info->ide_addr + (ATA_REG_FEATURE << 1);
217    ap->ioaddr.nsect_addr = info->ide_addr + (ATA_REG_NSECT << 1);
218    ap->ioaddr.lbal_addr = info->ide_addr + (ATA_REG_LBAL << 1);
219    ap->ioaddr.lbam_addr = info->ide_addr + (ATA_REG_LBAM << 1);
220    ap->ioaddr.lbah_addr = info->ide_addr + (ATA_REG_LBAH << 1);
221    ap->ioaddr.device_addr = info->ide_addr + (ATA_REG_DEVICE << 1);
222    ap->ioaddr.status_addr = info->ide_addr + (ATA_REG_STATUS << 1);
223    ap->ioaddr.command_addr = info->ide_addr + (ATA_REG_CMD << 1);
224
225    /* Set info as private data of ATA host */
226    host->private_data = info;
227
228    /* Register ATA device and return */
229    return ata_host_activate(host, info->irq, ata_sff_interrupt,
230                 IRQF_SHARED | IRQF_TRIGGER_RISING,
231                 &at32_sht);
232}
233
234/*
235 * This function may come in handy for people analyzing their own
236 * EBI -> PATA adaptors.
237 */
238#ifdef DEBUG_BUS
239
240static void __init pata_at32_debug_bus(struct device *dev,
241                       struct at32_ide_info *info)
242{
243    const int d1 = 0xff;
244    const int d2 = 0x00;
245
246    int i;
247
248    /* Write 8-bit values (registers) */
249    iowrite8(d1, info->alt_addr + (0x06 << 1));
250    iowrite8(d2, info->alt_addr + (0x06 << 1));
251
252    for (i = 0; i < 8; i++) {
253        iowrite8(d1, info->ide_addr + (i << 1));
254        iowrite8(d2, info->ide_addr + (i << 1));
255    }
256
257    /* Write 16 bit values (data) */
258    iowrite16(d1, info->ide_addr);
259    iowrite16(d1 << 8, info->ide_addr);
260
261    iowrite16(d1, info->ide_addr);
262    iowrite16(d1 << 8, info->ide_addr);
263}
264
265#endif
266
267static int __init pata_at32_probe(struct platform_device *pdev)
268{
269    const struct ata_timing initial_timing =
270        {XFER_PIO_0, 70, 290, 240, 600, 165, 150, 600, 0};
271
272    struct device *dev = &pdev->dev;
273    struct at32_ide_info *info;
274    struct ide_platform_data *board = pdev->dev.platform_data;
275    struct resource *res;
276
277    int irq;
278    int ret;
279
280    if (!board)
281        return -ENXIO;
282
283    res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
284    if (!res)
285        return -ENXIO;
286
287    /* Retrive IRQ */
288    irq = platform_get_irq(pdev, 0);
289    if (irq < 0)
290        return irq;
291
292    /* Setup struct containing private information */
293    info = kzalloc(sizeof(struct at32_ide_info), GFP_KERNEL);
294    if (!info)
295        return -ENOMEM;
296
297    info->irq = irq;
298    info->cs = board->cs;
299
300    /* Request memory resources */
301    info->res_ide.start = res->start + CF_IDE_OFFSET;
302    info->res_ide.end = info->res_ide.start + CF_RES_SIZE - 1;
303    info->res_ide.name = "ide";
304    info->res_ide.flags = IORESOURCE_MEM;
305
306    ret = request_resource(res, &info->res_ide);
307    if (ret)
308        goto err_req_res_ide;
309
310    info->res_alt.start = res->start + CF_ALT_IDE_OFFSET;
311    info->res_alt.end = info->res_alt.start + CF_RES_SIZE - 1;
312    info->res_alt.name = "alt";
313    info->res_alt.flags = IORESOURCE_MEM;
314
315    ret = request_resource(res, &info->res_alt);
316    if (ret)
317        goto err_req_res_alt;
318
319    /* Setup non-timing elements of SMC */
320    info->smc.bus_width = 2; /* 16 bit data bus */
321    info->smc.nrd_controlled = 1; /* Sample data on rising edge of NRD */
322    info->smc.nwe_controlled = 0; /* Drive data on falling edge of NCS */
323    info->smc.nwait_mode = 3; /* NWAIT is in READY mode */
324    info->smc.byte_write = 0; /* Byte select access type */
325    info->smc.tdf_mode = 0; /* TDF optimization disabled */
326    info->smc.tdf_cycles = 0; /* No TDF wait cycles */
327
328    /* Setup SMC to ATA timing */
329    ret = pata_at32_setup_timing(dev, info, &initial_timing);
330    if (ret)
331        goto err_setup_timing;
332
333    /* Map ATA address space */
334    ret = -ENOMEM;
335    info->ide_addr = devm_ioremap(dev, info->res_ide.start, 16);
336    info->alt_addr = devm_ioremap(dev, info->res_alt.start, 16);
337    if (!info->ide_addr || !info->alt_addr)
338        goto err_ioremap;
339
340#ifdef DEBUG_BUS
341    pata_at32_debug_bus(dev, info);
342#endif
343
344    /* Setup and register ATA device */
345    ret = pata_at32_init_one(dev, info);
346    if (ret)
347        goto err_ata_device;
348
349    return 0;
350
351 err_ata_device:
352 err_ioremap:
353 err_setup_timing:
354    release_resource(&info->res_alt);
355 err_req_res_alt:
356    release_resource(&info->res_ide);
357 err_req_res_ide:
358    kfree(info);
359
360    return ret;
361}
362
363static int __exit pata_at32_remove(struct platform_device *pdev)
364{
365    struct ata_host *host = platform_get_drvdata(pdev);
366    struct at32_ide_info *info;
367
368    if (!host)
369        return 0;
370
371    info = host->private_data;
372    ata_host_detach(host);
373
374    if (!info)
375        return 0;
376
377    release_resource(&info->res_ide);
378    release_resource(&info->res_alt);
379
380    kfree(info);
381
382    return 0;
383}
384
385/* work with hotplug and coldplug */
386MODULE_ALIAS("platform:at32_ide");
387
388static struct platform_driver pata_at32_driver = {
389    .remove = __exit_p(pata_at32_remove),
390    .driver = {
391        .name = "at32_ide",
392        .owner = THIS_MODULE,
393    },
394};
395
396static int __init pata_at32_init(void)
397{
398    return platform_driver_probe(&pata_at32_driver, pata_at32_probe);
399}
400
401static void __exit pata_at32_exit(void)
402{
403    platform_driver_unregister(&pata_at32_driver);
404}
405
406module_init(pata_at32_init);
407module_exit(pata_at32_exit);
408
409MODULE_LICENSE("GPL");
410MODULE_DESCRIPTION("AVR32 SMC/CFC PATA Driver");
411MODULE_AUTHOR("Kristoffer Nyborg Gregertsen <kngregertsen@norway.atmel.com>");
412MODULE_VERSION(DRV_VERSION);
413

Archive Download this file

Branches:
ben-wpan
ben-wpan-stefan
javiroman/ks7010
jz-2.6.34
jz-2.6.34-rc5
jz-2.6.34-rc6
jz-2.6.34-rc7
jz-2.6.35
jz-2.6.36
jz-2.6.37
jz-2.6.38
jz-2.6.39
jz-3.0
jz-3.1
jz-3.11
jz-3.12
jz-3.13
jz-3.15
jz-3.16
jz-3.18-dt
jz-3.2
jz-3.3
jz-3.4
jz-3.5
jz-3.6
jz-3.6-rc2-pwm
jz-3.9
jz-3.9-clk
jz-3.9-rc8
jz47xx
jz47xx-2.6.38
master

Tags:
od-2011-09-04
od-2011-09-18
v2.6.34-rc5
v2.6.34-rc6
v2.6.34-rc7
v3.9



interactive