Root/drivers/char/mwave/3780i.c

1/*
2*
3* 3780i.c -- helper routines for the 3780i DSP
4*
5*
6* Written By: Mike Sullivan IBM Corporation
7*
8* Copyright (C) 1999 IBM Corporation
9*
10* This program is free software; you can redistribute it and/or modify
11* it under the terms of the GNU General Public License as published by
12* the Free Software Foundation; either version 2 of the License, or
13* (at your option) any later version.
14*
15* This program is distributed in the hope that it will be useful,
16* but WITHOUT ANY WARRANTY; without even the implied warranty of
17* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18* GNU General Public License for more details.
19*
20* NO WARRANTY
21* THE PROGRAM IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR
22* CONDITIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED INCLUDING, WITHOUT
23* LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT,
24* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Each Recipient is
25* solely responsible for determining the appropriateness of using and
26* distributing the Program and assumes all risks associated with its
27* exercise of rights under this Agreement, including but not limited to
28* the risks and costs of program errors, damage to or loss of data,
29* programs or equipment, and unavailability or interruption of operations.
30*
31* DISCLAIMER OF LIABILITY
32* NEITHER RECIPIENT NOR ANY CONTRIBUTORS SHALL HAVE ANY LIABILITY FOR ANY
33* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
34* DAMAGES (INCLUDING WITHOUT LIMITATION LOST PROFITS), HOWEVER CAUSED AND
35* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
36* TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
37* USE OR DISTRIBUTION OF THE PROGRAM OR THE EXERCISE OF ANY RIGHTS GRANTED
38* HEREUNDER, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES
39*
40* You should have received a copy of the GNU General Public License
41* along with this program; if not, write to the Free Software
42* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
43*
44*
45* 10/23/2000 - Alpha Release
46* First release to the public
47*/
48
49#include <linux/kernel.h>
50#include <linux/unistd.h>
51#include <linux/delay.h>
52#include <linux/ioport.h>
53#include <linux/init.h>
54#include <linux/bitops.h>
55#include <linux/sched.h> /* cond_resched() */
56
57#include <asm/io.h>
58#include <asm/uaccess.h>
59#include <asm/irq.h>
60#include "smapi.h"
61#include "mwavedd.h"
62#include "3780i.h"
63
64static DEFINE_SPINLOCK(dsp_lock);
65
66static void PaceMsaAccess(unsigned short usDspBaseIO)
67{
68    cond_resched();
69    udelay(100);
70    cond_resched();
71}
72
73unsigned short dsp3780I_ReadMsaCfg(unsigned short usDspBaseIO,
74                                   unsigned long ulMsaAddr)
75{
76    unsigned long flags;
77    unsigned short val;
78
79    PRINTK_3(TRACE_3780I,
80        "3780i::dsp3780I_ReadMsaCfg entry usDspBaseIO %x ulMsaAddr %lx\n",
81        usDspBaseIO, ulMsaAddr);
82
83    spin_lock_irqsave(&dsp_lock, flags);
84    OutWordDsp(DSP_MsaAddrLow, (unsigned short) ulMsaAddr);
85    OutWordDsp(DSP_MsaAddrHigh, (unsigned short) (ulMsaAddr >> 16));
86    val = InWordDsp(DSP_MsaDataDSISHigh);
87    spin_unlock_irqrestore(&dsp_lock, flags);
88
89    PRINTK_2(TRACE_3780I, "3780i::dsp3780I_ReadMsaCfg exit val %x\n", val);
90
91    return val;
92}
93
94void dsp3780I_WriteMsaCfg(unsigned short usDspBaseIO,
95                          unsigned long ulMsaAddr, unsigned short usValue)
96{
97    unsigned long flags;
98
99    PRINTK_4(TRACE_3780I,
100        "3780i::dsp3780i_WriteMsaCfg entry usDspBaseIO %x ulMsaAddr %lx usValue %x\n",
101        usDspBaseIO, ulMsaAddr, usValue);
102
103    spin_lock_irqsave(&dsp_lock, flags);
104    OutWordDsp(DSP_MsaAddrLow, (unsigned short) ulMsaAddr);
105    OutWordDsp(DSP_MsaAddrHigh, (unsigned short) (ulMsaAddr >> 16));
106    OutWordDsp(DSP_MsaDataDSISHigh, usValue);
107    spin_unlock_irqrestore(&dsp_lock, flags);
108}
109
110static void dsp3780I_WriteGenCfg(unsigned short usDspBaseIO, unsigned uIndex,
111                 unsigned char ucValue)
112{
113    DSP_ISA_SLAVE_CONTROL rSlaveControl;
114    DSP_ISA_SLAVE_CONTROL rSlaveControl_Save;
115
116
117    PRINTK_4(TRACE_3780I,
118        "3780i::dsp3780i_WriteGenCfg entry usDspBaseIO %x uIndex %x ucValue %x\n",
119        usDspBaseIO, uIndex, ucValue);
120
121    MKBYTE(rSlaveControl) = InByteDsp(DSP_IsaSlaveControl);
122
123    PRINTK_2(TRACE_3780I,
124        "3780i::dsp3780i_WriteGenCfg rSlaveControl %x\n",
125        MKBYTE(rSlaveControl));
126
127    rSlaveControl_Save = rSlaveControl;
128    rSlaveControl.ConfigMode = TRUE;
129
130    PRINTK_2(TRACE_3780I,
131        "3780i::dsp3780i_WriteGenCfg entry rSlaveControl+ConfigMode %x\n",
132        MKBYTE(rSlaveControl));
133
134    OutByteDsp(DSP_IsaSlaveControl, MKBYTE(rSlaveControl));
135    OutByteDsp(DSP_ConfigAddress, (unsigned char) uIndex);
136    OutByteDsp(DSP_ConfigData, ucValue);
137    OutByteDsp(DSP_IsaSlaveControl, MKBYTE(rSlaveControl_Save));
138
139    PRINTK_1(TRACE_3780I, "3780i::dsp3780i_WriteGenCfg exit\n");
140
141
142}
143
144#if 0
145unsigned char dsp3780I_ReadGenCfg(unsigned short usDspBaseIO,
146                                  unsigned uIndex)
147{
148    DSP_ISA_SLAVE_CONTROL rSlaveControl;
149    DSP_ISA_SLAVE_CONTROL rSlaveControl_Save;
150    unsigned char ucValue;
151
152
153    PRINTK_3(TRACE_3780I,
154        "3780i::dsp3780i_ReadGenCfg entry usDspBaseIO %x uIndex %x\n",
155        usDspBaseIO, uIndex);
156
157    MKBYTE(rSlaveControl) = InByteDsp(DSP_IsaSlaveControl);
158    rSlaveControl_Save = rSlaveControl;
159    rSlaveControl.ConfigMode = TRUE;
160    OutByteDsp(DSP_IsaSlaveControl, MKBYTE(rSlaveControl));
161    OutByteDsp(DSP_ConfigAddress, (unsigned char) uIndex);
162    ucValue = InByteDsp(DSP_ConfigData);
163    OutByteDsp(DSP_IsaSlaveControl, MKBYTE(rSlaveControl_Save));
164
165    PRINTK_2(TRACE_3780I,
166        "3780i::dsp3780i_ReadGenCfg exit ucValue %x\n", ucValue);
167
168
169    return ucValue;
170}
171#endif /* 0 */
172
173int dsp3780I_EnableDSP(DSP_3780I_CONFIG_SETTINGS * pSettings,
174                       unsigned short *pIrqMap,
175                       unsigned short *pDmaMap)
176{
177    unsigned long flags;
178    unsigned short usDspBaseIO = pSettings->usDspBaseIO;
179    int i;
180    DSP_UART_CFG_1 rUartCfg1;
181    DSP_UART_CFG_2 rUartCfg2;
182    DSP_HBRIDGE_CFG_1 rHBridgeCfg1;
183    DSP_HBRIDGE_CFG_2 rHBridgeCfg2;
184    DSP_BUSMASTER_CFG_1 rBusmasterCfg1;
185    DSP_BUSMASTER_CFG_2 rBusmasterCfg2;
186    DSP_ISA_PROT_CFG rIsaProtCfg;
187    DSP_POWER_MGMT_CFG rPowerMgmtCfg;
188    DSP_HBUS_TIMER_CFG rHBusTimerCfg;
189    DSP_LBUS_TIMEOUT_DISABLE rLBusTimeoutDisable;
190    DSP_CHIP_RESET rChipReset;
191    DSP_CLOCK_CONTROL_1 rClockControl1;
192    DSP_CLOCK_CONTROL_2 rClockControl2;
193    DSP_ISA_SLAVE_CONTROL rSlaveControl;
194    DSP_HBRIDGE_CONTROL rHBridgeControl;
195    unsigned short ChipID = 0;
196    unsigned short tval;
197
198
199    PRINTK_2(TRACE_3780I,
200        "3780i::dsp3780I_EnableDSP entry pSettings->bDSPEnabled %x\n",
201        pSettings->bDSPEnabled);
202
203
204    if (!pSettings->bDSPEnabled) {
205        PRINTK_ERROR( KERN_ERR "3780i::dsp3780I_EnableDSP: Error: DSP not enabled. Aborting.\n" );
206        return -EIO;
207    }
208
209
210    PRINTK_2(TRACE_3780I,
211        "3780i::dsp3780i_EnableDSP entry pSettings->bModemEnabled %x\n",
212        pSettings->bModemEnabled);
213
214    if (pSettings->bModemEnabled) {
215        rUartCfg1.Reserved = rUartCfg2.Reserved = 0;
216        rUartCfg1.IrqActiveLow = pSettings->bUartIrqActiveLow;
217        rUartCfg1.IrqPulse = pSettings->bUartIrqPulse;
218        rUartCfg1.Irq =
219            (unsigned char) pIrqMap[pSettings->usUartIrq];
220        switch (pSettings->usUartBaseIO) {
221        case 0x03F8:
222            rUartCfg1.BaseIO = 0;
223            break;
224        case 0x02F8:
225            rUartCfg1.BaseIO = 1;
226            break;
227        case 0x03E8:
228            rUartCfg1.BaseIO = 2;
229            break;
230        case 0x02E8:
231            rUartCfg1.BaseIO = 3;
232            break;
233        }
234        rUartCfg2.Enable = TRUE;
235    }
236
237    rHBridgeCfg1.Reserved = rHBridgeCfg2.Reserved = 0;
238    rHBridgeCfg1.IrqActiveLow = pSettings->bDspIrqActiveLow;
239    rHBridgeCfg1.IrqPulse = pSettings->bDspIrqPulse;
240    rHBridgeCfg1.Irq = (unsigned char) pIrqMap[pSettings->usDspIrq];
241    rHBridgeCfg1.AccessMode = 1;
242    rHBridgeCfg2.Enable = TRUE;
243
244
245    rBusmasterCfg2.Reserved = 0;
246    rBusmasterCfg1.Dma = (unsigned char) pDmaMap[pSettings->usDspDma];
247    rBusmasterCfg1.NumTransfers =
248        (unsigned char) pSettings->usNumTransfers;
249    rBusmasterCfg1.ReRequest = (unsigned char) pSettings->usReRequest;
250    rBusmasterCfg1.MEMCS16 = pSettings->bEnableMEMCS16;
251    rBusmasterCfg2.IsaMemCmdWidth =
252        (unsigned char) pSettings->usIsaMemCmdWidth;
253
254
255    rIsaProtCfg.Reserved = 0;
256    rIsaProtCfg.GateIOCHRDY = pSettings->bGateIOCHRDY;
257
258    rPowerMgmtCfg.Reserved = 0;
259    rPowerMgmtCfg.Enable = pSettings->bEnablePwrMgmt;
260
261    rHBusTimerCfg.LoadValue =
262        (unsigned char) pSettings->usHBusTimerLoadValue;
263
264    rLBusTimeoutDisable.Reserved = 0;
265    rLBusTimeoutDisable.DisableTimeout =
266        pSettings->bDisableLBusTimeout;
267
268    MKWORD(rChipReset) = ~pSettings->usChipletEnable;
269
270    rClockControl1.Reserved1 = rClockControl1.Reserved2 = 0;
271    rClockControl1.N_Divisor = pSettings->usN_Divisor;
272    rClockControl1.M_Multiplier = pSettings->usM_Multiplier;
273
274    rClockControl2.Reserved = 0;
275    rClockControl2.PllBypass = pSettings->bPllBypass;
276
277    /* Issue a soft reset to the chip */
278    /* Note: Since we may be coming in with 3780i clocks suspended, we must keep
279    * soft-reset active for 10ms.
280    */
281    rSlaveControl.ClockControl = 0;
282    rSlaveControl.SoftReset = TRUE;
283    rSlaveControl.ConfigMode = FALSE;
284    rSlaveControl.Reserved = 0;
285
286    PRINTK_4(TRACE_3780I,
287        "3780i::dsp3780i_EnableDSP usDspBaseIO %x index %x taddr %x\n",
288        usDspBaseIO, DSP_IsaSlaveControl,
289        usDspBaseIO + DSP_IsaSlaveControl);
290
291    PRINTK_2(TRACE_3780I,
292        "3780i::dsp3780i_EnableDSP rSlaveContrl %x\n",
293        MKWORD(rSlaveControl));
294
295    spin_lock_irqsave(&dsp_lock, flags);
296    OutWordDsp(DSP_IsaSlaveControl, MKWORD(rSlaveControl));
297    MKWORD(tval) = InWordDsp(DSP_IsaSlaveControl);
298
299    PRINTK_2(TRACE_3780I,
300        "3780i::dsp3780i_EnableDSP rSlaveControl 2 %x\n", tval);
301
302
303    for (i = 0; i < 11; i++)
304        udelay(2000);
305
306    rSlaveControl.SoftReset = FALSE;
307    OutWordDsp(DSP_IsaSlaveControl, MKWORD(rSlaveControl));
308
309    MKWORD(tval) = InWordDsp(DSP_IsaSlaveControl);
310
311    PRINTK_2(TRACE_3780I,
312        "3780i::dsp3780i_EnableDSP rSlaveControl 3 %x\n", tval);
313
314
315    /* Program our general configuration registers */
316    WriteGenCfg(DSP_HBridgeCfg1Index, MKBYTE(rHBridgeCfg1));
317    WriteGenCfg(DSP_HBridgeCfg2Index, MKBYTE(rHBridgeCfg2));
318    WriteGenCfg(DSP_BusMasterCfg1Index, MKBYTE(rBusmasterCfg1));
319    WriteGenCfg(DSP_BusMasterCfg2Index, MKBYTE(rBusmasterCfg2));
320    WriteGenCfg(DSP_IsaProtCfgIndex, MKBYTE(rIsaProtCfg));
321    WriteGenCfg(DSP_PowerMgCfgIndex, MKBYTE(rPowerMgmtCfg));
322    WriteGenCfg(DSP_HBusTimerCfgIndex, MKBYTE(rHBusTimerCfg));
323
324    if (pSettings->bModemEnabled) {
325        WriteGenCfg(DSP_UartCfg1Index, MKBYTE(rUartCfg1));
326        WriteGenCfg(DSP_UartCfg2Index, MKBYTE(rUartCfg2));
327    }
328
329
330    rHBridgeControl.EnableDspInt = FALSE;
331    rHBridgeControl.MemAutoInc = TRUE;
332    rHBridgeControl.IoAutoInc = FALSE;
333    rHBridgeControl.DiagnosticMode = FALSE;
334
335    PRINTK_3(TRACE_3780I,
336        "3780i::dsp3780i_EnableDSP DSP_HBridgeControl %x rHBridgeControl %x\n",
337        DSP_HBridgeControl, MKWORD(rHBridgeControl));
338
339    OutWordDsp(DSP_HBridgeControl, MKWORD(rHBridgeControl));
340    spin_unlock_irqrestore(&dsp_lock, flags);
341    WriteMsaCfg(DSP_LBusTimeoutDisable, MKWORD(rLBusTimeoutDisable));
342    WriteMsaCfg(DSP_ClockControl_1, MKWORD(rClockControl1));
343    WriteMsaCfg(DSP_ClockControl_2, MKWORD(rClockControl2));
344    WriteMsaCfg(DSP_ChipReset, MKWORD(rChipReset));
345
346    ChipID = ReadMsaCfg(DSP_ChipID);
347
348    PRINTK_2(TRACE_3780I,
349        "3780i::dsp3780I_EnableDSP exiting bRC=TRUE, ChipID %x\n",
350        ChipID);
351
352    return 0;
353}
354
355int dsp3780I_DisableDSP(DSP_3780I_CONFIG_SETTINGS * pSettings)
356{
357    unsigned long flags;
358    unsigned short usDspBaseIO = pSettings->usDspBaseIO;
359    DSP_ISA_SLAVE_CONTROL rSlaveControl;
360
361
362    PRINTK_1(TRACE_3780I, "3780i::dsp3780i_DisableDSP entry\n");
363
364    rSlaveControl.ClockControl = 0;
365    rSlaveControl.SoftReset = TRUE;
366    rSlaveControl.ConfigMode = FALSE;
367    rSlaveControl.Reserved = 0;
368    spin_lock_irqsave(&dsp_lock, flags);
369    OutWordDsp(DSP_IsaSlaveControl, MKWORD(rSlaveControl));
370
371    udelay(5);
372
373    rSlaveControl.ClockControl = 1;
374    OutWordDsp(DSP_IsaSlaveControl, MKWORD(rSlaveControl));
375    spin_unlock_irqrestore(&dsp_lock, flags);
376
377    udelay(5);
378
379
380    PRINTK_1(TRACE_3780I, "3780i::dsp3780i_DisableDSP exit\n");
381
382    return 0;
383}
384
385int dsp3780I_Reset(DSP_3780I_CONFIG_SETTINGS * pSettings)
386{
387    unsigned long flags;
388    unsigned short usDspBaseIO = pSettings->usDspBaseIO;
389    DSP_BOOT_DOMAIN rBootDomain;
390    DSP_HBRIDGE_CONTROL rHBridgeControl;
391
392
393    PRINTK_1(TRACE_3780I, "3780i::dsp3780i_Reset entry\n");
394
395    spin_lock_irqsave(&dsp_lock, flags);
396    /* Mask DSP to PC interrupt */
397    MKWORD(rHBridgeControl) = InWordDsp(DSP_HBridgeControl);
398
399    PRINTK_2(TRACE_3780I, "3780i::dsp3780i_Reset rHBridgeControl %x\n",
400        MKWORD(rHBridgeControl));
401
402    rHBridgeControl.EnableDspInt = FALSE;
403    OutWordDsp(DSP_HBridgeControl, MKWORD(rHBridgeControl));
404    spin_unlock_irqrestore(&dsp_lock, flags);
405
406    /* Reset the core via the boot domain register */
407    rBootDomain.ResetCore = TRUE;
408    rBootDomain.Halt = TRUE;
409    rBootDomain.NMI = TRUE;
410    rBootDomain.Reserved = 0;
411
412    PRINTK_2(TRACE_3780I, "3780i::dsp3780i_Reset rBootDomain %x\n",
413        MKWORD(rBootDomain));
414
415    WriteMsaCfg(DSP_MspBootDomain, MKWORD(rBootDomain));
416
417    /* Reset all the chiplets and then reactivate them */
418    WriteMsaCfg(DSP_ChipReset, 0xFFFF);
419    udelay(5);
420    WriteMsaCfg(DSP_ChipReset,
421            (unsigned short) (~pSettings->usChipletEnable));
422
423
424    PRINTK_1(TRACE_3780I, "3780i::dsp3780i_Reset exit bRC=0\n");
425
426    return 0;
427}
428
429
430int dsp3780I_Run(DSP_3780I_CONFIG_SETTINGS * pSettings)
431{
432    unsigned long flags;
433    unsigned short usDspBaseIO = pSettings->usDspBaseIO;
434    DSP_BOOT_DOMAIN rBootDomain;
435    DSP_HBRIDGE_CONTROL rHBridgeControl;
436
437
438    PRINTK_1(TRACE_3780I, "3780i::dsp3780i_Run entry\n");
439
440
441    /* Transition the core to a running state */
442    rBootDomain.ResetCore = TRUE;
443    rBootDomain.Halt = FALSE;
444    rBootDomain.NMI = TRUE;
445    rBootDomain.Reserved = 0;
446    WriteMsaCfg(DSP_MspBootDomain, MKWORD(rBootDomain));
447
448    udelay(5);
449
450    rBootDomain.ResetCore = FALSE;
451    WriteMsaCfg(DSP_MspBootDomain, MKWORD(rBootDomain));
452    udelay(5);
453
454    rBootDomain.NMI = FALSE;
455    WriteMsaCfg(DSP_MspBootDomain, MKWORD(rBootDomain));
456    udelay(5);
457
458    /* Enable DSP to PC interrupt */
459    spin_lock_irqsave(&dsp_lock, flags);
460    MKWORD(rHBridgeControl) = InWordDsp(DSP_HBridgeControl);
461    rHBridgeControl.EnableDspInt = TRUE;
462
463    PRINTK_2(TRACE_3780I, "3780i::dsp3780i_Run rHBridgeControl %x\n",
464        MKWORD(rHBridgeControl));
465
466    OutWordDsp(DSP_HBridgeControl, MKWORD(rHBridgeControl));
467    spin_unlock_irqrestore(&dsp_lock, flags);
468
469
470    PRINTK_1(TRACE_3780I, "3780i::dsp3780i_Run exit bRC=TRUE\n");
471
472    return 0;
473}
474
475
476int dsp3780I_ReadDStore(unsigned short usDspBaseIO, void __user *pvBuffer,
477                        unsigned uCount, unsigned long ulDSPAddr)
478{
479    unsigned long flags;
480    unsigned short __user *pusBuffer = pvBuffer;
481    unsigned short val;
482
483
484    PRINTK_5(TRACE_3780I,
485        "3780i::dsp3780I_ReadDStore entry usDspBaseIO %x, pusBuffer %p, uCount %x, ulDSPAddr %lx\n",
486        usDspBaseIO, pusBuffer, uCount, ulDSPAddr);
487
488
489    /* Set the initial MSA address. No adjustments need to be made to data store addresses */
490    spin_lock_irqsave(&dsp_lock, flags);
491    OutWordDsp(DSP_MsaAddrLow, (unsigned short) ulDSPAddr);
492    OutWordDsp(DSP_MsaAddrHigh, (unsigned short) (ulDSPAddr >> 16));
493    spin_unlock_irqrestore(&dsp_lock, flags);
494
495    /* Transfer the memory block */
496    while (uCount-- != 0) {
497        spin_lock_irqsave(&dsp_lock, flags);
498        val = InWordDsp(DSP_MsaDataDSISHigh);
499        spin_unlock_irqrestore(&dsp_lock, flags);
500        if(put_user(val, pusBuffer++))
501            return -EFAULT;
502
503        PRINTK_3(TRACE_3780I,
504            "3780I::dsp3780I_ReadDStore uCount %x val %x\n",
505            uCount, val);
506
507        PaceMsaAccess(usDspBaseIO);
508    }
509
510
511    PRINTK_1(TRACE_3780I,
512        "3780I::dsp3780I_ReadDStore exit bRC=TRUE\n");
513
514    return 0;
515}
516
517int dsp3780I_ReadAndClearDStore(unsigned short usDspBaseIO,
518                                void __user *pvBuffer, unsigned uCount,
519                                unsigned long ulDSPAddr)
520{
521    unsigned long flags;
522    unsigned short __user *pusBuffer = pvBuffer;
523    unsigned short val;
524
525
526    PRINTK_5(TRACE_3780I,
527        "3780i::dsp3780I_ReadAndDStore entry usDspBaseIO %x, pusBuffer %p, uCount %x, ulDSPAddr %lx\n",
528        usDspBaseIO, pusBuffer, uCount, ulDSPAddr);
529
530
531    /* Set the initial MSA address. No adjustments need to be made to data store addresses */
532    spin_lock_irqsave(&dsp_lock, flags);
533    OutWordDsp(DSP_MsaAddrLow, (unsigned short) ulDSPAddr);
534    OutWordDsp(DSP_MsaAddrHigh, (unsigned short) (ulDSPAddr >> 16));
535    spin_unlock_irqrestore(&dsp_lock, flags);
536
537    /* Transfer the memory block */
538    while (uCount-- != 0) {
539        spin_lock_irqsave(&dsp_lock, flags);
540        val = InWordDsp(DSP_ReadAndClear);
541        spin_unlock_irqrestore(&dsp_lock, flags);
542        if(put_user(val, pusBuffer++))
543            return -EFAULT;
544
545        PRINTK_3(TRACE_3780I,
546            "3780I::dsp3780I_ReadAndCleanDStore uCount %x val %x\n",
547            uCount, val);
548
549        PaceMsaAccess(usDspBaseIO);
550    }
551
552
553    PRINTK_1(TRACE_3780I,
554        "3780I::dsp3780I_ReadAndClearDStore exit bRC=TRUE\n");
555
556    return 0;
557}
558
559
560int dsp3780I_WriteDStore(unsigned short usDspBaseIO, void __user *pvBuffer,
561                         unsigned uCount, unsigned long ulDSPAddr)
562{
563    unsigned long flags;
564    unsigned short __user *pusBuffer = pvBuffer;
565
566
567    PRINTK_5(TRACE_3780I,
568        "3780i::dsp3780D_WriteDStore entry usDspBaseIO %x, pusBuffer %p, uCount %x, ulDSPAddr %lx\n",
569        usDspBaseIO, pusBuffer, uCount, ulDSPAddr);
570
571
572    /* Set the initial MSA address. No adjustments need to be made to data store addresses */
573    spin_lock_irqsave(&dsp_lock, flags);
574    OutWordDsp(DSP_MsaAddrLow, (unsigned short) ulDSPAddr);
575    OutWordDsp(DSP_MsaAddrHigh, (unsigned short) (ulDSPAddr >> 16));
576    spin_unlock_irqrestore(&dsp_lock, flags);
577
578    /* Transfer the memory block */
579    while (uCount-- != 0) {
580        unsigned short val;
581        if(get_user(val, pusBuffer++))
582            return -EFAULT;
583        spin_lock_irqsave(&dsp_lock, flags);
584        OutWordDsp(DSP_MsaDataDSISHigh, val);
585        spin_unlock_irqrestore(&dsp_lock, flags);
586
587        PRINTK_3(TRACE_3780I,
588            "3780I::dsp3780I_WriteDStore uCount %x val %x\n",
589            uCount, val);
590
591        PaceMsaAccess(usDspBaseIO);
592    }
593
594
595    PRINTK_1(TRACE_3780I,
596        "3780I::dsp3780D_WriteDStore exit bRC=TRUE\n");
597
598    return 0;
599}
600
601
602int dsp3780I_ReadIStore(unsigned short usDspBaseIO, void __user *pvBuffer,
603                        unsigned uCount, unsigned long ulDSPAddr)
604{
605    unsigned long flags;
606    unsigned short __user *pusBuffer = pvBuffer;
607
608    PRINTK_5(TRACE_3780I,
609        "3780i::dsp3780I_ReadIStore entry usDspBaseIO %x, pusBuffer %p, uCount %x, ulDSPAddr %lx\n",
610        usDspBaseIO, pusBuffer, uCount, ulDSPAddr);
611
612    /*
613    * Set the initial MSA address. To convert from an instruction store
614    * address to an MSA address
615    * shift the address two bits to the left and set bit 22
616    */
617    ulDSPAddr = (ulDSPAddr << 2) | (1 << 22);
618    spin_lock_irqsave(&dsp_lock, flags);
619    OutWordDsp(DSP_MsaAddrLow, (unsigned short) ulDSPAddr);
620    OutWordDsp(DSP_MsaAddrHigh, (unsigned short) (ulDSPAddr >> 16));
621    spin_unlock_irqrestore(&dsp_lock, flags);
622
623    /* Transfer the memory block */
624    while (uCount-- != 0) {
625        unsigned short val_lo, val_hi;
626        spin_lock_irqsave(&dsp_lock, flags);
627        val_lo = InWordDsp(DSP_MsaDataISLow);
628        val_hi = InWordDsp(DSP_MsaDataDSISHigh);
629        spin_unlock_irqrestore(&dsp_lock, flags);
630        if(put_user(val_lo, pusBuffer++))
631            return -EFAULT;
632        if(put_user(val_hi, pusBuffer++))
633            return -EFAULT;
634
635        PRINTK_4(TRACE_3780I,
636            "3780I::dsp3780I_ReadIStore uCount %x val_lo %x val_hi %x\n",
637            uCount, val_lo, val_hi);
638
639        PaceMsaAccess(usDspBaseIO);
640
641    }
642
643    PRINTK_1(TRACE_3780I,
644        "3780I::dsp3780I_ReadIStore exit bRC=TRUE\n");
645
646    return 0;
647}
648
649
650int dsp3780I_WriteIStore(unsigned short usDspBaseIO, void __user *pvBuffer,
651                         unsigned uCount, unsigned long ulDSPAddr)
652{
653    unsigned long flags;
654    unsigned short __user *pusBuffer = pvBuffer;
655
656    PRINTK_5(TRACE_3780I,
657        "3780i::dsp3780I_WriteIStore entry usDspBaseIO %x, pusBuffer %p, uCount %x, ulDSPAddr %lx\n",
658        usDspBaseIO, pusBuffer, uCount, ulDSPAddr);
659
660
661    /*
662    * Set the initial MSA address. To convert from an instruction store
663    * address to an MSA address
664    * shift the address two bits to the left and set bit 22
665    */
666    ulDSPAddr = (ulDSPAddr << 2) | (1 << 22);
667    spin_lock_irqsave(&dsp_lock, flags);
668    OutWordDsp(DSP_MsaAddrLow, (unsigned short) ulDSPAddr);
669    OutWordDsp(DSP_MsaAddrHigh, (unsigned short) (ulDSPAddr >> 16));
670    spin_unlock_irqrestore(&dsp_lock, flags);
671
672    /* Transfer the memory block */
673    while (uCount-- != 0) {
674        unsigned short val_lo, val_hi;
675        if(get_user(val_lo, pusBuffer++))
676            return -EFAULT;
677        if(get_user(val_hi, pusBuffer++))
678            return -EFAULT;
679        spin_lock_irqsave(&dsp_lock, flags);
680        OutWordDsp(DSP_MsaDataISLow, val_lo);
681        OutWordDsp(DSP_MsaDataDSISHigh, val_hi);
682        spin_unlock_irqrestore(&dsp_lock, flags);
683
684        PRINTK_4(TRACE_3780I,
685            "3780I::dsp3780I_WriteIStore uCount %x val_lo %x val_hi %x\n",
686            uCount, val_lo, val_hi);
687
688        PaceMsaAccess(usDspBaseIO);
689
690    }
691
692    PRINTK_1(TRACE_3780I,
693        "3780I::dsp3780I_WriteIStore exit bRC=TRUE\n");
694
695    return 0;
696}
697
698
699int dsp3780I_GetIPCSource(unsigned short usDspBaseIO,
700                          unsigned short *pusIPCSource)
701{
702    unsigned long flags;
703    DSP_HBRIDGE_CONTROL rHBridgeControl;
704    unsigned short temp;
705
706
707    PRINTK_3(TRACE_3780I,
708        "3780i::dsp3780I_GetIPCSource entry usDspBaseIO %x pusIPCSource %p\n",
709        usDspBaseIO, pusIPCSource);
710
711    /*
712    * Disable DSP to PC interrupts, read the interrupt register,
713    * clear the pending IPC bits, and reenable DSP to PC interrupts
714    */
715    spin_lock_irqsave(&dsp_lock, flags);
716    MKWORD(rHBridgeControl) = InWordDsp(DSP_HBridgeControl);
717    rHBridgeControl.EnableDspInt = FALSE;
718    OutWordDsp(DSP_HBridgeControl, MKWORD(rHBridgeControl));
719
720    *pusIPCSource = InWordDsp(DSP_Interrupt);
721    temp = (unsigned short) ~(*pusIPCSource);
722
723    PRINTK_3(TRACE_3780I,
724        "3780i::dsp3780I_GetIPCSource, usIPCSource %x ~ %x\n",
725        *pusIPCSource, temp);
726
727    OutWordDsp(DSP_Interrupt, (unsigned short) ~(*pusIPCSource));
728
729    rHBridgeControl.EnableDspInt = TRUE;
730    OutWordDsp(DSP_HBridgeControl, MKWORD(rHBridgeControl));
731    spin_unlock_irqrestore(&dsp_lock, flags);
732
733
734    PRINTK_2(TRACE_3780I,
735        "3780i::dsp3780I_GetIPCSource exit usIPCSource %x\n",
736        *pusIPCSource);
737
738    return 0;
739}
740

Archive Download this file



interactive