Root/drivers/clocksource/sh_cmt.c

1/*
2 * SuperH Timer Support - CMT
3 *
4 * Copyright (C) 2008 Magnus Damm
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20#include <linux/init.h>
21#include <linux/platform_device.h>
22#include <linux/spinlock.h>
23#include <linux/interrupt.h>
24#include <linux/ioport.h>
25#include <linux/io.h>
26#include <linux/clk.h>
27#include <linux/irq.h>
28#include <linux/err.h>
29#include <linux/delay.h>
30#include <linux/clocksource.h>
31#include <linux/clockchips.h>
32#include <linux/sh_timer.h>
33#include <linux/slab.h>
34#include <linux/module.h>
35#include <linux/pm_domain.h>
36
37struct sh_cmt_priv {
38    void __iomem *mapbase;
39    struct clk *clk;
40    unsigned long width; /* 16 or 32 bit version of hardware block */
41    unsigned long overflow_bit;
42    unsigned long clear_bits;
43    struct irqaction irqaction;
44    struct platform_device *pdev;
45
46    unsigned long flags;
47    unsigned long match_value;
48    unsigned long next_match_value;
49    unsigned long max_match_value;
50    unsigned long rate;
51    raw_spinlock_t lock;
52    struct clock_event_device ced;
53    struct clocksource cs;
54    unsigned long total_cycles;
55};
56
57static DEFINE_RAW_SPINLOCK(sh_cmt_lock);
58
59#define CMSTR -1 /* shared register */
60#define CMCSR 0 /* channel register */
61#define CMCNT 1 /* channel register */
62#define CMCOR 2 /* channel register */
63
64static inline unsigned long sh_cmt_read(struct sh_cmt_priv *p, int reg_nr)
65{
66    struct sh_timer_config *cfg = p->pdev->dev.platform_data;
67    void __iomem *base = p->mapbase;
68    unsigned long offs;
69
70    if (reg_nr == CMSTR) {
71        offs = 0;
72        base -= cfg->channel_offset;
73    } else
74        offs = reg_nr;
75
76    if (p->width == 16)
77        offs <<= 1;
78    else {
79        offs <<= 2;
80        if ((reg_nr == CMCNT) || (reg_nr == CMCOR))
81            return ioread32(base + offs);
82    }
83
84    return ioread16(base + offs);
85}
86
87static inline void sh_cmt_write(struct sh_cmt_priv *p, int reg_nr,
88                unsigned long value)
89{
90    struct sh_timer_config *cfg = p->pdev->dev.platform_data;
91    void __iomem *base = p->mapbase;
92    unsigned long offs;
93
94    if (reg_nr == CMSTR) {
95        offs = 0;
96        base -= cfg->channel_offset;
97    } else
98        offs = reg_nr;
99
100    if (p->width == 16)
101        offs <<= 1;
102    else {
103        offs <<= 2;
104        if ((reg_nr == CMCNT) || (reg_nr == CMCOR)) {
105            iowrite32(value, base + offs);
106            return;
107        }
108    }
109
110    iowrite16(value, base + offs);
111}
112
113static unsigned long sh_cmt_get_counter(struct sh_cmt_priv *p,
114                    int *has_wrapped)
115{
116    unsigned long v1, v2, v3;
117    int o1, o2;
118
119    o1 = sh_cmt_read(p, CMCSR) & p->overflow_bit;
120
121    /* Make sure the timer value is stable. Stolen from acpi_pm.c */
122    do {
123        o2 = o1;
124        v1 = sh_cmt_read(p, CMCNT);
125        v2 = sh_cmt_read(p, CMCNT);
126        v3 = sh_cmt_read(p, CMCNT);
127        o1 = sh_cmt_read(p, CMCSR) & p->overflow_bit;
128    } while (unlikely((o1 != o2) || (v1 > v2 && v1 < v3)
129              || (v2 > v3 && v2 < v1) || (v3 > v1 && v3 < v2)));
130
131    *has_wrapped = o1;
132    return v2;
133}
134
135
136static void sh_cmt_start_stop_ch(struct sh_cmt_priv *p, int start)
137{
138    struct sh_timer_config *cfg = p->pdev->dev.platform_data;
139    unsigned long flags, value;
140
141    /* start stop register shared by multiple timer channels */
142    raw_spin_lock_irqsave(&sh_cmt_lock, flags);
143    value = sh_cmt_read(p, CMSTR);
144
145    if (start)
146        value |= 1 << cfg->timer_bit;
147    else
148        value &= ~(1 << cfg->timer_bit);
149
150    sh_cmt_write(p, CMSTR, value);
151    raw_spin_unlock_irqrestore(&sh_cmt_lock, flags);
152}
153
154static int sh_cmt_enable(struct sh_cmt_priv *p, unsigned long *rate)
155{
156    int k, ret;
157
158    /* enable clock */
159    ret = clk_enable(p->clk);
160    if (ret) {
161        dev_err(&p->pdev->dev, "cannot enable clock\n");
162        goto err0;
163    }
164
165    /* make sure channel is disabled */
166    sh_cmt_start_stop_ch(p, 0);
167
168    /* configure channel, periodic mode and maximum timeout */
169    if (p->width == 16) {
170        *rate = clk_get_rate(p->clk) / 512;
171        sh_cmt_write(p, CMCSR, 0x43);
172    } else {
173        *rate = clk_get_rate(p->clk) / 8;
174        sh_cmt_write(p, CMCSR, 0x01a4);
175    }
176
177    sh_cmt_write(p, CMCOR, 0xffffffff);
178    sh_cmt_write(p, CMCNT, 0);
179
180    /*
181     * According to the sh73a0 user's manual, as CMCNT can be operated
182     * only by the RCLK (Pseudo 32 KHz), there's one restriction on
183     * modifying CMCNT register; two RCLK cycles are necessary before
184     * this register is either read or any modification of the value
185     * it holds is reflected in the LSI's actual operation.
186     *
187     * While at it, we're supposed to clear out the CMCNT as of this
188     * moment, so make sure it's processed properly here. This will
189     * take RCLKx2 at maximum.
190     */
191    for (k = 0; k < 100; k++) {
192        if (!sh_cmt_read(p, CMCNT))
193            break;
194        udelay(1);
195    }
196
197    if (sh_cmt_read(p, CMCNT)) {
198        dev_err(&p->pdev->dev, "cannot clear CMCNT\n");
199        ret = -ETIMEDOUT;
200        goto err1;
201    }
202
203    /* enable channel */
204    sh_cmt_start_stop_ch(p, 1);
205    return 0;
206 err1:
207    /* stop clock */
208    clk_disable(p->clk);
209
210 err0:
211    return ret;
212}
213
214static void sh_cmt_disable(struct sh_cmt_priv *p)
215{
216    /* disable channel */
217    sh_cmt_start_stop_ch(p, 0);
218
219    /* disable interrupts in CMT block */
220    sh_cmt_write(p, CMCSR, 0);
221
222    /* stop clock */
223    clk_disable(p->clk);
224}
225
226/* private flags */
227#define FLAG_CLOCKEVENT (1 << 0)
228#define FLAG_CLOCKSOURCE (1 << 1)
229#define FLAG_REPROGRAM (1 << 2)
230#define FLAG_SKIPEVENT (1 << 3)
231#define FLAG_IRQCONTEXT (1 << 4)
232
233static void sh_cmt_clock_event_program_verify(struct sh_cmt_priv *p,
234                          int absolute)
235{
236    unsigned long new_match;
237    unsigned long value = p->next_match_value;
238    unsigned long delay = 0;
239    unsigned long now = 0;
240    int has_wrapped;
241
242    now = sh_cmt_get_counter(p, &has_wrapped);
243    p->flags |= FLAG_REPROGRAM; /* force reprogram */
244
245    if (has_wrapped) {
246        /* we're competing with the interrupt handler.
247         * -> let the interrupt handler reprogram the timer.
248         * -> interrupt number two handles the event.
249         */
250        p->flags |= FLAG_SKIPEVENT;
251        return;
252    }
253
254    if (absolute)
255        now = 0;
256
257    do {
258        /* reprogram the timer hardware,
259         * but don't save the new match value yet.
260         */
261        new_match = now + value + delay;
262        if (new_match > p->max_match_value)
263            new_match = p->max_match_value;
264
265        sh_cmt_write(p, CMCOR, new_match);
266
267        now = sh_cmt_get_counter(p, &has_wrapped);
268        if (has_wrapped && (new_match > p->match_value)) {
269            /* we are changing to a greater match value,
270             * so this wrap must be caused by the counter
271             * matching the old value.
272             * -> first interrupt reprograms the timer.
273             * -> interrupt number two handles the event.
274             */
275            p->flags |= FLAG_SKIPEVENT;
276            break;
277        }
278
279        if (has_wrapped) {
280            /* we are changing to a smaller match value,
281             * so the wrap must be caused by the counter
282             * matching the new value.
283             * -> save programmed match value.
284             * -> let isr handle the event.
285             */
286            p->match_value = new_match;
287            break;
288        }
289
290        /* be safe: verify hardware settings */
291        if (now < new_match) {
292            /* timer value is below match value, all good.
293             * this makes sure we won't miss any match events.
294             * -> save programmed match value.
295             * -> let isr handle the event.
296             */
297            p->match_value = new_match;
298            break;
299        }
300
301        /* the counter has reached a value greater
302         * than our new match value. and since the
303         * has_wrapped flag isn't set we must have
304         * programmed a too close event.
305         * -> increase delay and retry.
306         */
307        if (delay)
308            delay <<= 1;
309        else
310            delay = 1;
311
312        if (!delay)
313            dev_warn(&p->pdev->dev, "too long delay\n");
314
315    } while (delay);
316}
317
318static void __sh_cmt_set_next(struct sh_cmt_priv *p, unsigned long delta)
319{
320    if (delta > p->max_match_value)
321        dev_warn(&p->pdev->dev, "delta out of range\n");
322
323    p->next_match_value = delta;
324    sh_cmt_clock_event_program_verify(p, 0);
325}
326
327static void sh_cmt_set_next(struct sh_cmt_priv *p, unsigned long delta)
328{
329    unsigned long flags;
330
331    raw_spin_lock_irqsave(&p->lock, flags);
332    __sh_cmt_set_next(p, delta);
333    raw_spin_unlock_irqrestore(&p->lock, flags);
334}
335
336static irqreturn_t sh_cmt_interrupt(int irq, void *dev_id)
337{
338    struct sh_cmt_priv *p = dev_id;
339
340    /* clear flags */
341    sh_cmt_write(p, CMCSR, sh_cmt_read(p, CMCSR) & p->clear_bits);
342
343    /* update clock source counter to begin with if enabled
344     * the wrap flag should be cleared by the timer specific
345     * isr before we end up here.
346     */
347    if (p->flags & FLAG_CLOCKSOURCE)
348        p->total_cycles += p->match_value + 1;
349
350    if (!(p->flags & FLAG_REPROGRAM))
351        p->next_match_value = p->max_match_value;
352
353    p->flags |= FLAG_IRQCONTEXT;
354
355    if (p->flags & FLAG_CLOCKEVENT) {
356        if (!(p->flags & FLAG_SKIPEVENT)) {
357            if (p->ced.mode == CLOCK_EVT_MODE_ONESHOT) {
358                p->next_match_value = p->max_match_value;
359                p->flags |= FLAG_REPROGRAM;
360            }
361
362            p->ced.event_handler(&p->ced);
363        }
364    }
365
366    p->flags &= ~FLAG_SKIPEVENT;
367
368    if (p->flags & FLAG_REPROGRAM) {
369        p->flags &= ~FLAG_REPROGRAM;
370        sh_cmt_clock_event_program_verify(p, 1);
371
372        if (p->flags & FLAG_CLOCKEVENT)
373            if ((p->ced.mode == CLOCK_EVT_MODE_SHUTDOWN)
374                || (p->match_value == p->next_match_value))
375                p->flags &= ~FLAG_REPROGRAM;
376    }
377
378    p->flags &= ~FLAG_IRQCONTEXT;
379
380    return IRQ_HANDLED;
381}
382
383static int sh_cmt_start(struct sh_cmt_priv *p, unsigned long flag)
384{
385    int ret = 0;
386    unsigned long flags;
387
388    raw_spin_lock_irqsave(&p->lock, flags);
389
390    if (!(p->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE)))
391        ret = sh_cmt_enable(p, &p->rate);
392
393    if (ret)
394        goto out;
395    p->flags |= flag;
396
397    /* setup timeout if no clockevent */
398    if ((flag == FLAG_CLOCKSOURCE) && (!(p->flags & FLAG_CLOCKEVENT)))
399        __sh_cmt_set_next(p, p->max_match_value);
400 out:
401    raw_spin_unlock_irqrestore(&p->lock, flags);
402
403    return ret;
404}
405
406static void sh_cmt_stop(struct sh_cmt_priv *p, unsigned long flag)
407{
408    unsigned long flags;
409    unsigned long f;
410
411    raw_spin_lock_irqsave(&p->lock, flags);
412
413    f = p->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE);
414    p->flags &= ~flag;
415
416    if (f && !(p->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE)))
417        sh_cmt_disable(p);
418
419    /* adjust the timeout to maximum if only clocksource left */
420    if ((flag == FLAG_CLOCKEVENT) && (p->flags & FLAG_CLOCKSOURCE))
421        __sh_cmt_set_next(p, p->max_match_value);
422
423    raw_spin_unlock_irqrestore(&p->lock, flags);
424}
425
426static struct sh_cmt_priv *cs_to_sh_cmt(struct clocksource *cs)
427{
428    return container_of(cs, struct sh_cmt_priv, cs);
429}
430
431static cycle_t sh_cmt_clocksource_read(struct clocksource *cs)
432{
433    struct sh_cmt_priv *p = cs_to_sh_cmt(cs);
434    unsigned long flags, raw;
435    unsigned long value;
436    int has_wrapped;
437
438    raw_spin_lock_irqsave(&p->lock, flags);
439    value = p->total_cycles;
440    raw = sh_cmt_get_counter(p, &has_wrapped);
441
442    if (unlikely(has_wrapped))
443        raw += p->match_value + 1;
444    raw_spin_unlock_irqrestore(&p->lock, flags);
445
446    return value + raw;
447}
448
449static int sh_cmt_clocksource_enable(struct clocksource *cs)
450{
451    int ret;
452    struct sh_cmt_priv *p = cs_to_sh_cmt(cs);
453
454    p->total_cycles = 0;
455
456    ret = sh_cmt_start(p, FLAG_CLOCKSOURCE);
457    if (!ret)
458        __clocksource_updatefreq_hz(cs, p->rate);
459    return ret;
460}
461
462static void sh_cmt_clocksource_disable(struct clocksource *cs)
463{
464    sh_cmt_stop(cs_to_sh_cmt(cs), FLAG_CLOCKSOURCE);
465}
466
467static void sh_cmt_clocksource_resume(struct clocksource *cs)
468{
469    sh_cmt_start(cs_to_sh_cmt(cs), FLAG_CLOCKSOURCE);
470}
471
472static int sh_cmt_register_clocksource(struct sh_cmt_priv *p,
473                       char *name, unsigned long rating)
474{
475    struct clocksource *cs = &p->cs;
476
477    cs->name = name;
478    cs->rating = rating;
479    cs->read = sh_cmt_clocksource_read;
480    cs->enable = sh_cmt_clocksource_enable;
481    cs->disable = sh_cmt_clocksource_disable;
482    cs->suspend = sh_cmt_clocksource_disable;
483    cs->resume = sh_cmt_clocksource_resume;
484    cs->mask = CLOCKSOURCE_MASK(sizeof(unsigned long) * 8);
485    cs->flags = CLOCK_SOURCE_IS_CONTINUOUS;
486
487    dev_info(&p->pdev->dev, "used as clock source\n");
488
489    /* Register with dummy 1 Hz value, gets updated in ->enable() */
490    clocksource_register_hz(cs, 1);
491    return 0;
492}
493
494static struct sh_cmt_priv *ced_to_sh_cmt(struct clock_event_device *ced)
495{
496    return container_of(ced, struct sh_cmt_priv, ced);
497}
498
499static void sh_cmt_clock_event_start(struct sh_cmt_priv *p, int periodic)
500{
501    struct clock_event_device *ced = &p->ced;
502
503    sh_cmt_start(p, FLAG_CLOCKEVENT);
504
505    /* TODO: calculate good shift from rate and counter bit width */
506
507    ced->shift = 32;
508    ced->mult = div_sc(p->rate, NSEC_PER_SEC, ced->shift);
509    ced->max_delta_ns = clockevent_delta2ns(p->max_match_value, ced);
510    ced->min_delta_ns = clockevent_delta2ns(0x1f, ced);
511
512    if (periodic)
513        sh_cmt_set_next(p, ((p->rate + HZ/2) / HZ) - 1);
514    else
515        sh_cmt_set_next(p, p->max_match_value);
516}
517
518static void sh_cmt_clock_event_mode(enum clock_event_mode mode,
519                    struct clock_event_device *ced)
520{
521    struct sh_cmt_priv *p = ced_to_sh_cmt(ced);
522
523    /* deal with old setting first */
524    switch (ced->mode) {
525    case CLOCK_EVT_MODE_PERIODIC:
526    case CLOCK_EVT_MODE_ONESHOT:
527        sh_cmt_stop(p, FLAG_CLOCKEVENT);
528        break;
529    default:
530        break;
531    }
532
533    switch (mode) {
534    case CLOCK_EVT_MODE_PERIODIC:
535        dev_info(&p->pdev->dev, "used for periodic clock events\n");
536        sh_cmt_clock_event_start(p, 1);
537        break;
538    case CLOCK_EVT_MODE_ONESHOT:
539        dev_info(&p->pdev->dev, "used for oneshot clock events\n");
540        sh_cmt_clock_event_start(p, 0);
541        break;
542    case CLOCK_EVT_MODE_SHUTDOWN:
543    case CLOCK_EVT_MODE_UNUSED:
544        sh_cmt_stop(p, FLAG_CLOCKEVENT);
545        break;
546    default:
547        break;
548    }
549}
550
551static int sh_cmt_clock_event_next(unsigned long delta,
552                   struct clock_event_device *ced)
553{
554    struct sh_cmt_priv *p = ced_to_sh_cmt(ced);
555
556    BUG_ON(ced->mode != CLOCK_EVT_MODE_ONESHOT);
557    if (likely(p->flags & FLAG_IRQCONTEXT))
558        p->next_match_value = delta - 1;
559    else
560        sh_cmt_set_next(p, delta - 1);
561
562    return 0;
563}
564
565static void sh_cmt_register_clockevent(struct sh_cmt_priv *p,
566                       char *name, unsigned long rating)
567{
568    struct clock_event_device *ced = &p->ced;
569
570    memset(ced, 0, sizeof(*ced));
571
572    ced->name = name;
573    ced->features = CLOCK_EVT_FEAT_PERIODIC;
574    ced->features |= CLOCK_EVT_FEAT_ONESHOT;
575    ced->rating = rating;
576    ced->cpumask = cpumask_of(0);
577    ced->set_next_event = sh_cmt_clock_event_next;
578    ced->set_mode = sh_cmt_clock_event_mode;
579
580    dev_info(&p->pdev->dev, "used for clock events\n");
581    clockevents_register_device(ced);
582}
583
584static int sh_cmt_register(struct sh_cmt_priv *p, char *name,
585               unsigned long clockevent_rating,
586               unsigned long clocksource_rating)
587{
588    if (p->width == (sizeof(p->max_match_value) * 8))
589        p->max_match_value = ~0;
590    else
591        p->max_match_value = (1 << p->width) - 1;
592
593    p->match_value = p->max_match_value;
594    raw_spin_lock_init(&p->lock);
595
596    if (clockevent_rating)
597        sh_cmt_register_clockevent(p, name, clockevent_rating);
598
599    if (clocksource_rating)
600        sh_cmt_register_clocksource(p, name, clocksource_rating);
601
602    return 0;
603}
604
605static int sh_cmt_setup(struct sh_cmt_priv *p, struct platform_device *pdev)
606{
607    struct sh_timer_config *cfg = pdev->dev.platform_data;
608    struct resource *res;
609    int irq, ret;
610    ret = -ENXIO;
611
612    memset(p, 0, sizeof(*p));
613    p->pdev = pdev;
614
615    if (!cfg) {
616        dev_err(&p->pdev->dev, "missing platform data\n");
617        goto err0;
618    }
619
620    platform_set_drvdata(pdev, p);
621
622    res = platform_get_resource(p->pdev, IORESOURCE_MEM, 0);
623    if (!res) {
624        dev_err(&p->pdev->dev, "failed to get I/O memory\n");
625        goto err0;
626    }
627
628    irq = platform_get_irq(p->pdev, 0);
629    if (irq < 0) {
630        dev_err(&p->pdev->dev, "failed to get irq\n");
631        goto err0;
632    }
633
634    /* map memory, let mapbase point to our channel */
635    p->mapbase = ioremap_nocache(res->start, resource_size(res));
636    if (p->mapbase == NULL) {
637        dev_err(&p->pdev->dev, "failed to remap I/O memory\n");
638        goto err0;
639    }
640
641    /* request irq using setup_irq() (too early for request_irq()) */
642    p->irqaction.name = dev_name(&p->pdev->dev);
643    p->irqaction.handler = sh_cmt_interrupt;
644    p->irqaction.dev_id = p;
645    p->irqaction.flags = IRQF_DISABLED | IRQF_TIMER | \
646                 IRQF_IRQPOLL | IRQF_NOBALANCING;
647
648    /* get hold of clock */
649    p->clk = clk_get(&p->pdev->dev, "cmt_fck");
650    if (IS_ERR(p->clk)) {
651        dev_err(&p->pdev->dev, "cannot get clock\n");
652        ret = PTR_ERR(p->clk);
653        goto err1;
654    }
655
656    if (resource_size(res) == 6) {
657        p->width = 16;
658        p->overflow_bit = 0x80;
659        p->clear_bits = ~0x80;
660    } else {
661        p->width = 32;
662        p->overflow_bit = 0x8000;
663        p->clear_bits = ~0xc000;
664    }
665
666    ret = sh_cmt_register(p, (char *)dev_name(&p->pdev->dev),
667                  cfg->clockevent_rating,
668                  cfg->clocksource_rating);
669    if (ret) {
670        dev_err(&p->pdev->dev, "registration failed\n");
671        goto err1;
672    }
673
674    ret = setup_irq(irq, &p->irqaction);
675    if (ret) {
676        dev_err(&p->pdev->dev, "failed to request irq %d\n", irq);
677        goto err1;
678    }
679
680    return 0;
681
682err1:
683    iounmap(p->mapbase);
684err0:
685    return ret;
686}
687
688static int __devinit sh_cmt_probe(struct platform_device *pdev)
689{
690    struct sh_cmt_priv *p = platform_get_drvdata(pdev);
691    int ret;
692
693    if (!is_early_platform_device(pdev))
694        pm_genpd_dev_always_on(&pdev->dev, true);
695
696    if (p) {
697        dev_info(&pdev->dev, "kept as earlytimer\n");
698        return 0;
699    }
700
701    p = kmalloc(sizeof(*p), GFP_KERNEL);
702    if (p == NULL) {
703        dev_err(&pdev->dev, "failed to allocate driver data\n");
704        return -ENOMEM;
705    }
706
707    ret = sh_cmt_setup(p, pdev);
708    if (ret) {
709        kfree(p);
710        platform_set_drvdata(pdev, NULL);
711    }
712    return ret;
713}
714
715static int __devexit sh_cmt_remove(struct platform_device *pdev)
716{
717    return -EBUSY; /* cannot unregister clockevent and clocksource */
718}
719
720static struct platform_driver sh_cmt_device_driver = {
721    .probe = sh_cmt_probe,
722    .remove = __devexit_p(sh_cmt_remove),
723    .driver = {
724        .name = "sh_cmt",
725    }
726};
727
728static int __init sh_cmt_init(void)
729{
730    return platform_driver_register(&sh_cmt_device_driver);
731}
732
733static void __exit sh_cmt_exit(void)
734{
735    platform_driver_unregister(&sh_cmt_device_driver);
736}
737
738early_platform_init("earlytimer", &sh_cmt_device_driver);
739module_init(sh_cmt_init);
740module_exit(sh_cmt_exit);
741
742MODULE_AUTHOR("Magnus Damm");
743MODULE_DESCRIPTION("SuperH CMT Timer Driver");
744MODULE_LICENSE("GPL v2");
745

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