Root/drivers/cpufreq/speedstep-ich.c

1/*
2 * (C) 2001 Dave Jones, Arjan van de ven.
3 * (C) 2002 - 2003 Dominik Brodowski <linux@brodo.de>
4 *
5 * Licensed under the terms of the GNU GPL License version 2.
6 * Based upon reverse engineered information, and on Intel documentation
7 * for chipsets ICH2-M and ICH3-M.
8 *
9 * Many thanks to Ducrot Bruno for finding and fixing the last
10 * "missing link" for ICH2-M/ICH3-M support, and to Thomas Winkler
11 * for extensive testing.
12 *
13 * BIG FAT DISCLAIMER: Work in progress code. Possibly *dangerous*
14 */
15
16
17/*********************************************************************
18 * SPEEDSTEP - DEFINITIONS *
19 *********************************************************************/
20
21#include <linux/kernel.h>
22#include <linux/module.h>
23#include <linux/init.h>
24#include <linux/cpufreq.h>
25#include <linux/pci.h>
26#include <linux/sched.h>
27
28#include <asm/cpu_device_id.h>
29
30#include "speedstep-lib.h"
31
32
33/* speedstep_chipset:
34 * It is necessary to know which chipset is used. As accesses to
35 * this device occur at various places in this module, we need a
36 * static struct pci_dev * pointing to that device.
37 */
38static struct pci_dev *speedstep_chipset_dev;
39
40
41/* speedstep_processor
42 */
43static enum speedstep_processor speedstep_processor;
44
45static u32 pmbase;
46
47/*
48 * There are only two frequency states for each processor. Values
49 * are in kHz for the time being.
50 */
51static struct cpufreq_frequency_table speedstep_freqs[] = {
52    {SPEEDSTEP_HIGH, 0},
53    {SPEEDSTEP_LOW, 0},
54    {0, CPUFREQ_TABLE_END},
55};
56
57
58/**
59 * speedstep_find_register - read the PMBASE address
60 *
61 * Returns: -ENODEV if no register could be found
62 */
63static int speedstep_find_register(void)
64{
65    if (!speedstep_chipset_dev)
66        return -ENODEV;
67
68    /* get PMBASE */
69    pci_read_config_dword(speedstep_chipset_dev, 0x40, &pmbase);
70    if (!(pmbase & 0x01)) {
71        printk(KERN_ERR "speedstep-ich: could not find speedstep register\n");
72        return -ENODEV;
73    }
74
75    pmbase &= 0xFFFFFFFE;
76    if (!pmbase) {
77        printk(KERN_ERR "speedstep-ich: could not find speedstep register\n");
78        return -ENODEV;
79    }
80
81    pr_debug("pmbase is 0x%x\n", pmbase);
82    return 0;
83}
84
85/**
86 * speedstep_set_state - set the SpeedStep state
87 * @state: new processor frequency state (SPEEDSTEP_LOW or SPEEDSTEP_HIGH)
88 *
89 * Tries to change the SpeedStep state. Can be called from
90 * smp_call_function_single.
91 */
92static void speedstep_set_state(unsigned int state)
93{
94    u8 pm2_blk;
95    u8 value;
96    unsigned long flags;
97
98    if (state > 0x1)
99        return;
100
101    /* Disable IRQs */
102    local_irq_save(flags);
103
104    /* read state */
105    value = inb(pmbase + 0x50);
106
107    pr_debug("read at pmbase 0x%x + 0x50 returned 0x%x\n", pmbase, value);
108
109    /* write new state */
110    value &= 0xFE;
111    value |= state;
112
113    pr_debug("writing 0x%x to pmbase 0x%x + 0x50\n", value, pmbase);
114
115    /* Disable bus master arbitration */
116    pm2_blk = inb(pmbase + 0x20);
117    pm2_blk |= 0x01;
118    outb(pm2_blk, (pmbase + 0x20));
119
120    /* Actual transition */
121    outb(value, (pmbase + 0x50));
122
123    /* Restore bus master arbitration */
124    pm2_blk &= 0xfe;
125    outb(pm2_blk, (pmbase + 0x20));
126
127    /* check if transition was successful */
128    value = inb(pmbase + 0x50);
129
130    /* Enable IRQs */
131    local_irq_restore(flags);
132
133    pr_debug("read at pmbase 0x%x + 0x50 returned 0x%x\n", pmbase, value);
134
135    if (state == (value & 0x1))
136        pr_debug("change to %u MHz succeeded\n",
137            speedstep_get_frequency(speedstep_processor) / 1000);
138    else
139        printk(KERN_ERR "cpufreq: change failed - I/O error\n");
140
141    return;
142}
143
144/* Wrapper for smp_call_function_single. */
145static void _speedstep_set_state(void *_state)
146{
147    speedstep_set_state(*(unsigned int *)_state);
148}
149
150/**
151 * speedstep_activate - activate SpeedStep control in the chipset
152 *
153 * Tries to activate the SpeedStep status and control registers.
154 * Returns -EINVAL on an unsupported chipset, and zero on success.
155 */
156static int speedstep_activate(void)
157{
158    u16 value = 0;
159
160    if (!speedstep_chipset_dev)
161        return -EINVAL;
162
163    pci_read_config_word(speedstep_chipset_dev, 0x00A0, &value);
164    if (!(value & 0x08)) {
165        value |= 0x08;
166        pr_debug("activating SpeedStep (TM) registers\n");
167        pci_write_config_word(speedstep_chipset_dev, 0x00A0, value);
168    }
169
170    return 0;
171}
172
173
174/**
175 * speedstep_detect_chipset - detect the Southbridge which contains SpeedStep logic
176 *
177 * Detects ICH2-M, ICH3-M and ICH4-M so far. The pci_dev points to
178 * the LPC bridge / PM module which contains all power-management
179 * functions. Returns the SPEEDSTEP_CHIPSET_-number for the detected
180 * chipset, or zero on failure.
181 */
182static unsigned int speedstep_detect_chipset(void)
183{
184    speedstep_chipset_dev = pci_get_subsys(PCI_VENDOR_ID_INTEL,
185                  PCI_DEVICE_ID_INTEL_82801DB_12,
186                  PCI_ANY_ID, PCI_ANY_ID,
187                  NULL);
188    if (speedstep_chipset_dev)
189        return 4; /* 4-M */
190
191    speedstep_chipset_dev = pci_get_subsys(PCI_VENDOR_ID_INTEL,
192                  PCI_DEVICE_ID_INTEL_82801CA_12,
193                  PCI_ANY_ID, PCI_ANY_ID,
194                  NULL);
195    if (speedstep_chipset_dev)
196        return 3; /* 3-M */
197
198
199    speedstep_chipset_dev = pci_get_subsys(PCI_VENDOR_ID_INTEL,
200                  PCI_DEVICE_ID_INTEL_82801BA_10,
201                  PCI_ANY_ID, PCI_ANY_ID,
202                  NULL);
203    if (speedstep_chipset_dev) {
204        /* speedstep.c causes lockups on Dell Inspirons 8000 and
205         * 8100 which use a pretty old revision of the 82815
206         * host bridge. Abort on these systems.
207         */
208        static struct pci_dev *hostbridge;
209
210        hostbridge = pci_get_subsys(PCI_VENDOR_ID_INTEL,
211                  PCI_DEVICE_ID_INTEL_82815_MC,
212                  PCI_ANY_ID, PCI_ANY_ID,
213                  NULL);
214
215        if (!hostbridge)
216            return 2; /* 2-M */
217
218        if (hostbridge->revision < 5) {
219            pr_debug("hostbridge does not support speedstep\n");
220            speedstep_chipset_dev = NULL;
221            pci_dev_put(hostbridge);
222            return 0;
223        }
224
225        pci_dev_put(hostbridge);
226        return 2; /* 2-M */
227    }
228
229    return 0;
230}
231
232static void get_freq_data(void *_speed)
233{
234    unsigned int *speed = _speed;
235
236    *speed = speedstep_get_frequency(speedstep_processor);
237}
238
239static unsigned int speedstep_get(unsigned int cpu)
240{
241    unsigned int speed;
242
243    /* You're supposed to ensure CPU is online. */
244    if (smp_call_function_single(cpu, get_freq_data, &speed, 1) != 0)
245        BUG();
246
247    pr_debug("detected %u kHz as current frequency\n", speed);
248    return speed;
249}
250
251/**
252 * speedstep_target - set a new CPUFreq policy
253 * @policy: new policy
254 * @target_freq: the target frequency
255 * @relation: how that frequency relates to achieved frequency
256 * (CPUFREQ_RELATION_L or CPUFREQ_RELATION_H)
257 *
258 * Sets a new CPUFreq policy.
259 */
260static int speedstep_target(struct cpufreq_policy *policy,
261                 unsigned int target_freq,
262                 unsigned int relation)
263{
264    unsigned int newstate = 0, policy_cpu;
265    struct cpufreq_freqs freqs;
266    int i;
267
268    if (cpufreq_frequency_table_target(policy, &speedstep_freqs[0],
269                target_freq, relation, &newstate))
270        return -EINVAL;
271
272    policy_cpu = cpumask_any_and(policy->cpus, cpu_online_mask);
273    freqs.old = speedstep_get(policy_cpu);
274    freqs.new = speedstep_freqs[newstate].frequency;
275    freqs.cpu = policy->cpu;
276
277    pr_debug("transiting from %u to %u kHz\n", freqs.old, freqs.new);
278
279    /* no transition necessary */
280    if (freqs.old == freqs.new)
281        return 0;
282
283    for_each_cpu(i, policy->cpus) {
284        freqs.cpu = i;
285        cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
286    }
287
288    smp_call_function_single(policy_cpu, _speedstep_set_state, &newstate,
289                 true);
290
291    for_each_cpu(i, policy->cpus) {
292        freqs.cpu = i;
293        cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
294    }
295
296    return 0;
297}
298
299
300/**
301 * speedstep_verify - verifies a new CPUFreq policy
302 * @policy: new policy
303 *
304 * Limit must be within speedstep_low_freq and speedstep_high_freq, with
305 * at least one border included.
306 */
307static int speedstep_verify(struct cpufreq_policy *policy)
308{
309    return cpufreq_frequency_table_verify(policy, &speedstep_freqs[0]);
310}
311
312struct get_freqs {
313    struct cpufreq_policy *policy;
314    int ret;
315};
316
317static void get_freqs_on_cpu(void *_get_freqs)
318{
319    struct get_freqs *get_freqs = _get_freqs;
320
321    get_freqs->ret =
322        speedstep_get_freqs(speedstep_processor,
323                &speedstep_freqs[SPEEDSTEP_LOW].frequency,
324                &speedstep_freqs[SPEEDSTEP_HIGH].frequency,
325                &get_freqs->policy->cpuinfo.transition_latency,
326                &speedstep_set_state);
327}
328
329static int speedstep_cpu_init(struct cpufreq_policy *policy)
330{
331    int result;
332    unsigned int policy_cpu, speed;
333    struct get_freqs gf;
334
335    /* only run on CPU to be set, or on its sibling */
336#ifdef CONFIG_SMP
337    cpumask_copy(policy->cpus, cpu_sibling_mask(policy->cpu));
338#endif
339    policy_cpu = cpumask_any_and(policy->cpus, cpu_online_mask);
340
341    /* detect low and high frequency and transition latency */
342    gf.policy = policy;
343    smp_call_function_single(policy_cpu, get_freqs_on_cpu, &gf, 1);
344    if (gf.ret)
345        return gf.ret;
346
347    /* get current speed setting */
348    speed = speedstep_get(policy_cpu);
349    if (!speed)
350        return -EIO;
351
352    pr_debug("currently at %s speed setting - %i MHz\n",
353        (speed == speedstep_freqs[SPEEDSTEP_LOW].frequency)
354        ? "low" : "high",
355        (speed / 1000));
356
357    /* cpuinfo and default policy values */
358    policy->cur = speed;
359
360    result = cpufreq_frequency_table_cpuinfo(policy, speedstep_freqs);
361    if (result)
362        return result;
363
364    cpufreq_frequency_table_get_attr(speedstep_freqs, policy->cpu);
365
366    return 0;
367}
368
369
370static int speedstep_cpu_exit(struct cpufreq_policy *policy)
371{
372    cpufreq_frequency_table_put_attr(policy->cpu);
373    return 0;
374}
375
376static struct freq_attr *speedstep_attr[] = {
377    &cpufreq_freq_attr_scaling_available_freqs,
378    NULL,
379};
380
381
382static struct cpufreq_driver speedstep_driver = {
383    .name = "speedstep-ich",
384    .verify = speedstep_verify,
385    .target = speedstep_target,
386    .init = speedstep_cpu_init,
387    .exit = speedstep_cpu_exit,
388    .get = speedstep_get,
389    .owner = THIS_MODULE,
390    .attr = speedstep_attr,
391};
392
393static const struct x86_cpu_id ss_smi_ids[] = {
394    { X86_VENDOR_INTEL, 6, 0xb, },
395    { X86_VENDOR_INTEL, 6, 0x8, },
396    { X86_VENDOR_INTEL, 15, 2 },
397    {}
398};
399#if 0
400/* Autoload or not? Do not for now. */
401MODULE_DEVICE_TABLE(x86cpu, ss_smi_ids);
402#endif
403
404/**
405 * speedstep_init - initializes the SpeedStep CPUFreq driver
406 *
407 * Initializes the SpeedStep support. Returns -ENODEV on unsupported
408 * devices, -EINVAL on problems during initiatization, and zero on
409 * success.
410 */
411static int __init speedstep_init(void)
412{
413    if (!x86_match_cpu(ss_smi_ids))
414        return -ENODEV;
415
416    /* detect processor */
417    speedstep_processor = speedstep_detect_processor();
418    if (!speedstep_processor) {
419        pr_debug("Intel(R) SpeedStep(TM) capable processor "
420                "not found\n");
421        return -ENODEV;
422    }
423
424    /* detect chipset */
425    if (!speedstep_detect_chipset()) {
426        pr_debug("Intel(R) SpeedStep(TM) for this chipset not "
427                "(yet) available.\n");
428        return -ENODEV;
429    }
430
431    /* activate speedstep support */
432    if (speedstep_activate()) {
433        pci_dev_put(speedstep_chipset_dev);
434        return -EINVAL;
435    }
436
437    if (speedstep_find_register())
438        return -ENODEV;
439
440    return cpufreq_register_driver(&speedstep_driver);
441}
442
443
444/**
445 * speedstep_exit - unregisters SpeedStep support
446 *
447 * Unregisters SpeedStep support.
448 */
449static void __exit speedstep_exit(void)
450{
451    pci_dev_put(speedstep_chipset_dev);
452    cpufreq_unregister_driver(&speedstep_driver);
453}
454
455
456MODULE_AUTHOR("Dave Jones <davej@redhat.com>, "
457        "Dominik Brodowski <linux@brodo.de>");
458MODULE_DESCRIPTION("Speedstep driver for Intel mobile processors on chipsets "
459        "with ICH-M southbridges.");
460MODULE_LICENSE("GPL");
461
462module_init(speedstep_init);
463module_exit(speedstep_exit);
464

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