Root/drivers/edac/Kconfig

1#
2# EDAC Kconfig
3# Copyright (c) 2008 Doug Thompson www.softwarebitmaker.com
4# Licensed and distributed under the GPL
5#
6
7menuconfig EDAC
8    bool "EDAC (Error Detection And Correction) reporting"
9    depends on HAS_IOMEM
10    depends on X86 || PPC || TILE || ARM
11    help
12      EDAC is designed to report errors in the core system.
13      These are low-level errors that are reported in the CPU or
14      supporting chipset or other subsystems:
15      memory errors, cache errors, PCI errors, thermal throttling, etc..
16      If unsure, select 'Y'.
17
18      If this code is reporting problems on your system, please
19      see the EDAC project web pages for more information at:
20
21      <http://bluesmoke.sourceforge.net/>
22
23      and:
24
25      <http://buttersideup.com/edacwiki>
26
27      There is also a mailing list for the EDAC project, which can
28      be found via the sourceforge page.
29
30if EDAC
31
32comment "Reporting subsystems"
33
34config EDAC_LEGACY_SYSFS
35    bool "EDAC legacy sysfs"
36    default y
37    help
38      Enable the compatibility sysfs nodes.
39      Use 'Y' if your edac utilities aren't ported to work with the newer
40      structures.
41
42config EDAC_DEBUG
43    bool "Debugging"
44    help
45      This turns on debugging information for the entire EDAC
46      sub-system. You can insert module with "debug_level=x", current
47      there're four debug levels (x=0,1,2,3 from low to high).
48      Usually you should select 'N'.
49
50config EDAC_DECODE_MCE
51    tristate "Decode MCEs in human-readable form (only on AMD for now)"
52    depends on CPU_SUP_AMD && X86_MCE_AMD
53    default y
54    ---help---
55      Enable this option if you want to decode Machine Check Exceptions
56      occurring on your machine in human-readable form.
57
58      You should definitely say Y here in case you want to decode MCEs
59      which occur really early upon boot, before the module infrastructure
60      has been initialized.
61
62config EDAC_MCE_INJ
63    tristate "Simple MCE injection interface over /sysfs"
64    depends on EDAC_DECODE_MCE
65    default n
66    help
67      This is a simple interface to inject MCEs over /sysfs and test
68      the MCE decoding code in EDAC.
69
70      This is currently AMD-only.
71
72config EDAC_MM_EDAC
73    tristate "Main Memory EDAC (Error Detection And Correction) reporting"
74    help
75      Some systems are able to detect and correct errors in main
76      memory. EDAC can report statistics on memory error
77      detection and correction (EDAC - or commonly referred to ECC
78      errors). EDAC will also try to decode where these errors
79      occurred so that a particular failing memory module can be
80      replaced. If unsure, select 'Y'.
81
82config EDAC_AMD64
83    tristate "AMD64 (Opteron, Athlon64) K8, F10h"
84    depends on EDAC_MM_EDAC && AMD_NB && X86_64 && EDAC_DECODE_MCE
85    help
86      Support for error detection and correction of DRAM ECC errors on
87      the AMD64 families of memory controllers (K8 and F10h)
88
89config EDAC_AMD64_ERROR_INJECTION
90    bool "Sysfs HW Error injection facilities"
91    depends on EDAC_AMD64
92    help
93      Recent Opterons (Family 10h and later) provide for Memory Error
94      Injection into the ECC detection circuits. The amd64_edac module
95      allows the operator/user to inject Uncorrectable and Correctable
96      errors into DRAM.
97
98      When enabled, in each of the respective memory controller directories
99      (/sys/devices/system/edac/mc/mcX), there are 3 input files:
100
101      - inject_section (0..3, 16-byte section of 64-byte cacheline),
102      - inject_word (0..8, 16-bit word of 16-byte section),
103      - inject_ecc_vector (hex ecc vector: select bits of inject word)
104
105      In addition, there are two control files, inject_read and inject_write,
106      which trigger the DRAM ECC Read and Write respectively.
107
108config EDAC_AMD76X
109    tristate "AMD 76x (760, 762, 768)"
110    depends on EDAC_MM_EDAC && PCI && X86_32
111    help
112      Support for error detection and correction on the AMD 76x
113      series of chipsets used with the Athlon processor.
114
115config EDAC_E7XXX
116    tristate "Intel e7xxx (e7205, e7500, e7501, e7505)"
117    depends on EDAC_MM_EDAC && PCI && X86_32
118    help
119      Support for error detection and correction on the Intel
120      E7205, E7500, E7501 and E7505 server chipsets.
121
122config EDAC_E752X
123    tristate "Intel e752x (e7520, e7525, e7320) and 3100"
124    depends on EDAC_MM_EDAC && PCI && X86 && HOTPLUG
125    help
126      Support for error detection and correction on the Intel
127      E7520, E7525, E7320 server chipsets.
128
129config EDAC_I82443BXGX
130    tristate "Intel 82443BX/GX (440BX/GX)"
131    depends on EDAC_MM_EDAC && PCI && X86_32
132    depends on BROKEN
133    help
134      Support for error detection and correction on the Intel
135      82443BX/GX memory controllers (440BX/GX chipsets).
136
137config EDAC_I82875P
138    tristate "Intel 82875p (D82875P, E7210)"
139    depends on EDAC_MM_EDAC && PCI && X86_32
140    help
141      Support for error detection and correction on the Intel
142      DP82785P and E7210 server chipsets.
143
144config EDAC_I82975X
145    tristate "Intel 82975x (D82975x)"
146    depends on EDAC_MM_EDAC && PCI && X86
147    help
148      Support for error detection and correction on the Intel
149      DP82975x server chipsets.
150
151config EDAC_I3000
152    tristate "Intel 3000/3010"
153    depends on EDAC_MM_EDAC && PCI && X86
154    help
155      Support for error detection and correction on the Intel
156      3000 and 3010 server chipsets.
157
158config EDAC_I3200
159    tristate "Intel 3200"
160    depends on EDAC_MM_EDAC && PCI && X86 && EXPERIMENTAL
161    help
162      Support for error detection and correction on the Intel
163      3200 and 3210 server chipsets.
164
165config EDAC_X38
166    tristate "Intel X38"
167    depends on EDAC_MM_EDAC && PCI && X86
168    help
169      Support for error detection and correction on the Intel
170      X38 server chipsets.
171
172config EDAC_I5400
173    tristate "Intel 5400 (Seaburg) chipsets"
174    depends on EDAC_MM_EDAC && PCI && X86
175    help
176      Support for error detection and correction the Intel
177      i5400 MCH chipset (Seaburg).
178
179config EDAC_I7CORE
180    tristate "Intel i7 Core (Nehalem) processors"
181    depends on EDAC_MM_EDAC && PCI && X86 && X86_MCE_INTEL
182    help
183      Support for error detection and correction the Intel
184      i7 Core (Nehalem) Integrated Memory Controller that exists on
185      newer processors like i7 Core, i7 Core Extreme, Xeon 35xx
186      and Xeon 55xx processors.
187
188config EDAC_I82860
189    tristate "Intel 82860"
190    depends on EDAC_MM_EDAC && PCI && X86_32
191    help
192      Support for error detection and correction on the Intel
193      82860 chipset.
194
195config EDAC_R82600
196    tristate "Radisys 82600 embedded chipset"
197    depends on EDAC_MM_EDAC && PCI && X86_32
198    help
199      Support for error detection and correction on the Radisys
200      82600 embedded chipset.
201
202config EDAC_I5000
203    tristate "Intel Greencreek/Blackford chipset"
204    depends on EDAC_MM_EDAC && X86 && PCI
205    help
206      Support for error detection and correction the Intel
207      Greekcreek/Blackford chipsets.
208
209config EDAC_I5100
210    tristate "Intel San Clemente MCH"
211    depends on EDAC_MM_EDAC && X86 && PCI
212    help
213      Support for error detection and correction the Intel
214      San Clemente MCH.
215
216config EDAC_I7300
217    tristate "Intel Clarksboro MCH"
218    depends on EDAC_MM_EDAC && X86 && PCI
219    help
220      Support for error detection and correction the Intel
221      Clarksboro MCH (Intel 7300 chipset).
222
223config EDAC_SBRIDGE
224    tristate "Intel Sandy-Bridge Integrated MC"
225    depends on EDAC_MM_EDAC && PCI && X86_64 && X86_MCE_INTEL
226    depends on PCI_MMCONFIG && EXPERIMENTAL
227    help
228      Support for error detection and correction the Intel
229      Sandy Bridge Integrated Memory Controller.
230
231config EDAC_MPC85XX
232    tristate "Freescale MPC83xx / MPC85xx"
233    depends on EDAC_MM_EDAC && FSL_SOC && (PPC_83xx || PPC_85xx)
234    help
235      Support for error detection and correction on the Freescale
236      MPC8349, MPC8560, MPC8540, MPC8548
237
238config EDAC_MV64X60
239    tristate "Marvell MV64x60"
240    depends on EDAC_MM_EDAC && MV64X60
241    help
242      Support for error detection and correction on the Marvell
243      MV64360 and MV64460 chipsets.
244
245config EDAC_PASEMI
246    tristate "PA Semi PWRficient"
247    depends on EDAC_MM_EDAC && PCI
248    depends on PPC_PASEMI
249    help
250      Support for error detection and correction on PA Semi
251      PWRficient.
252
253config EDAC_CELL
254    tristate "Cell Broadband Engine memory controller"
255    depends on EDAC_MM_EDAC && PPC_CELL_COMMON
256    help
257      Support for error detection and correction on the
258      Cell Broadband Engine internal memory controller
259      on platform without a hypervisor
260
261config EDAC_PPC4XX
262    tristate "PPC4xx IBM DDR2 Memory Controller"
263    depends on EDAC_MM_EDAC && 4xx
264    help
265      This enables support for EDAC on the ECC memory used
266      with the IBM DDR2 memory controller found in various
267      PowerPC 4xx embedded processors such as the 405EX[r],
268      440SP, 440SPe, 460EX, 460GT and 460SX.
269
270config EDAC_AMD8131
271    tristate "AMD8131 HyperTransport PCI-X Tunnel"
272    depends on EDAC_MM_EDAC && PCI && PPC_MAPLE
273    help
274      Support for error detection and correction on the
275      AMD8131 HyperTransport PCI-X Tunnel chip.
276      Note, add more Kconfig dependency if it's adopted
277      on some machine other than Maple.
278
279config EDAC_AMD8111
280    tristate "AMD8111 HyperTransport I/O Hub"
281    depends on EDAC_MM_EDAC && PCI && PPC_MAPLE
282    help
283      Support for error detection and correction on the
284      AMD8111 HyperTransport I/O Hub chip.
285      Note, add more Kconfig dependency if it's adopted
286      on some machine other than Maple.
287
288config EDAC_CPC925
289    tristate "IBM CPC925 Memory Controller (PPC970FX)"
290    depends on EDAC_MM_EDAC && PPC64
291    help
292      Support for error detection and correction on the
293      IBM CPC925 Bridge and Memory Controller, which is
294      a companion chip to the PowerPC 970 family of
295      processors.
296
297config EDAC_TILE
298    tristate "Tilera Memory Controller"
299    depends on EDAC_MM_EDAC && TILE
300    default y
301    help
302      Support for error detection and correction on the
303      Tilera memory controller.
304
305config EDAC_HIGHBANK_MC
306    tristate "Highbank Memory Controller"
307    depends on EDAC_MM_EDAC && ARCH_HIGHBANK
308    help
309      Support for error detection and correction on the
310      Calxeda Highbank memory controller.
311
312config EDAC_HIGHBANK_L2
313    tristate "Highbank L2 Cache"
314    depends on EDAC_MM_EDAC && ARCH_HIGHBANK
315    help
316      Support for error detection and correction on the
317      Calxeda Highbank memory controller.
318
319endif # EDAC
320

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