Root/drivers/edac/edac_core.h

1/*
2 * Defines, structures, APIs for edac_core module
3 *
4 * (C) 2007 Linux Networx (http://lnxi.com)
5 * This file may be distributed under the terms of the
6 * GNU General Public License.
7 *
8 * Written by Thayne Harbaugh
9 * Based on work by Dan Hollis <goemon at anime dot net> and others.
10 * http://www.anime.net/~goemon/linux-ecc/
11 *
12 * NMI handling support added by
13 * Dave Peterson <dsp@llnl.gov> <dave_peterson@pobox.com>
14 *
15 * Refactored for multi-source files:
16 * Doug Thompson <norsk5@xmission.com>
17 *
18 */
19
20#ifndef _EDAC_CORE_H_
21#define _EDAC_CORE_H_
22
23#include <linux/kernel.h>
24#include <linux/types.h>
25#include <linux/module.h>
26#include <linux/spinlock.h>
27#include <linux/smp.h>
28#include <linux/pci.h>
29#include <linux/time.h>
30#include <linux/nmi.h>
31#include <linux/rcupdate.h>
32#include <linux/completion.h>
33#include <linux/kobject.h>
34#include <linux/platform_device.h>
35#include <linux/workqueue.h>
36#include <linux/edac.h>
37
38#define EDAC_DEVICE_NAME_LEN 31
39#define EDAC_ATTRIB_VALUE_LEN 15
40
41#if PAGE_SHIFT < 20
42#define PAGES_TO_MiB(pages) ((pages) >> (20 - PAGE_SHIFT))
43#define MiB_TO_PAGES(mb) ((mb) << (20 - PAGE_SHIFT))
44#else /* PAGE_SHIFT > 20 */
45#define PAGES_TO_MiB(pages) ((pages) << (PAGE_SHIFT - 20))
46#define MiB_TO_PAGES(mb) ((mb) >> (PAGE_SHIFT - 20))
47#endif
48
49#define edac_printk(level, prefix, fmt, arg...) \
50    printk(level "EDAC " prefix ": " fmt, ##arg)
51
52#define edac_mc_printk(mci, level, fmt, arg...) \
53    printk(level "EDAC MC%d: " fmt, mci->mc_idx, ##arg)
54
55#define edac_mc_chipset_printk(mci, level, prefix, fmt, arg...) \
56    printk(level "EDAC " prefix " MC%d: " fmt, mci->mc_idx, ##arg)
57
58#define edac_device_printk(ctl, level, fmt, arg...) \
59    printk(level "EDAC DEVICE%d: " fmt, ctl->dev_idx, ##arg)
60
61#define edac_pci_printk(ctl, level, fmt, arg...) \
62    printk(level "EDAC PCI%d: " fmt, ctl->pci_idx, ##arg)
63
64/* prefixes for edac_printk() and edac_mc_printk() */
65#define EDAC_MC "MC"
66#define EDAC_PCI "PCI"
67#define EDAC_DEBUG "DEBUG"
68
69extern const char *edac_mem_types[];
70
71#ifdef CONFIG_EDAC_DEBUG
72extern int edac_debug_level;
73
74#define edac_dbg(level, fmt, ...) \
75do { \
76    if (level <= edac_debug_level) \
77        edac_printk(KERN_DEBUG, EDAC_DEBUG, \
78                "%s: " fmt, __func__, ##__VA_ARGS__); \
79} while (0)
80
81#else /* !CONFIG_EDAC_DEBUG */
82
83#define edac_dbg(level, fmt, ...) \
84do { \
85    if (0) \
86        edac_printk(KERN_DEBUG, EDAC_DEBUG, \
87                "%s: " fmt, __func__, ##__VA_ARGS__); \
88} while (0)
89
90#endif /* !CONFIG_EDAC_DEBUG */
91
92#define PCI_VEND_DEV(vend, dev) PCI_VENDOR_ID_ ## vend, \
93    PCI_DEVICE_ID_ ## vend ## _ ## dev
94
95#define edac_dev_name(dev) (dev)->dev_name
96
97/*
98 * The following are the structures to provide for a generic
99 * or abstract 'edac_device'. This set of structures and the
100 * code that implements the APIs for the same, provide for
101 * registering EDAC type devices which are NOT standard memory.
102 *
103 * CPU caches (L1 and L2)
104 * DMA engines
105 * Core CPU switches
106 * Fabric switch units
107 * PCIe interface controllers
108 * other EDAC/ECC type devices that can be monitored for
109 * errors, etc.
110 *
111 * It allows for a 2 level set of hierarchy. For example:
112 *
113 * cache could be composed of L1, L2 and L3 levels of cache.
114 * Each CPU core would have its own L1 cache, while sharing
115 * L2 and maybe L3 caches.
116 *
117 * View them arranged, via the sysfs presentation:
118 * /sys/devices/system/edac/..
119 *
120 * mc/ <existing memory device directory>
121 * cpu/cpu0/.. <L1 and L2 block directory>
122 * /L1-cache/ce_count
123 * /ue_count
124 * /L2-cache/ce_count
125 * /ue_count
126 * cpu/cpu1/.. <L1 and L2 block directory>
127 * /L1-cache/ce_count
128 * /ue_count
129 * /L2-cache/ce_count
130 * /ue_count
131 * ...
132 *
133 * the L1 and L2 directories would be "edac_device_block's"
134 */
135
136struct edac_device_counter {
137    u32 ue_count;
138    u32 ce_count;
139};
140
141/* forward reference */
142struct edac_device_ctl_info;
143struct edac_device_block;
144
145/* edac_dev_sysfs_attribute structure
146 * used for driver sysfs attributes in mem_ctl_info
147 * for extra controls and attributes:
148 * like high level error Injection controls
149 */
150struct edac_dev_sysfs_attribute {
151    struct attribute attr;
152    ssize_t (*show)(struct edac_device_ctl_info *, char *);
153    ssize_t (*store)(struct edac_device_ctl_info *, const char *, size_t);
154};
155
156/* edac_dev_sysfs_block_attribute structure
157 *
158 * used in leaf 'block' nodes for adding controls/attributes
159 *
160 * each block in each instance of the containing control structure
161 * can have an array of the following. The show and store functions
162 * will be filled in with the show/store function in the
163 * low level driver.
164 *
165 * The 'value' field will be the actual value field used for
166 * counting
167 */
168struct edac_dev_sysfs_block_attribute {
169    struct attribute attr;
170    ssize_t (*show)(struct kobject *, struct attribute *, char *);
171    ssize_t (*store)(struct kobject *, struct attribute *,
172            const char *, size_t);
173    struct edac_device_block *block;
174
175    unsigned int value;
176};
177
178/* device block control structure */
179struct edac_device_block {
180    struct edac_device_instance *instance; /* Up Pointer */
181    char name[EDAC_DEVICE_NAME_LEN + 1];
182
183    struct edac_device_counter counters; /* basic UE and CE counters */
184
185    int nr_attribs; /* how many attributes */
186
187    /* this block's attributes, could be NULL */
188    struct edac_dev_sysfs_block_attribute *block_attributes;
189
190    /* edac sysfs device control */
191    struct kobject kobj;
192};
193
194/* device instance control structure */
195struct edac_device_instance {
196    struct edac_device_ctl_info *ctl; /* Up pointer */
197    char name[EDAC_DEVICE_NAME_LEN + 4];
198
199    struct edac_device_counter counters; /* instance counters */
200
201    u32 nr_blocks; /* how many blocks */
202    struct edac_device_block *blocks; /* block array */
203
204    /* edac sysfs device control */
205    struct kobject kobj;
206};
207
208
209/*
210 * Abstract edac_device control info structure
211 *
212 */
213struct edac_device_ctl_info {
214    /* for global list of edac_device_ctl_info structs */
215    struct list_head link;
216
217    struct module *owner; /* Module owner of this control struct */
218
219    int dev_idx;
220
221    /* Per instance controls for this edac_device */
222    int log_ue; /* boolean for logging UEs */
223    int log_ce; /* boolean for logging CEs */
224    int panic_on_ue; /* boolean for panic'ing on an UE */
225    unsigned poll_msec; /* number of milliseconds to poll interval */
226    unsigned long delay; /* number of jiffies for poll_msec */
227
228    /* Additional top controller level attributes, but specified
229     * by the low level driver.
230     *
231     * Set by the low level driver to provide attributes at the
232     * controller level, same level as 'ue_count' and 'ce_count' above.
233     * An array of structures, NULL terminated
234     *
235     * If attributes are desired, then set to array of attributes
236     * If no attributes are desired, leave NULL
237     */
238    struct edac_dev_sysfs_attribute *sysfs_attributes;
239
240    /* pointer to main 'edac' subsys in sysfs */
241    struct bus_type *edac_subsys;
242
243    /* the internal state of this controller instance */
244    int op_state;
245    /* work struct for this instance */
246    struct delayed_work work;
247
248    /* pointer to edac polling checking routine:
249     * If NOT NULL: points to polling check routine
250     * If NULL: Then assumes INTERRUPT operation, where
251     * MC driver will receive events
252     */
253    void (*edac_check) (struct edac_device_ctl_info * edac_dev);
254
255    struct device *dev; /* pointer to device structure */
256
257    const char *mod_name; /* module name */
258    const char *ctl_name; /* edac controller name */
259    const char *dev_name; /* pci/platform/etc... name */
260
261    void *pvt_info; /* pointer to 'private driver' info */
262
263    unsigned long start_time; /* edac_device load start time (jiffies) */
264
265    struct completion removal_complete;
266
267    /* sysfs top name under 'edac' directory
268     * and instance name:
269     * cpu/cpu0/...
270     * cpu/cpu1/...
271     * cpu/cpu2/...
272     * ...
273     */
274    char name[EDAC_DEVICE_NAME_LEN + 1];
275
276    /* Number of instances supported on this control structure
277     * and the array of those instances
278     */
279    u32 nr_instances;
280    struct edac_device_instance *instances;
281
282    /* Event counters for the this whole EDAC Device */
283    struct edac_device_counter counters;
284
285    /* edac sysfs device control for the 'name'
286     * device this structure controls
287     */
288    struct kobject kobj;
289};
290
291/* To get from the instance's wq to the beginning of the ctl structure */
292#define to_edac_mem_ctl_work(w) \
293        container_of(w, struct mem_ctl_info, work)
294
295#define to_edac_device_ctl_work(w) \
296        container_of(w,struct edac_device_ctl_info,work)
297
298/*
299 * The alloc() and free() functions for the 'edac_device' control info
300 * structure. A MC driver will allocate one of these for each edac_device
301 * it is going to control/register with the EDAC CORE.
302 */
303extern struct edac_device_ctl_info *edac_device_alloc_ctl_info(
304        unsigned sizeof_private,
305        char *edac_device_name, unsigned nr_instances,
306        char *edac_block_name, unsigned nr_blocks,
307        unsigned offset_value,
308        struct edac_dev_sysfs_block_attribute *block_attributes,
309        unsigned nr_attribs,
310        int device_index);
311
312/* The offset value can be:
313 * -1 indicating no offset value
314 * 0 for zero-based block numbers
315 * 1 for 1-based block number
316 * other for other-based block number
317 */
318#define BLOCK_OFFSET_VALUE_OFF ((unsigned) -1)
319
320extern void edac_device_free_ctl_info(struct edac_device_ctl_info *ctl_info);
321
322#ifdef CONFIG_PCI
323
324struct edac_pci_counter {
325    atomic_t pe_count;
326    atomic_t npe_count;
327};
328
329/*
330 * Abstract edac_pci control info structure
331 *
332 */
333struct edac_pci_ctl_info {
334    /* for global list of edac_pci_ctl_info structs */
335    struct list_head link;
336
337    int pci_idx;
338
339    struct bus_type *edac_subsys; /* pointer to subsystem */
340
341    /* the internal state of this controller instance */
342    int op_state;
343    /* work struct for this instance */
344    struct delayed_work work;
345
346    /* pointer to edac polling checking routine:
347     * If NOT NULL: points to polling check routine
348     * If NULL: Then assumes INTERRUPT operation, where
349     * MC driver will receive events
350     */
351    void (*edac_check) (struct edac_pci_ctl_info * edac_dev);
352
353    struct device *dev; /* pointer to device structure */
354
355    const char *mod_name; /* module name */
356    const char *ctl_name; /* edac controller name */
357    const char *dev_name; /* pci/platform/etc... name */
358
359    void *pvt_info; /* pointer to 'private driver' info */
360
361    unsigned long start_time; /* edac_pci load start time (jiffies) */
362
363    struct completion complete;
364
365    /* sysfs top name under 'edac' directory
366     * and instance name:
367     * cpu/cpu0/...
368     * cpu/cpu1/...
369     * cpu/cpu2/...
370     * ...
371     */
372    char name[EDAC_DEVICE_NAME_LEN + 1];
373
374    /* Event counters for the this whole EDAC Device */
375    struct edac_pci_counter counters;
376
377    /* edac sysfs device control for the 'name'
378     * device this structure controls
379     */
380    struct kobject kobj;
381    struct completion kobj_complete;
382};
383
384#define to_edac_pci_ctl_work(w) \
385        container_of(w, struct edac_pci_ctl_info,work)
386
387/* write all or some bits in a byte-register*/
388static inline void pci_write_bits8(struct pci_dev *pdev, int offset, u8 value,
389                   u8 mask)
390{
391    if (mask != 0xff) {
392        u8 buf;
393
394        pci_read_config_byte(pdev, offset, &buf);
395        value &= mask;
396        buf &= ~mask;
397        value |= buf;
398    }
399
400    pci_write_config_byte(pdev, offset, value);
401}
402
403/* write all or some bits in a word-register*/
404static inline void pci_write_bits16(struct pci_dev *pdev, int offset,
405                    u16 value, u16 mask)
406{
407    if (mask != 0xffff) {
408        u16 buf;
409
410        pci_read_config_word(pdev, offset, &buf);
411        value &= mask;
412        buf &= ~mask;
413        value |= buf;
414    }
415
416    pci_write_config_word(pdev, offset, value);
417}
418
419/*
420 * pci_write_bits32
421 *
422 * edac local routine to do pci_write_config_dword, but adds
423 * a mask parameter. If mask is all ones, ignore the mask.
424 * Otherwise utilize the mask to isolate specified bits
425 *
426 * write all or some bits in a dword-register
427 */
428static inline void pci_write_bits32(struct pci_dev *pdev, int offset,
429                    u32 value, u32 mask)
430{
431    if (mask != 0xffffffff) {
432        u32 buf;
433
434        pci_read_config_dword(pdev, offset, &buf);
435        value &= mask;
436        buf &= ~mask;
437        value |= buf;
438    }
439
440    pci_write_config_dword(pdev, offset, value);
441}
442
443#endif /* CONFIG_PCI */
444
445struct mem_ctl_info *edac_mc_alloc(unsigned mc_num,
446                   unsigned n_layers,
447                   struct edac_mc_layer *layers,
448                   unsigned sz_pvt);
449extern int edac_mc_add_mc(struct mem_ctl_info *mci);
450extern void edac_mc_free(struct mem_ctl_info *mci);
451extern struct mem_ctl_info *edac_mc_find(int idx);
452extern struct mem_ctl_info *find_mci_by_dev(struct device *dev);
453extern struct mem_ctl_info *edac_mc_del_mc(struct device *dev);
454extern int edac_mc_find_csrow_by_page(struct mem_ctl_info *mci,
455                      unsigned long page);
456void edac_mc_handle_error(const enum hw_event_mc_err_type type,
457              struct mem_ctl_info *mci,
458              const u16 error_count,
459              const unsigned long page_frame_number,
460              const unsigned long offset_in_page,
461              const unsigned long syndrome,
462              const int top_layer,
463              const int mid_layer,
464              const int low_layer,
465              const char *msg,
466              const char *other_detail);
467
468/*
469 * edac_device APIs
470 */
471extern int edac_device_add_device(struct edac_device_ctl_info *edac_dev);
472extern struct edac_device_ctl_info *edac_device_del_device(struct device *dev);
473extern void edac_device_handle_ue(struct edac_device_ctl_info *edac_dev,
474                int inst_nr, int block_nr, const char *msg);
475extern void edac_device_handle_ce(struct edac_device_ctl_info *edac_dev,
476                int inst_nr, int block_nr, const char *msg);
477extern int edac_device_alloc_index(void);
478extern const char *edac_layer_name[];
479
480/*
481 * edac_pci APIs
482 */
483extern struct edac_pci_ctl_info *edac_pci_alloc_ctl_info(unsigned int sz_pvt,
484                const char *edac_pci_name);
485
486extern void edac_pci_free_ctl_info(struct edac_pci_ctl_info *pci);
487
488extern void edac_pci_reset_delay_period(struct edac_pci_ctl_info *pci,
489                unsigned long value);
490
491extern int edac_pci_alloc_index(void);
492extern int edac_pci_add_device(struct edac_pci_ctl_info *pci, int edac_idx);
493extern struct edac_pci_ctl_info *edac_pci_del_device(struct device *dev);
494
495extern struct edac_pci_ctl_info *edac_pci_create_generic_ctl(
496                struct device *dev,
497                const char *mod_name);
498
499extern void edac_pci_release_generic_ctl(struct edac_pci_ctl_info *pci);
500extern int edac_pci_create_sysfs(struct edac_pci_ctl_info *pci);
501extern void edac_pci_remove_sysfs(struct edac_pci_ctl_info *pci);
502
503/*
504 * edac misc APIs
505 */
506extern char *edac_op_state_to_string(int op_state);
507
508#endif /* _EDAC_CORE_H_ */
509

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