Root/drivers/edac/ppc4xx_edac.c

1/*
2 * Copyright (c) 2008 Nuovation System Designs, LLC
3 * Grant Erickson <gerickson@nuovations.com>
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation; version 2 of the
8 * License.
9 *
10 */
11
12#include <linux/edac.h>
13#include <linux/interrupt.h>
14#include <linux/irq.h>
15#include <linux/kernel.h>
16#include <linux/mm.h>
17#include <linux/module.h>
18#include <linux/of_device.h>
19#include <linux/of_platform.h>
20#include <linux/types.h>
21
22#include <asm/dcr.h>
23
24#include "edac_core.h"
25#include "ppc4xx_edac.h"
26
27/*
28 * This file implements a driver for monitoring and handling events
29 * associated with the IMB DDR2 ECC controller found in the AMCC/IBM
30 * 405EX[r], 440SP, 440SPe, 460EX, 460GT and 460SX.
31 *
32 * As realized in the 405EX[r], this controller features:
33 *
34 * - Support for registered- and non-registered DDR1 and DDR2 memory.
35 * - 32-bit or 16-bit memory interface with optional ECC.
36 *
37 * o ECC support includes:
38 *
39 * - 4-bit SEC/DED
40 * - Aligned-nibble error detect
41 * - Bypass mode
42 *
43 * - Two (2) memory banks/ranks.
44 * - Up to 1 GiB per bank/rank in 32-bit mode and up to 512 MiB per
45 * bank/rank in 16-bit mode.
46 *
47 * As realized in the 440SP and 440SPe, this controller changes/adds:
48 *
49 * - 64-bit or 32-bit memory interface with optional ECC.
50 *
51 * o ECC support includes:
52 *
53 * - 8-bit SEC/DED
54 * - Aligned-nibble error detect
55 * - Bypass mode
56 *
57 * - Up to 4 GiB per bank/rank in 64-bit mode and up to 2 GiB
58 * per bank/rank in 32-bit mode.
59 *
60 * As realized in the 460EX and 460GT, this controller changes/adds:
61 *
62 * - 64-bit or 32-bit memory interface with optional ECC.
63 *
64 * o ECC support includes:
65 *
66 * - 8-bit SEC/DED
67 * - Aligned-nibble error detect
68 * - Bypass mode
69 *
70 * - Four (4) memory banks/ranks.
71 * - Up to 16 GiB per bank/rank in 64-bit mode and up to 8 GiB
72 * per bank/rank in 32-bit mode.
73 *
74 * At present, this driver has ONLY been tested against the controller
75 * realization in the 405EX[r] on the AMCC Kilauea and Haleakala
76 * boards (256 MiB w/o ECC memory soldered onto the board) and a
77 * proprietary board based on those designs (128 MiB ECC memory, also
78 * soldered onto the board).
79 *
80 * Dynamic feature detection and handling needs to be added for the
81 * other realizations of this controller listed above.
82 *
83 * Eventually, this driver will likely be adapted to the above variant
84 * realizations of this controller as well as broken apart to handle
85 * the other known ECC-capable controllers prevalent in other 4xx
86 * processors:
87 *
88 * - IBM SDRAM (405GP, 405CR and 405EP) "ibm,sdram-4xx"
89 * - IBM DDR1 (440GP, 440GX, 440EP and 440GR) "ibm,sdram-4xx-ddr"
90 * - Denali DDR1/DDR2 (440EPX and 440GRX) "denali,sdram-4xx-ddr2"
91 *
92 * For this controller, unfortunately, correctable errors report
93 * nothing more than the beat/cycle and byte/lane the correction
94 * occurred on and the check bit group that covered the error.
95 *
96 * In contrast, uncorrectable errors also report the failing address,
97 * the bus master and the transaction direction (i.e. read or write)
98 *
99 * Regardless of whether the error is a CE or a UE, we report the
100 * following pieces of information in the driver-unique message to the
101 * EDAC subsystem:
102 *
103 * - Device tree path
104 * - Bank(s)
105 * - Check bit error group
106 * - Beat(s)/lane(s)
107 */
108
109/* Preprocessor Definitions */
110
111#define EDAC_OPSTATE_INT_STR "interrupt"
112#define EDAC_OPSTATE_POLL_STR "polled"
113#define EDAC_OPSTATE_UNKNOWN_STR "unknown"
114
115#define PPC4XX_EDAC_MODULE_NAME "ppc4xx_edac"
116#define PPC4XX_EDAC_MODULE_REVISION "v1.0.0"
117
118#define PPC4XX_EDAC_MESSAGE_SIZE 256
119
120/*
121 * Kernel logging without an EDAC instance
122 */
123#define ppc4xx_edac_printk(level, fmt, arg...) \
124    edac_printk(level, "PPC4xx MC", fmt, ##arg)
125
126/*
127 * Kernel logging with an EDAC instance
128 */
129#define ppc4xx_edac_mc_printk(level, mci, fmt, arg...) \
130    edac_mc_chipset_printk(mci, level, "PPC4xx", fmt, ##arg)
131
132/*
133 * Macros to convert bank configuration size enumerations into MiB and
134 * page values.
135 */
136#define SDRAM_MBCF_SZ_MiB_MIN 4
137#define SDRAM_MBCF_SZ_TO_MiB(n) (SDRAM_MBCF_SZ_MiB_MIN \
138                     << (SDRAM_MBCF_SZ_DECODE(n)))
139#define SDRAM_MBCF_SZ_TO_PAGES(n) (SDRAM_MBCF_SZ_MiB_MIN \
140                     << (20 - PAGE_SHIFT + \
141                         SDRAM_MBCF_SZ_DECODE(n)))
142
143/*
144 * The ibm,sdram-4xx-ddr2 Device Control Registers (DCRs) are
145 * indirectly accessed and have a base and length defined by the
146 * device tree. The base can be anything; however, we expect the
147 * length to be precisely two registers, the first for the address
148 * window and the second for the data window.
149 */
150#define SDRAM_DCR_RESOURCE_LEN 2
151#define SDRAM_DCR_ADDR_OFFSET 0
152#define SDRAM_DCR_DATA_OFFSET 1
153
154/*
155 * Device tree interrupt indices
156 */
157#define INTMAP_ECCDED_INDEX 0 /* Double-bit Error Detect */
158#define INTMAP_ECCSEC_INDEX 1 /* Single-bit Error Correct */
159
160/* Type Definitions */
161
162/*
163 * PPC4xx SDRAM memory controller private instance data
164 */
165struct ppc4xx_edac_pdata {
166    dcr_host_t dcr_host; /* Indirect DCR address/data window mapping */
167    struct {
168        int sec; /* Single-bit correctable error IRQ assigned */
169        int ded; /* Double-bit detectable error IRQ assigned */
170    } irqs;
171};
172
173/*
174 * Various status data gathered and manipulated when checking and
175 * reporting ECC status.
176 */
177struct ppc4xx_ecc_status {
178    u32 ecces;
179    u32 besr;
180    u32 bearh;
181    u32 bearl;
182    u32 wmirq;
183};
184
185/* Function Prototypes */
186
187static int ppc4xx_edac_probe(struct platform_device *device);
188static int ppc4xx_edac_remove(struct platform_device *device);
189
190/* Global Variables */
191
192/*
193 * Device tree node type and compatible tuples this driver can match
194 * on.
195 */
196static struct of_device_id ppc4xx_edac_match[] = {
197    {
198        .compatible = "ibm,sdram-4xx-ddr2"
199    },
200    { }
201};
202
203static struct platform_driver ppc4xx_edac_driver = {
204    .probe = ppc4xx_edac_probe,
205    .remove = ppc4xx_edac_remove,
206    .driver = {
207        .owner = THIS_MODULE,
208        .name = PPC4XX_EDAC_MODULE_NAME,
209        .of_match_table = ppc4xx_edac_match,
210    },
211};
212
213/*
214 * TODO: The row and channel parameters likely need to be dynamically
215 * set based on the aforementioned variant controller realizations.
216 */
217static const unsigned ppc4xx_edac_nr_csrows = 2;
218static const unsigned ppc4xx_edac_nr_chans = 1;
219
220/*
221 * Strings associated with PLB master IDs capable of being posted in
222 * SDRAM_BESR or SDRAM_WMIRQ on uncorrectable ECC errors.
223 */
224static const char * const ppc4xx_plb_masters[9] = {
225    [SDRAM_PLB_M0ID_ICU] = "ICU",
226    [SDRAM_PLB_M0ID_PCIE0] = "PCI-E 0",
227    [SDRAM_PLB_M0ID_PCIE1] = "PCI-E 1",
228    [SDRAM_PLB_M0ID_DMA] = "DMA",
229    [SDRAM_PLB_M0ID_DCU] = "DCU",
230    [SDRAM_PLB_M0ID_OPB] = "OPB",
231    [SDRAM_PLB_M0ID_MAL] = "MAL",
232    [SDRAM_PLB_M0ID_SEC] = "SEC",
233    [SDRAM_PLB_M0ID_AHB] = "AHB"
234};
235
236/**
237 * mfsdram - read and return controller register data
238 * @dcr_host: A pointer to the DCR mapping.
239 * @idcr_n: The indirect DCR register to read.
240 *
241 * This routine reads and returns the data associated with the
242 * controller's specified indirect DCR register.
243 *
244 * Returns the read data.
245 */
246static inline u32
247mfsdram(const dcr_host_t *dcr_host, unsigned int idcr_n)
248{
249    return __mfdcri(dcr_host->base + SDRAM_DCR_ADDR_OFFSET,
250            dcr_host->base + SDRAM_DCR_DATA_OFFSET,
251            idcr_n);
252}
253
254/**
255 * mtsdram - write controller register data
256 * @dcr_host: A pointer to the DCR mapping.
257 * @idcr_n: The indirect DCR register to write.
258 * @value: The data to write.
259 *
260 * This routine writes the provided data to the controller's specified
261 * indirect DCR register.
262 */
263static inline void
264mtsdram(const dcr_host_t *dcr_host, unsigned int idcr_n, u32 value)
265{
266    return __mtdcri(dcr_host->base + SDRAM_DCR_ADDR_OFFSET,
267            dcr_host->base + SDRAM_DCR_DATA_OFFSET,
268            idcr_n,
269            value);
270}
271
272/**
273 * ppc4xx_edac_check_bank_error - check a bank for an ECC bank error
274 * @status: A pointer to the ECC status structure to check for an
275 * ECC bank error.
276 * @bank: The bank to check for an ECC error.
277 *
278 * This routine determines whether the specified bank has an ECC
279 * error.
280 *
281 * Returns true if the specified bank has an ECC error; otherwise,
282 * false.
283 */
284static bool
285ppc4xx_edac_check_bank_error(const struct ppc4xx_ecc_status *status,
286                 unsigned int bank)
287{
288    switch (bank) {
289    case 0:
290        return status->ecces & SDRAM_ECCES_BK0ER;
291    case 1:
292        return status->ecces & SDRAM_ECCES_BK1ER;
293    default:
294        return false;
295    }
296}
297
298/**
299 * ppc4xx_edac_generate_bank_message - generate interpretted bank status message
300 * @mci: A pointer to the EDAC memory controller instance associated
301 * with the bank message being generated.
302 * @status: A pointer to the ECC status structure to generate the
303 * message from.
304 * @buffer: A pointer to the buffer in which to generate the
305 * message.
306 * @size: The size, in bytes, of space available in buffer.
307 *
308 * This routine generates to the provided buffer the portion of the
309 * driver-unique report message associated with the ECCESS[BKNER]
310 * field of the specified ECC status.
311 *
312 * Returns the number of characters generated on success; otherwise, <
313 * 0 on error.
314 */
315static int
316ppc4xx_edac_generate_bank_message(const struct mem_ctl_info *mci,
317                  const struct ppc4xx_ecc_status *status,
318                  char *buffer,
319                  size_t size)
320{
321    int n, total = 0;
322    unsigned int row, rows;
323
324    n = snprintf(buffer, size, "%s: Banks: ", mci->dev_name);
325
326    if (n < 0 || n >= size)
327        goto fail;
328
329    buffer += n;
330    size -= n;
331    total += n;
332
333    for (rows = 0, row = 0; row < mci->nr_csrows; row++) {
334        if (ppc4xx_edac_check_bank_error(status, row)) {
335            n = snprintf(buffer, size, "%s%u",
336                    (rows++ ? ", " : ""), row);
337
338            if (n < 0 || n >= size)
339                goto fail;
340
341            buffer += n;
342            size -= n;
343            total += n;
344        }
345    }
346
347    n = snprintf(buffer, size, "%s; ", rows ? "" : "None");
348
349    if (n < 0 || n >= size)
350        goto fail;
351
352    buffer += n;
353    size -= n;
354    total += n;
355
356 fail:
357    return total;
358}
359
360/**
361 * ppc4xx_edac_generate_checkbit_message - generate interpretted checkbit message
362 * @mci: A pointer to the EDAC memory controller instance associated
363 * with the checkbit message being generated.
364 * @status: A pointer to the ECC status structure to generate the
365 * message from.
366 * @buffer: A pointer to the buffer in which to generate the
367 * message.
368 * @size: The size, in bytes, of space available in buffer.
369 *
370 * This routine generates to the provided buffer the portion of the
371 * driver-unique report message associated with the ECCESS[CKBER]
372 * field of the specified ECC status.
373 *
374 * Returns the number of characters generated on success; otherwise, <
375 * 0 on error.
376 */
377static int
378ppc4xx_edac_generate_checkbit_message(const struct mem_ctl_info *mci,
379                      const struct ppc4xx_ecc_status *status,
380                      char *buffer,
381                      size_t size)
382{
383    const struct ppc4xx_edac_pdata *pdata = mci->pvt_info;
384    const char *ckber = NULL;
385
386    switch (status->ecces & SDRAM_ECCES_CKBER_MASK) {
387    case SDRAM_ECCES_CKBER_NONE:
388        ckber = "None";
389        break;
390    case SDRAM_ECCES_CKBER_32_ECC_0_3:
391        ckber = "ECC0:3";
392        break;
393    case SDRAM_ECCES_CKBER_32_ECC_4_8:
394        switch (mfsdram(&pdata->dcr_host, SDRAM_MCOPT1) &
395            SDRAM_MCOPT1_WDTH_MASK) {
396        case SDRAM_MCOPT1_WDTH_16:
397            ckber = "ECC0:3";
398            break;
399        case SDRAM_MCOPT1_WDTH_32:
400            ckber = "ECC4:8";
401            break;
402        default:
403            ckber = "Unknown";
404            break;
405        }
406        break;
407    case SDRAM_ECCES_CKBER_32_ECC_0_8:
408        ckber = "ECC0:8";
409        break;
410    default:
411        ckber = "Unknown";
412        break;
413    }
414
415    return snprintf(buffer, size, "Checkbit Error: %s", ckber);
416}
417
418/**
419 * ppc4xx_edac_generate_lane_message - generate interpretted byte lane message
420 * @mci: A pointer to the EDAC memory controller instance associated
421 * with the byte lane message being generated.
422 * @status: A pointer to the ECC status structure to generate the
423 * message from.
424 * @buffer: A pointer to the buffer in which to generate the
425 * message.
426 * @size: The size, in bytes, of space available in buffer.
427 *
428 * This routine generates to the provided buffer the portion of the
429 * driver-unique report message associated with the ECCESS[BNCE]
430 * field of the specified ECC status.
431 *
432 * Returns the number of characters generated on success; otherwise, <
433 * 0 on error.
434 */
435static int
436ppc4xx_edac_generate_lane_message(const struct mem_ctl_info *mci,
437                  const struct ppc4xx_ecc_status *status,
438                  char *buffer,
439                  size_t size)
440{
441    int n, total = 0;
442    unsigned int lane, lanes;
443    const unsigned int first_lane = 0;
444    const unsigned int lane_count = 16;
445
446    n = snprintf(buffer, size, "; Byte Lane Errors: ");
447
448    if (n < 0 || n >= size)
449        goto fail;
450
451    buffer += n;
452    size -= n;
453    total += n;
454
455    for (lanes = 0, lane = first_lane; lane < lane_count; lane++) {
456        if ((status->ecces & SDRAM_ECCES_BNCE_ENCODE(lane)) != 0) {
457            n = snprintf(buffer, size,
458                     "%s%u",
459                     (lanes++ ? ", " : ""), lane);
460
461            if (n < 0 || n >= size)
462                goto fail;
463
464            buffer += n;
465            size -= n;
466            total += n;
467        }
468    }
469
470    n = snprintf(buffer, size, "%s; ", lanes ? "" : "None");
471
472    if (n < 0 || n >= size)
473        goto fail;
474
475    buffer += n;
476    size -= n;
477    total += n;
478
479 fail:
480    return total;
481}
482
483/**
484 * ppc4xx_edac_generate_ecc_message - generate interpretted ECC status message
485 * @mci: A pointer to the EDAC memory controller instance associated
486 * with the ECCES message being generated.
487 * @status: A pointer to the ECC status structure to generate the
488 * message from.
489 * @buffer: A pointer to the buffer in which to generate the
490 * message.
491 * @size: The size, in bytes, of space available in buffer.
492 *
493 * This routine generates to the provided buffer the portion of the
494 * driver-unique report message associated with the ECCESS register of
495 * the specified ECC status.
496 *
497 * Returns the number of characters generated on success; otherwise, <
498 * 0 on error.
499 */
500static int
501ppc4xx_edac_generate_ecc_message(const struct mem_ctl_info *mci,
502                 const struct ppc4xx_ecc_status *status,
503                 char *buffer,
504                 size_t size)
505{
506    int n, total = 0;
507
508    n = ppc4xx_edac_generate_bank_message(mci, status, buffer, size);
509
510    if (n < 0 || n >= size)
511        goto fail;
512
513    buffer += n;
514    size -= n;
515    total += n;
516
517    n = ppc4xx_edac_generate_checkbit_message(mci, status, buffer, size);
518
519    if (n < 0 || n >= size)
520        goto fail;
521
522    buffer += n;
523    size -= n;
524    total += n;
525
526    n = ppc4xx_edac_generate_lane_message(mci, status, buffer, size);
527
528    if (n < 0 || n >= size)
529        goto fail;
530
531    buffer += n;
532    size -= n;
533    total += n;
534
535 fail:
536    return total;
537}
538
539/**
540 * ppc4xx_edac_generate_plb_message - generate interpretted PLB status message
541 * @mci: A pointer to the EDAC memory controller instance associated
542 * with the PLB message being generated.
543 * @status: A pointer to the ECC status structure to generate the
544 * message from.
545 * @buffer: A pointer to the buffer in which to generate the
546 * message.
547 * @size: The size, in bytes, of space available in buffer.
548 *
549 * This routine generates to the provided buffer the portion of the
550 * driver-unique report message associated with the PLB-related BESR
551 * and/or WMIRQ registers of the specified ECC status.
552 *
553 * Returns the number of characters generated on success; otherwise, <
554 * 0 on error.
555 */
556static int
557ppc4xx_edac_generate_plb_message(const struct mem_ctl_info *mci,
558                 const struct ppc4xx_ecc_status *status,
559                 char *buffer,
560                 size_t size)
561{
562    unsigned int master;
563    bool read;
564
565    if ((status->besr & SDRAM_BESR_MASK) == 0)
566        return 0;
567
568    if ((status->besr & SDRAM_BESR_M0ET_MASK) == SDRAM_BESR_M0ET_NONE)
569        return 0;
570
571    read = ((status->besr & SDRAM_BESR_M0RW_MASK) == SDRAM_BESR_M0RW_READ);
572
573    master = SDRAM_BESR_M0ID_DECODE(status->besr);
574
575    return snprintf(buffer, size,
576            "%s error w/ PLB master %u \"%s\"; ",
577            (read ? "Read" : "Write"),
578            master,
579            (((master >= SDRAM_PLB_M0ID_FIRST) &&
580              (master <= SDRAM_PLB_M0ID_LAST)) ?
581             ppc4xx_plb_masters[master] : "UNKNOWN"));
582}
583
584/**
585 * ppc4xx_edac_generate_message - generate interpretted status message
586 * @mci: A pointer to the EDAC memory controller instance associated
587 * with the driver-unique message being generated.
588 * @status: A pointer to the ECC status structure to generate the
589 * message from.
590 * @buffer: A pointer to the buffer in which to generate the
591 * message.
592 * @size: The size, in bytes, of space available in buffer.
593 *
594 * This routine generates to the provided buffer the driver-unique
595 * EDAC report message from the specified ECC status.
596 */
597static void
598ppc4xx_edac_generate_message(const struct mem_ctl_info *mci,
599                 const struct ppc4xx_ecc_status *status,
600                 char *buffer,
601                 size_t size)
602{
603    int n;
604
605    if (buffer == NULL || size == 0)
606        return;
607
608    n = ppc4xx_edac_generate_ecc_message(mci, status, buffer, size);
609
610    if (n < 0 || n >= size)
611        return;
612
613    buffer += n;
614    size -= n;
615
616    ppc4xx_edac_generate_plb_message(mci, status, buffer, size);
617}
618
619#ifdef DEBUG
620/**
621 * ppc4xx_ecc_dump_status - dump controller ECC status registers
622 * @mci: A pointer to the EDAC memory controller instance
623 * associated with the status being dumped.
624 * @status: A pointer to the ECC status structure to generate the
625 * dump from.
626 *
627 * This routine dumps to the kernel log buffer the raw and
628 * interpretted specified ECC status.
629 */
630static void
631ppc4xx_ecc_dump_status(const struct mem_ctl_info *mci,
632               const struct ppc4xx_ecc_status *status)
633{
634    char message[PPC4XX_EDAC_MESSAGE_SIZE];
635
636    ppc4xx_edac_generate_message(mci, status, message, sizeof(message));
637
638    ppc4xx_edac_mc_printk(KERN_INFO, mci,
639                  "\n"
640                  "\tECCES: 0x%08x\n"
641                  "\tWMIRQ: 0x%08x\n"
642                  "\tBESR: 0x%08x\n"
643                  "\tBEAR: 0x%08x%08x\n"
644                  "\t%s\n",
645                  status->ecces,
646                  status->wmirq,
647                  status->besr,
648                  status->bearh,
649                  status->bearl,
650                  message);
651}
652#endif /* DEBUG */
653
654/**
655 * ppc4xx_ecc_get_status - get controller ECC status
656 * @mci: A pointer to the EDAC memory controller instance
657 * associated with the status being retrieved.
658 * @status: A pointer to the ECC status structure to populate the
659 * ECC status with.
660 *
661 * This routine reads and masks, as appropriate, all the relevant
662 * status registers that deal with ibm,sdram-4xx-ddr2 ECC errors.
663 * While we read all of them, for correctable errors, we only expect
664 * to deal with ECCES. For uncorrectable errors, we expect to deal
665 * with all of them.
666 */
667static void
668ppc4xx_ecc_get_status(const struct mem_ctl_info *mci,
669              struct ppc4xx_ecc_status *status)
670{
671    const struct ppc4xx_edac_pdata *pdata = mci->pvt_info;
672    const dcr_host_t *dcr_host = &pdata->dcr_host;
673
674    status->ecces = mfsdram(dcr_host, SDRAM_ECCES) & SDRAM_ECCES_MASK;
675    status->wmirq = mfsdram(dcr_host, SDRAM_WMIRQ) & SDRAM_WMIRQ_MASK;
676    status->besr = mfsdram(dcr_host, SDRAM_BESR) & SDRAM_BESR_MASK;
677    status->bearl = mfsdram(dcr_host, SDRAM_BEARL);
678    status->bearh = mfsdram(dcr_host, SDRAM_BEARH);
679}
680
681/**
682 * ppc4xx_ecc_clear_status - clear controller ECC status
683 * @mci: A pointer to the EDAC memory controller instance
684 * associated with the status being cleared.
685 * @status: A pointer to the ECC status structure containing the
686 * values to write to clear the ECC status.
687 *
688 * This routine clears--by writing the masked (as appropriate) status
689 * values back to--the status registers that deal with
690 * ibm,sdram-4xx-ddr2 ECC errors.
691 */
692static void
693ppc4xx_ecc_clear_status(const struct mem_ctl_info *mci,
694            const struct ppc4xx_ecc_status *status)
695{
696    const struct ppc4xx_edac_pdata *pdata = mci->pvt_info;
697    const dcr_host_t *dcr_host = &pdata->dcr_host;
698
699    mtsdram(dcr_host, SDRAM_ECCES, status->ecces & SDRAM_ECCES_MASK);
700    mtsdram(dcr_host, SDRAM_WMIRQ, status->wmirq & SDRAM_WMIRQ_MASK);
701    mtsdram(dcr_host, SDRAM_BESR, status->besr & SDRAM_BESR_MASK);
702    mtsdram(dcr_host, SDRAM_BEARL, 0);
703    mtsdram(dcr_host, SDRAM_BEARH, 0);
704}
705
706/**
707 * ppc4xx_edac_handle_ce - handle controller correctable ECC error (CE)
708 * @mci: A pointer to the EDAC memory controller instance
709 * associated with the correctable error being handled and reported.
710 * @status: A pointer to the ECC status structure associated with
711 * the correctable error being handled and reported.
712 *
713 * This routine handles an ibm,sdram-4xx-ddr2 controller ECC
714 * correctable error. Per the aforementioned discussion, there's not
715 * enough status available to use the full EDAC correctable error
716 * interface, so we just pass driver-unique message to the "no info"
717 * interface.
718 */
719static void
720ppc4xx_edac_handle_ce(struct mem_ctl_info *mci,
721              const struct ppc4xx_ecc_status *status)
722{
723    int row;
724    char message[PPC4XX_EDAC_MESSAGE_SIZE];
725
726    ppc4xx_edac_generate_message(mci, status, message, sizeof(message));
727
728    for (row = 0; row < mci->nr_csrows; row++)
729        if (ppc4xx_edac_check_bank_error(status, row))
730            edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1,
731                         0, 0, 0,
732                         row, 0, -1,
733                         message, "");
734}
735
736/**
737 * ppc4xx_edac_handle_ue - handle controller uncorrectable ECC error (UE)
738 * @mci: A pointer to the EDAC memory controller instance
739 * associated with the uncorrectable error being handled and
740 * reported.
741 * @status: A pointer to the ECC status structure associated with
742 * the uncorrectable error being handled and reported.
743 *
744 * This routine handles an ibm,sdram-4xx-ddr2 controller ECC
745 * uncorrectable error.
746 */
747static void
748ppc4xx_edac_handle_ue(struct mem_ctl_info *mci,
749              const struct ppc4xx_ecc_status *status)
750{
751    const u64 bear = ((u64)status->bearh << 32 | status->bearl);
752    const unsigned long page = bear >> PAGE_SHIFT;
753    const unsigned long offset = bear & ~PAGE_MASK;
754    int row;
755    char message[PPC4XX_EDAC_MESSAGE_SIZE];
756
757    ppc4xx_edac_generate_message(mci, status, message, sizeof(message));
758
759    for (row = 0; row < mci->nr_csrows; row++)
760        if (ppc4xx_edac_check_bank_error(status, row))
761            edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1,
762                         page, offset, 0,
763                         row, 0, -1,
764                         message, "");
765}
766
767/**
768 * ppc4xx_edac_check - check controller for ECC errors
769 * @mci: A pointer to the EDAC memory controller instance
770 * associated with the ibm,sdram-4xx-ddr2 controller being
771 * checked.
772 *
773 * This routine is used to check and post ECC errors and is called by
774 * both the EDAC polling thread and this driver's CE and UE interrupt
775 * handler.
776 */
777static void
778ppc4xx_edac_check(struct mem_ctl_info *mci)
779{
780#ifdef DEBUG
781    static unsigned int count;
782#endif
783    struct ppc4xx_ecc_status status;
784
785    ppc4xx_ecc_get_status(mci, &status);
786
787#ifdef DEBUG
788    if (count++ % 30 == 0)
789        ppc4xx_ecc_dump_status(mci, &status);
790#endif
791
792    if (status.ecces & SDRAM_ECCES_UE)
793        ppc4xx_edac_handle_ue(mci, &status);
794
795    if (status.ecces & SDRAM_ECCES_CE)
796        ppc4xx_edac_handle_ce(mci, &status);
797
798    ppc4xx_ecc_clear_status(mci, &status);
799}
800
801/**
802 * ppc4xx_edac_isr - SEC (CE) and DED (UE) interrupt service routine
803 * @irq: The virtual interrupt number being serviced.
804 * @dev_id: A pointer to the EDAC memory controller instance
805 * associated with the interrupt being handled.
806 *
807 * This routine implements the interrupt handler for both correctable
808 * (CE) and uncorrectable (UE) ECC errors for the ibm,sdram-4xx-ddr2
809 * controller. It simply calls through to the same routine used during
810 * polling to check, report and clear the ECC status.
811 *
812 * Unconditionally returns IRQ_HANDLED.
813 */
814static irqreturn_t
815ppc4xx_edac_isr(int irq, void *dev_id)
816{
817    struct mem_ctl_info *mci = dev_id;
818
819    ppc4xx_edac_check(mci);
820
821    return IRQ_HANDLED;
822}
823
824/**
825 * ppc4xx_edac_get_dtype - return the controller memory width
826 * @mcopt1: The 32-bit Memory Controller Option 1 register value
827 * currently set for the controller, from which the width
828 * is derived.
829 *
830 * This routine returns the EDAC device type width appropriate for the
831 * current controller configuration.
832 *
833 * TODO: This needs to be conditioned dynamically through feature
834 * flags or some such when other controller variants are supported as
835 * the 405EX[r] is 16-/32-bit and the others are 32-/64-bit with the
836 * 16- and 64-bit field definition/value/enumeration (b1) overloaded
837 * among them.
838 *
839 * Returns a device type width enumeration.
840 */
841static enum dev_type __devinit
842ppc4xx_edac_get_dtype(u32 mcopt1)
843{
844    switch (mcopt1 & SDRAM_MCOPT1_WDTH_MASK) {
845    case SDRAM_MCOPT1_WDTH_16:
846        return DEV_X2;
847    case SDRAM_MCOPT1_WDTH_32:
848        return DEV_X4;
849    default:
850        return DEV_UNKNOWN;
851    }
852}
853
854/**
855 * ppc4xx_edac_get_mtype - return controller memory type
856 * @mcopt1: The 32-bit Memory Controller Option 1 register value
857 * currently set for the controller, from which the memory type
858 * is derived.
859 *
860 * This routine returns the EDAC memory type appropriate for the
861 * current controller configuration.
862 *
863 * Returns a memory type enumeration.
864 */
865static enum mem_type __devinit
866ppc4xx_edac_get_mtype(u32 mcopt1)
867{
868    bool rden = ((mcopt1 & SDRAM_MCOPT1_RDEN_MASK) == SDRAM_MCOPT1_RDEN);
869
870    switch (mcopt1 & SDRAM_MCOPT1_DDR_TYPE_MASK) {
871    case SDRAM_MCOPT1_DDR2_TYPE:
872        return rden ? MEM_RDDR2 : MEM_DDR2;
873    case SDRAM_MCOPT1_DDR1_TYPE:
874        return rden ? MEM_RDDR : MEM_DDR;
875    default:
876        return MEM_UNKNOWN;
877    }
878}
879
880/**
881 * ppc4xx_edac_init_csrows - initialize driver instance rows
882 * @mci: A pointer to the EDAC memory controller instance
883 * associated with the ibm,sdram-4xx-ddr2 controller for which
884 * the csrows (i.e. banks/ranks) are being initialized.
885 * @mcopt1: The 32-bit Memory Controller Option 1 register value
886 * currently set for the controller, from which bank width
887 * and memory typ information is derived.
888 *
889 * This routine initializes the virtual "chip select rows" associated
890 * with the EDAC memory controller instance. An ibm,sdram-4xx-ddr2
891 * controller bank/rank is mapped to a row.
892 *
893 * Returns 0 if OK; otherwise, -EINVAL if the memory bank size
894 * configuration cannot be determined.
895 */
896static int __devinit
897ppc4xx_edac_init_csrows(struct mem_ctl_info *mci, u32 mcopt1)
898{
899    const struct ppc4xx_edac_pdata *pdata = mci->pvt_info;
900    int status = 0;
901    enum mem_type mtype;
902    enum dev_type dtype;
903    enum edac_type edac_mode;
904    int row, j;
905    u32 mbxcf, size, nr_pages;
906
907    /* Establish the memory type and width */
908
909    mtype = ppc4xx_edac_get_mtype(mcopt1);
910    dtype = ppc4xx_edac_get_dtype(mcopt1);
911
912    /* Establish EDAC mode */
913
914    if (mci->edac_cap & EDAC_FLAG_SECDED)
915        edac_mode = EDAC_SECDED;
916    else if (mci->edac_cap & EDAC_FLAG_EC)
917        edac_mode = EDAC_EC;
918    else
919        edac_mode = EDAC_NONE;
920
921    /*
922     * Initialize each chip select row structure which correspond
923     * 1:1 with a controller bank/rank.
924     */
925
926    for (row = 0; row < mci->nr_csrows; row++) {
927        struct csrow_info *csi = &mci->csrows[row];
928
929        /*
930         * Get the configuration settings for this
931         * row/bank/rank and skip disabled banks.
932         */
933
934        mbxcf = mfsdram(&pdata->dcr_host, SDRAM_MBXCF(row));
935
936        if ((mbxcf & SDRAM_MBCF_BE_MASK) != SDRAM_MBCF_BE_ENABLE)
937            continue;
938
939        /* Map the bank configuration size setting to pages. */
940
941        size = mbxcf & SDRAM_MBCF_SZ_MASK;
942
943        switch (size) {
944        case SDRAM_MBCF_SZ_4MB:
945        case SDRAM_MBCF_SZ_8MB:
946        case SDRAM_MBCF_SZ_16MB:
947        case SDRAM_MBCF_SZ_32MB:
948        case SDRAM_MBCF_SZ_64MB:
949        case SDRAM_MBCF_SZ_128MB:
950        case SDRAM_MBCF_SZ_256MB:
951        case SDRAM_MBCF_SZ_512MB:
952        case SDRAM_MBCF_SZ_1GB:
953        case SDRAM_MBCF_SZ_2GB:
954        case SDRAM_MBCF_SZ_4GB:
955        case SDRAM_MBCF_SZ_8GB:
956            nr_pages = SDRAM_MBCF_SZ_TO_PAGES(size);
957            break;
958        default:
959            ppc4xx_edac_mc_printk(KERN_ERR, mci,
960                          "Unrecognized memory bank %d "
961                          "size 0x%08x\n",
962                          row, SDRAM_MBCF_SZ_DECODE(size));
963            status = -EINVAL;
964            goto done;
965        }
966
967        /*
968         * It's unclear exactly what grain should be set to
969         * here. The SDRAM_ECCES register allows resolution of
970         * an error down to a nibble which would potentially
971         * argue for a grain of '1' byte, even though we only
972         * know the associated address for uncorrectable
973         * errors. This value is not used at present for
974         * anything other than error reporting so getting it
975         * wrong should be of little consequence. Other
976         * possible values would be the PLB width (16), the
977         * page size (PAGE_SIZE) or the memory width (2 or 4).
978         */
979        for (j = 0; j < csi->nr_channels; j++) {
980            struct dimm_info *dimm = csi->channels[j].dimm;
981
982            dimm->nr_pages = nr_pages / csi->nr_channels;
983            dimm->grain = 1;
984
985            dimm->mtype = mtype;
986            dimm->dtype = dtype;
987
988            dimm->edac_mode = edac_mode;
989        }
990    }
991
992 done:
993    return status;
994}
995
996/**
997 * ppc4xx_edac_mc_init - initialize driver instance
998 * @mci: A pointer to the EDAC memory controller instance being
999 * initialized.
1000 * @op: A pointer to the OpenFirmware device tree node associated
1001 * with the controller this EDAC instance is bound to.
1002 * @dcr_host: A pointer to the DCR data containing the DCR mapping
1003 * for this controller instance.
1004 * @mcopt1: The 32-bit Memory Controller Option 1 register value
1005 * currently set for the controller, from which ECC capabilities
1006 * and scrub mode are derived.
1007 *
1008 * This routine performs initialization of the EDAC memory controller
1009 * instance and related driver-private data associated with the
1010 * ibm,sdram-4xx-ddr2 memory controller the instance is bound to.
1011 *
1012 * Returns 0 if OK; otherwise, < 0 on error.
1013 */
1014static int __devinit
1015ppc4xx_edac_mc_init(struct mem_ctl_info *mci,
1016            struct platform_device *op,
1017            const dcr_host_t *dcr_host,
1018            u32 mcopt1)
1019{
1020    int status = 0;
1021    const u32 memcheck = (mcopt1 & SDRAM_MCOPT1_MCHK_MASK);
1022    struct ppc4xx_edac_pdata *pdata = NULL;
1023    const struct device_node *np = op->dev.of_node;
1024
1025    if (of_match_device(ppc4xx_edac_match, &op->dev) == NULL)
1026        return -EINVAL;
1027
1028    /* Initial driver pointers and private data */
1029
1030    mci->pdev = &op->dev;
1031
1032    dev_set_drvdata(mci->pdev, mci);
1033
1034    pdata = mci->pvt_info;
1035
1036    pdata->dcr_host = *dcr_host;
1037    pdata->irqs.sec = NO_IRQ;
1038    pdata->irqs.ded = NO_IRQ;
1039
1040    /* Initialize controller capabilities and configuration */
1041
1042    mci->mtype_cap = (MEM_FLAG_DDR | MEM_FLAG_RDDR |
1043                   MEM_FLAG_DDR2 | MEM_FLAG_RDDR2);
1044
1045    mci->edac_ctl_cap = (EDAC_FLAG_NONE |
1046                   EDAC_FLAG_EC |
1047                   EDAC_FLAG_SECDED);
1048
1049    mci->scrub_cap = SCRUB_NONE;
1050    mci->scrub_mode = SCRUB_NONE;
1051
1052    /*
1053     * Update the actual capabilites based on the MCOPT1[MCHK]
1054     * settings. Scrubbing is only useful if reporting is enabled.
1055     */
1056
1057    switch (memcheck) {
1058    case SDRAM_MCOPT1_MCHK_CHK:
1059        mci->edac_cap = EDAC_FLAG_EC;
1060        break;
1061    case SDRAM_MCOPT1_MCHK_CHK_REP:
1062        mci->edac_cap = (EDAC_FLAG_EC | EDAC_FLAG_SECDED);
1063        mci->scrub_mode = SCRUB_SW_SRC;
1064        break;
1065    default:
1066        mci->edac_cap = EDAC_FLAG_NONE;
1067        break;
1068    }
1069
1070    /* Initialize strings */
1071
1072    mci->mod_name = PPC4XX_EDAC_MODULE_NAME;
1073    mci->mod_ver = PPC4XX_EDAC_MODULE_REVISION;
1074    mci->ctl_name = ppc4xx_edac_match->compatible,
1075    mci->dev_name = np->full_name;
1076
1077    /* Initialize callbacks */
1078
1079    mci->edac_check = ppc4xx_edac_check;
1080    mci->ctl_page_to_phys = NULL;
1081
1082    /* Initialize chip select rows */
1083
1084    status = ppc4xx_edac_init_csrows(mci, mcopt1);
1085
1086    if (status)
1087        ppc4xx_edac_mc_printk(KERN_ERR, mci,
1088                      "Failed to initialize rows!\n");
1089
1090    return status;
1091}
1092
1093/**
1094 * ppc4xx_edac_register_irq - setup and register controller interrupts
1095 * @op: A pointer to the OpenFirmware device tree node associated
1096 * with the controller this EDAC instance is bound to.
1097 * @mci: A pointer to the EDAC memory controller instance
1098 * associated with the ibm,sdram-4xx-ddr2 controller for which
1099 * interrupts are being registered.
1100 *
1101 * This routine parses the correctable (CE) and uncorrectable error (UE)
1102 * interrupts from the device tree node and maps and assigns them to
1103 * the associated EDAC memory controller instance.
1104 *
1105 * Returns 0 if OK; otherwise, -ENODEV if the interrupts could not be
1106 * mapped and assigned.
1107 */
1108static int __devinit
1109ppc4xx_edac_register_irq(struct platform_device *op, struct mem_ctl_info *mci)
1110{
1111    int status = 0;
1112    int ded_irq, sec_irq;
1113    struct ppc4xx_edac_pdata *pdata = mci->pvt_info;
1114    struct device_node *np = op->dev.of_node;
1115
1116    ded_irq = irq_of_parse_and_map(np, INTMAP_ECCDED_INDEX);
1117    sec_irq = irq_of_parse_and_map(np, INTMAP_ECCSEC_INDEX);
1118
1119    if (ded_irq == NO_IRQ || sec_irq == NO_IRQ) {
1120        ppc4xx_edac_mc_printk(KERN_ERR, mci,
1121                      "Unable to map interrupts.\n");
1122        status = -ENODEV;
1123        goto fail;
1124    }
1125
1126    status = request_irq(ded_irq,
1127                 ppc4xx_edac_isr,
1128                 IRQF_DISABLED,
1129                 "[EDAC] MC ECCDED",
1130                 mci);
1131
1132    if (status < 0) {
1133        ppc4xx_edac_mc_printk(KERN_ERR, mci,
1134                      "Unable to request irq %d for ECC DED",
1135                      ded_irq);
1136        status = -ENODEV;
1137        goto fail1;
1138    }
1139
1140    status = request_irq(sec_irq,
1141                 ppc4xx_edac_isr,
1142                 IRQF_DISABLED,
1143                 "[EDAC] MC ECCSEC",
1144                 mci);
1145
1146    if (status < 0) {
1147        ppc4xx_edac_mc_printk(KERN_ERR, mci,
1148                      "Unable to request irq %d for ECC SEC",
1149                      sec_irq);
1150        status = -ENODEV;
1151        goto fail2;
1152    }
1153
1154    ppc4xx_edac_mc_printk(KERN_INFO, mci, "ECCDED irq is %d\n", ded_irq);
1155    ppc4xx_edac_mc_printk(KERN_INFO, mci, "ECCSEC irq is %d\n", sec_irq);
1156
1157    pdata->irqs.ded = ded_irq;
1158    pdata->irqs.sec = sec_irq;
1159
1160    return 0;
1161
1162 fail2:
1163    free_irq(sec_irq, mci);
1164
1165 fail1:
1166    free_irq(ded_irq, mci);
1167
1168 fail:
1169    return status;
1170}
1171
1172/**
1173 * ppc4xx_edac_map_dcrs - locate and map controller registers
1174 * @np: A pointer to the device tree node containing the DCR
1175 * resources to map.
1176 * @dcr_host: A pointer to the DCR data to populate with the
1177 * DCR mapping.
1178 *
1179 * This routine attempts to locate in the device tree and map the DCR
1180 * register resources associated with the controller's indirect DCR
1181 * address and data windows.
1182 *
1183 * Returns 0 if the DCRs were successfully mapped; otherwise, < 0 on
1184 * error.
1185 */
1186static int __devinit
1187ppc4xx_edac_map_dcrs(const struct device_node *np, dcr_host_t *dcr_host)
1188{
1189    unsigned int dcr_base, dcr_len;
1190
1191    if (np == NULL || dcr_host == NULL)
1192        return -EINVAL;
1193
1194    /* Get the DCR resource extent and sanity check the values. */
1195
1196    dcr_base = dcr_resource_start(np, 0);
1197    dcr_len = dcr_resource_len(np, 0);
1198
1199    if (dcr_base == 0 || dcr_len == 0) {
1200        ppc4xx_edac_printk(KERN_ERR,
1201                   "Failed to obtain DCR property.\n");
1202        return -ENODEV;
1203    }
1204
1205    if (dcr_len != SDRAM_DCR_RESOURCE_LEN) {
1206        ppc4xx_edac_printk(KERN_ERR,
1207                   "Unexpected DCR length %d, expected %d.\n",
1208                   dcr_len, SDRAM_DCR_RESOURCE_LEN);
1209        return -ENODEV;
1210    }
1211
1212    /* Attempt to map the DCR extent. */
1213
1214    *dcr_host = dcr_map(np, dcr_base, dcr_len);
1215
1216    if (!DCR_MAP_OK(*dcr_host)) {
1217        ppc4xx_edac_printk(KERN_INFO, "Failed to map DCRs.\n");
1218            return -ENODEV;
1219    }
1220
1221    return 0;
1222}
1223
1224/**
1225 * ppc4xx_edac_probe - check controller and bind driver
1226 * @op: A pointer to the OpenFirmware device tree node associated
1227 * with the controller being probed for driver binding.
1228 *
1229 * This routine probes a specific ibm,sdram-4xx-ddr2 controller
1230 * instance for binding with the driver.
1231 *
1232 * Returns 0 if the controller instance was successfully bound to the
1233 * driver; otherwise, < 0 on error.
1234 */
1235static int __devinit ppc4xx_edac_probe(struct platform_device *op)
1236{
1237    int status = 0;
1238    u32 mcopt1, memcheck;
1239    dcr_host_t dcr_host;
1240    const struct device_node *np = op->dev.of_node;
1241    struct mem_ctl_info *mci = NULL;
1242    struct edac_mc_layer layers[2];
1243    static int ppc4xx_edac_instance;
1244
1245    /*
1246     * At this point, we only support the controller realized on
1247     * the AMCC PPC 405EX[r]. Reject anything else.
1248     */
1249
1250    if (!of_device_is_compatible(np, "ibm,sdram-405ex") &&
1251        !of_device_is_compatible(np, "ibm,sdram-405exr")) {
1252        ppc4xx_edac_printk(KERN_NOTICE,
1253                   "Only the PPC405EX[r] is supported.\n");
1254        return -ENODEV;
1255    }
1256
1257    /*
1258     * Next, get the DCR property and attempt to map it so that we
1259     * can probe the controller.
1260     */
1261
1262    status = ppc4xx_edac_map_dcrs(np, &dcr_host);
1263
1264    if (status)
1265        return status;
1266
1267    /*
1268     * First determine whether ECC is enabled at all. If not,
1269     * there is no useful checking or monitoring that can be done
1270     * for this controller.
1271     */
1272
1273    mcopt1 = mfsdram(&dcr_host, SDRAM_MCOPT1);
1274    memcheck = (mcopt1 & SDRAM_MCOPT1_MCHK_MASK);
1275
1276    if (memcheck == SDRAM_MCOPT1_MCHK_NON) {
1277        ppc4xx_edac_printk(KERN_INFO, "%s: No ECC memory detected or "
1278                   "ECC is disabled.\n", np->full_name);
1279        status = -ENODEV;
1280        goto done;
1281    }
1282
1283    /*
1284     * At this point, we know ECC is enabled, allocate an EDAC
1285     * controller instance and perform the appropriate
1286     * initialization.
1287     */
1288    layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
1289    layers[0].size = ppc4xx_edac_nr_csrows;
1290    layers[0].is_virt_csrow = true;
1291    layers[1].type = EDAC_MC_LAYER_CHANNEL;
1292    layers[1].size = ppc4xx_edac_nr_chans;
1293    layers[1].is_virt_csrow = false;
1294    mci = edac_mc_alloc(ppc4xx_edac_instance, ARRAY_SIZE(layers), layers,
1295                sizeof(struct ppc4xx_edac_pdata));
1296    if (mci == NULL) {
1297        ppc4xx_edac_printk(KERN_ERR, "%s: "
1298                   "Failed to allocate EDAC MC instance!\n",
1299                   np->full_name);
1300        status = -ENOMEM;
1301        goto done;
1302    }
1303
1304    status = ppc4xx_edac_mc_init(mci, op, &dcr_host, mcopt1);
1305
1306    if (status) {
1307        ppc4xx_edac_mc_printk(KERN_ERR, mci,
1308                      "Failed to initialize instance!\n");
1309        goto fail;
1310    }
1311
1312    /*
1313     * We have a valid, initialized EDAC instance bound to the
1314     * controller. Attempt to register it with the EDAC subsystem
1315     * and, if necessary, register interrupts.
1316     */
1317
1318    if (edac_mc_add_mc(mci)) {
1319        ppc4xx_edac_mc_printk(KERN_ERR, mci,
1320                      "Failed to add instance!\n");
1321        status = -ENODEV;
1322        goto fail;
1323    }
1324
1325    if (edac_op_state == EDAC_OPSTATE_INT) {
1326        status = ppc4xx_edac_register_irq(op, mci);
1327
1328        if (status)
1329            goto fail1;
1330    }
1331
1332    ppc4xx_edac_instance++;
1333
1334    return 0;
1335
1336 fail1:
1337    edac_mc_del_mc(mci->pdev);
1338
1339 fail:
1340    edac_mc_free(mci);
1341
1342 done:
1343    return status;
1344}
1345
1346/**
1347 * ppc4xx_edac_remove - unbind driver from controller
1348 * @op: A pointer to the OpenFirmware device tree node associated
1349 * with the controller this EDAC instance is to be unbound/removed
1350 * from.
1351 *
1352 * This routine unbinds the EDAC memory controller instance associated
1353 * with the specified ibm,sdram-4xx-ddr2 controller described by the
1354 * OpenFirmware device tree node passed as a parameter.
1355 *
1356 * Unconditionally returns 0.
1357 */
1358static int
1359ppc4xx_edac_remove(struct platform_device *op)
1360{
1361    struct mem_ctl_info *mci = dev_get_drvdata(&op->dev);
1362    struct ppc4xx_edac_pdata *pdata = mci->pvt_info;
1363
1364    if (edac_op_state == EDAC_OPSTATE_INT) {
1365        free_irq(pdata->irqs.sec, mci);
1366        free_irq(pdata->irqs.ded, mci);
1367    }
1368
1369    dcr_unmap(pdata->dcr_host, SDRAM_DCR_RESOURCE_LEN);
1370
1371    edac_mc_del_mc(mci->pdev);
1372    edac_mc_free(mci);
1373
1374    return 0;
1375}
1376
1377/**
1378 * ppc4xx_edac_opstate_init - initialize EDAC reporting method
1379 *
1380 * This routine ensures that the EDAC memory controller reporting
1381 * method is mapped to a sane value as the EDAC core defines the value
1382 * to EDAC_OPSTATE_INVAL by default. We don't call the global
1383 * opstate_init as that defaults to polling and we want interrupt as
1384 * the default.
1385 */
1386static inline void __init
1387ppc4xx_edac_opstate_init(void)
1388{
1389    switch (edac_op_state) {
1390    case EDAC_OPSTATE_POLL:
1391    case EDAC_OPSTATE_INT:
1392        break;
1393    default:
1394        edac_op_state = EDAC_OPSTATE_INT;
1395        break;
1396    }
1397
1398    ppc4xx_edac_printk(KERN_INFO, "Reporting type: %s\n",
1399               ((edac_op_state == EDAC_OPSTATE_POLL) ?
1400                EDAC_OPSTATE_POLL_STR :
1401                ((edac_op_state == EDAC_OPSTATE_INT) ?
1402                 EDAC_OPSTATE_INT_STR :
1403                 EDAC_OPSTATE_UNKNOWN_STR)));
1404}
1405
1406/**
1407 * ppc4xx_edac_init - driver/module insertion entry point
1408 *
1409 * This routine is the driver/module insertion entry point. It
1410 * initializes the EDAC memory controller reporting state and
1411 * registers the driver as an OpenFirmware device tree platform
1412 * driver.
1413 */
1414static int __init
1415ppc4xx_edac_init(void)
1416{
1417    ppc4xx_edac_printk(KERN_INFO, PPC4XX_EDAC_MODULE_REVISION "\n");
1418
1419    ppc4xx_edac_opstate_init();
1420
1421    return platform_driver_register(&ppc4xx_edac_driver);
1422}
1423
1424/**
1425 * ppc4xx_edac_exit - driver/module removal entry point
1426 *
1427 * This routine is the driver/module removal entry point. It
1428 * unregisters the driver as an OpenFirmware device tree platform
1429 * driver.
1430 */
1431static void __exit
1432ppc4xx_edac_exit(void)
1433{
1434    platform_driver_unregister(&ppc4xx_edac_driver);
1435}
1436
1437module_init(ppc4xx_edac_init);
1438module_exit(ppc4xx_edac_exit);
1439
1440MODULE_LICENSE("GPL v2");
1441MODULE_AUTHOR("Grant Erickson <gerickson@nuovations.com>");
1442MODULE_DESCRIPTION("EDAC MC Driver for the PPC4xx IBM DDR2 Memory Controller");
1443module_param(edac_op_state, int, 0444);
1444MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting State: "
1445         "0=" EDAC_OPSTATE_POLL_STR ", 2=" EDAC_OPSTATE_INT_STR);
1446

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