Root/drivers/gpio/gpio-lpc32xx.c

1/*
2 * GPIO driver for LPC32xx SoC
3 *
4 * Author: Kevin Wells <kevin.wells@nxp.com>
5 *
6 * Copyright (C) 2010 NXP Semiconductors
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 */
18
19#include <linux/kernel.h>
20#include <linux/init.h>
21#include <linux/io.h>
22#include <linux/errno.h>
23#include <linux/gpio.h>
24#include <linux/of_gpio.h>
25#include <linux/platform_device.h>
26#include <linux/module.h>
27
28#include <mach/hardware.h>
29#include <mach/platform.h>
30#include <mach/gpio-lpc32xx.h>
31#include <mach/irqs.h>
32
33#define LPC32XX_GPIO_P3_INP_STATE _GPREG(0x000)
34#define LPC32XX_GPIO_P3_OUTP_SET _GPREG(0x004)
35#define LPC32XX_GPIO_P3_OUTP_CLR _GPREG(0x008)
36#define LPC32XX_GPIO_P3_OUTP_STATE _GPREG(0x00C)
37#define LPC32XX_GPIO_P2_DIR_SET _GPREG(0x010)
38#define LPC32XX_GPIO_P2_DIR_CLR _GPREG(0x014)
39#define LPC32XX_GPIO_P2_DIR_STATE _GPREG(0x018)
40#define LPC32XX_GPIO_P2_INP_STATE _GPREG(0x01C)
41#define LPC32XX_GPIO_P2_OUTP_SET _GPREG(0x020)
42#define LPC32XX_GPIO_P2_OUTP_CLR _GPREG(0x024)
43#define LPC32XX_GPIO_P2_MUX_SET _GPREG(0x028)
44#define LPC32XX_GPIO_P2_MUX_CLR _GPREG(0x02C)
45#define LPC32XX_GPIO_P2_MUX_STATE _GPREG(0x030)
46#define LPC32XX_GPIO_P0_INP_STATE _GPREG(0x040)
47#define LPC32XX_GPIO_P0_OUTP_SET _GPREG(0x044)
48#define LPC32XX_GPIO_P0_OUTP_CLR _GPREG(0x048)
49#define LPC32XX_GPIO_P0_OUTP_STATE _GPREG(0x04C)
50#define LPC32XX_GPIO_P0_DIR_SET _GPREG(0x050)
51#define LPC32XX_GPIO_P0_DIR_CLR _GPREG(0x054)
52#define LPC32XX_GPIO_P0_DIR_STATE _GPREG(0x058)
53#define LPC32XX_GPIO_P1_INP_STATE _GPREG(0x060)
54#define LPC32XX_GPIO_P1_OUTP_SET _GPREG(0x064)
55#define LPC32XX_GPIO_P1_OUTP_CLR _GPREG(0x068)
56#define LPC32XX_GPIO_P1_OUTP_STATE _GPREG(0x06C)
57#define LPC32XX_GPIO_P1_DIR_SET _GPREG(0x070)
58#define LPC32XX_GPIO_P1_DIR_CLR _GPREG(0x074)
59#define LPC32XX_GPIO_P1_DIR_STATE _GPREG(0x078)
60
61#define GPIO012_PIN_TO_BIT(x) (1 << (x))
62#define GPIO3_PIN_TO_BIT(x) (1 << ((x) + 25))
63#define GPO3_PIN_TO_BIT(x) (1 << (x))
64#define GPIO012_PIN_IN_SEL(x, y) (((x) >> (y)) & 1)
65#define GPIO3_PIN_IN_SHIFT(x) ((x) == 5 ? 24 : 10 + (x))
66#define GPIO3_PIN_IN_SEL(x, y) (((x) >> GPIO3_PIN_IN_SHIFT(y)) & 1)
67#define GPIO3_PIN5_IN_SEL(x) (((x) >> 24) & 1)
68#define GPI3_PIN_IN_SEL(x, y) (((x) >> (y)) & 1)
69#define GPO3_PIN_IN_SEL(x, y) (((x) >> (y)) & 1)
70
71struct gpio_regs {
72    void __iomem *inp_state;
73    void __iomem *outp_state;
74    void __iomem *outp_set;
75    void __iomem *outp_clr;
76    void __iomem *dir_set;
77    void __iomem *dir_clr;
78};
79
80/*
81 * GPIO names
82 */
83static const char *gpio_p0_names[LPC32XX_GPIO_P0_MAX] = {
84    "p0.0", "p0.1", "p0.2", "p0.3",
85    "p0.4", "p0.5", "p0.6", "p0.7"
86};
87
88static const char *gpio_p1_names[LPC32XX_GPIO_P1_MAX] = {
89    "p1.0", "p1.1", "p1.2", "p1.3",
90    "p1.4", "p1.5", "p1.6", "p1.7",
91    "p1.8", "p1.9", "p1.10", "p1.11",
92    "p1.12", "p1.13", "p1.14", "p1.15",
93    "p1.16", "p1.17", "p1.18", "p1.19",
94    "p1.20", "p1.21", "p1.22", "p1.23",
95};
96
97static const char *gpio_p2_names[LPC32XX_GPIO_P2_MAX] = {
98    "p2.0", "p2.1", "p2.2", "p2.3",
99    "p2.4", "p2.5", "p2.6", "p2.7",
100    "p2.8", "p2.9", "p2.10", "p2.11",
101    "p2.12"
102};
103
104static const char *gpio_p3_names[LPC32XX_GPIO_P3_MAX] = {
105    "gpio00", "gpio01", "gpio02", "gpio03",
106    "gpio04", "gpio05"
107};
108
109static const char *gpi_p3_names[LPC32XX_GPI_P3_MAX] = {
110    "gpi00", "gpi01", "gpi02", "gpi03",
111    "gpi04", "gpi05", "gpi06", "gpi07",
112    "gpi08", "gpi09", NULL, NULL,
113     NULL, NULL, NULL, "gpi15",
114    "gpi16", "gpi17", "gpi18", "gpi19",
115    "gpi20", "gpi21", "gpi22", "gpi23",
116    "gpi24", "gpi25", "gpi26", "gpi27"
117};
118
119static const char *gpo_p3_names[LPC32XX_GPO_P3_MAX] = {
120    "gpo00", "gpo01", "gpo02", "gpo03",
121    "gpo04", "gpo05", "gpo06", "gpo07",
122    "gpo08", "gpo09", "gpo10", "gpo11",
123    "gpo12", "gpo13", "gpo14", "gpo15",
124    "gpo16", "gpo17", "gpo18", "gpo19",
125    "gpo20", "gpo21", "gpo22", "gpo23"
126};
127
128static struct gpio_regs gpio_grp_regs_p0 = {
129    .inp_state = LPC32XX_GPIO_P0_INP_STATE,
130    .outp_set = LPC32XX_GPIO_P0_OUTP_SET,
131    .outp_clr = LPC32XX_GPIO_P0_OUTP_CLR,
132    .dir_set = LPC32XX_GPIO_P0_DIR_SET,
133    .dir_clr = LPC32XX_GPIO_P0_DIR_CLR,
134};
135
136static struct gpio_regs gpio_grp_regs_p1 = {
137    .inp_state = LPC32XX_GPIO_P1_INP_STATE,
138    .outp_set = LPC32XX_GPIO_P1_OUTP_SET,
139    .outp_clr = LPC32XX_GPIO_P1_OUTP_CLR,
140    .dir_set = LPC32XX_GPIO_P1_DIR_SET,
141    .dir_clr = LPC32XX_GPIO_P1_DIR_CLR,
142};
143
144static struct gpio_regs gpio_grp_regs_p2 = {
145    .inp_state = LPC32XX_GPIO_P2_INP_STATE,
146    .outp_set = LPC32XX_GPIO_P2_OUTP_SET,
147    .outp_clr = LPC32XX_GPIO_P2_OUTP_CLR,
148    .dir_set = LPC32XX_GPIO_P2_DIR_SET,
149    .dir_clr = LPC32XX_GPIO_P2_DIR_CLR,
150};
151
152static struct gpio_regs gpio_grp_regs_p3 = {
153    .inp_state = LPC32XX_GPIO_P3_INP_STATE,
154    .outp_state = LPC32XX_GPIO_P3_OUTP_STATE,
155    .outp_set = LPC32XX_GPIO_P3_OUTP_SET,
156    .outp_clr = LPC32XX_GPIO_P3_OUTP_CLR,
157    .dir_set = LPC32XX_GPIO_P2_DIR_SET,
158    .dir_clr = LPC32XX_GPIO_P2_DIR_CLR,
159};
160
161struct lpc32xx_gpio_chip {
162    struct gpio_chip chip;
163    struct gpio_regs *gpio_grp;
164};
165
166static inline struct lpc32xx_gpio_chip *to_lpc32xx_gpio(
167    struct gpio_chip *gpc)
168{
169    return container_of(gpc, struct lpc32xx_gpio_chip, chip);
170}
171
172static void __set_gpio_dir_p012(struct lpc32xx_gpio_chip *group,
173    unsigned pin, int input)
174{
175    if (input)
176        __raw_writel(GPIO012_PIN_TO_BIT(pin),
177            group->gpio_grp->dir_clr);
178    else
179        __raw_writel(GPIO012_PIN_TO_BIT(pin),
180            group->gpio_grp->dir_set);
181}
182
183static void __set_gpio_dir_p3(struct lpc32xx_gpio_chip *group,
184    unsigned pin, int input)
185{
186    u32 u = GPIO3_PIN_TO_BIT(pin);
187
188    if (input)
189        __raw_writel(u, group->gpio_grp->dir_clr);
190    else
191        __raw_writel(u, group->gpio_grp->dir_set);
192}
193
194static void __set_gpio_level_p012(struct lpc32xx_gpio_chip *group,
195    unsigned pin, int high)
196{
197    if (high)
198        __raw_writel(GPIO012_PIN_TO_BIT(pin),
199            group->gpio_grp->outp_set);
200    else
201        __raw_writel(GPIO012_PIN_TO_BIT(pin),
202            group->gpio_grp->outp_clr);
203}
204
205static void __set_gpio_level_p3(struct lpc32xx_gpio_chip *group,
206    unsigned pin, int high)
207{
208    u32 u = GPIO3_PIN_TO_BIT(pin);
209
210    if (high)
211        __raw_writel(u, group->gpio_grp->outp_set);
212    else
213        __raw_writel(u, group->gpio_grp->outp_clr);
214}
215
216static void __set_gpo_level_p3(struct lpc32xx_gpio_chip *group,
217    unsigned pin, int high)
218{
219    if (high)
220        __raw_writel(GPO3_PIN_TO_BIT(pin), group->gpio_grp->outp_set);
221    else
222        __raw_writel(GPO3_PIN_TO_BIT(pin), group->gpio_grp->outp_clr);
223}
224
225static int __get_gpio_state_p012(struct lpc32xx_gpio_chip *group,
226    unsigned pin)
227{
228    return GPIO012_PIN_IN_SEL(__raw_readl(group->gpio_grp->inp_state),
229        pin);
230}
231
232static int __get_gpio_state_p3(struct lpc32xx_gpio_chip *group,
233    unsigned pin)
234{
235    int state = __raw_readl(group->gpio_grp->inp_state);
236
237    /*
238     * P3 GPIO pin input mapping is not contiguous, GPIOP3-0..4 is mapped
239     * to bits 10..14, while GPIOP3-5 is mapped to bit 24.
240     */
241    return GPIO3_PIN_IN_SEL(state, pin);
242}
243
244static int __get_gpi_state_p3(struct lpc32xx_gpio_chip *group,
245    unsigned pin)
246{
247    return GPI3_PIN_IN_SEL(__raw_readl(group->gpio_grp->inp_state), pin);
248}
249
250static int __get_gpo_state_p3(struct lpc32xx_gpio_chip *group,
251    unsigned pin)
252{
253    return GPO3_PIN_IN_SEL(__raw_readl(group->gpio_grp->outp_state), pin);
254}
255
256/*
257 * GENERIC_GPIO primitives.
258 */
259static int lpc32xx_gpio_dir_input_p012(struct gpio_chip *chip,
260    unsigned pin)
261{
262    struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip);
263
264    __set_gpio_dir_p012(group, pin, 1);
265
266    return 0;
267}
268
269static int lpc32xx_gpio_dir_input_p3(struct gpio_chip *chip,
270    unsigned pin)
271{
272    struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip);
273
274    __set_gpio_dir_p3(group, pin, 1);
275
276    return 0;
277}
278
279static int lpc32xx_gpio_dir_in_always(struct gpio_chip *chip,
280    unsigned pin)
281{
282    return 0;
283}
284
285static int lpc32xx_gpio_get_value_p012(struct gpio_chip *chip, unsigned pin)
286{
287    struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip);
288
289    return __get_gpio_state_p012(group, pin);
290}
291
292static int lpc32xx_gpio_get_value_p3(struct gpio_chip *chip, unsigned pin)
293{
294    struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip);
295
296    return __get_gpio_state_p3(group, pin);
297}
298
299static int lpc32xx_gpi_get_value(struct gpio_chip *chip, unsigned pin)
300{
301    struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip);
302
303    return __get_gpi_state_p3(group, pin);
304}
305
306static int lpc32xx_gpio_dir_output_p012(struct gpio_chip *chip, unsigned pin,
307    int value)
308{
309    struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip);
310
311    __set_gpio_level_p012(group, pin, value);
312    __set_gpio_dir_p012(group, pin, 0);
313
314    return 0;
315}
316
317static int lpc32xx_gpio_dir_output_p3(struct gpio_chip *chip, unsigned pin,
318    int value)
319{
320    struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip);
321
322    __set_gpio_level_p3(group, pin, value);
323    __set_gpio_dir_p3(group, pin, 0);
324
325    return 0;
326}
327
328static int lpc32xx_gpio_dir_out_always(struct gpio_chip *chip, unsigned pin,
329    int value)
330{
331    struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip);
332
333    __set_gpo_level_p3(group, pin, value);
334    return 0;
335}
336
337static void lpc32xx_gpio_set_value_p012(struct gpio_chip *chip, unsigned pin,
338    int value)
339{
340    struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip);
341
342    __set_gpio_level_p012(group, pin, value);
343}
344
345static void lpc32xx_gpio_set_value_p3(struct gpio_chip *chip, unsigned pin,
346    int value)
347{
348    struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip);
349
350    __set_gpio_level_p3(group, pin, value);
351}
352
353static void lpc32xx_gpo_set_value(struct gpio_chip *chip, unsigned pin,
354    int value)
355{
356    struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip);
357
358    __set_gpo_level_p3(group, pin, value);
359}
360
361static int lpc32xx_gpo_get_value(struct gpio_chip *chip, unsigned pin)
362{
363    struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip);
364
365    return __get_gpo_state_p3(group, pin);
366}
367
368static int lpc32xx_gpio_request(struct gpio_chip *chip, unsigned pin)
369{
370    if (pin < chip->ngpio)
371        return 0;
372
373    return -EINVAL;
374}
375
376static int lpc32xx_gpio_to_irq_p01(struct gpio_chip *chip, unsigned offset)
377{
378    return IRQ_LPC32XX_P0_P1_IRQ;
379}
380
381static const char lpc32xx_gpio_to_irq_gpio_p3_table[] = {
382    IRQ_LPC32XX_GPIO_00,
383    IRQ_LPC32XX_GPIO_01,
384    IRQ_LPC32XX_GPIO_02,
385    IRQ_LPC32XX_GPIO_03,
386    IRQ_LPC32XX_GPIO_04,
387    IRQ_LPC32XX_GPIO_05,
388};
389
390static int lpc32xx_gpio_to_irq_gpio_p3(struct gpio_chip *chip, unsigned offset)
391{
392    if (offset < ARRAY_SIZE(lpc32xx_gpio_to_irq_gpio_p3_table))
393        return lpc32xx_gpio_to_irq_gpio_p3_table[offset];
394    return -ENXIO;
395}
396
397static const char lpc32xx_gpio_to_irq_gpi_p3_table[] = {
398    IRQ_LPC32XX_GPI_00,
399    IRQ_LPC32XX_GPI_01,
400    IRQ_LPC32XX_GPI_02,
401    IRQ_LPC32XX_GPI_03,
402    IRQ_LPC32XX_GPI_04,
403    IRQ_LPC32XX_GPI_05,
404    IRQ_LPC32XX_GPI_06,
405    IRQ_LPC32XX_GPI_07,
406    IRQ_LPC32XX_GPI_08,
407    IRQ_LPC32XX_GPI_09,
408    -ENXIO, /* 10 */
409    -ENXIO, /* 11 */
410    -ENXIO, /* 12 */
411    -ENXIO, /* 13 */
412    -ENXIO, /* 14 */
413    -ENXIO, /* 15 */
414    -ENXIO, /* 16 */
415    -ENXIO, /* 17 */
416    -ENXIO, /* 18 */
417    IRQ_LPC32XX_GPI_19,
418    -ENXIO, /* 20 */
419    -ENXIO, /* 21 */
420    -ENXIO, /* 22 */
421    -ENXIO, /* 23 */
422    -ENXIO, /* 24 */
423    -ENXIO, /* 25 */
424    -ENXIO, /* 26 */
425    -ENXIO, /* 27 */
426    IRQ_LPC32XX_GPI_28,
427};
428
429static int lpc32xx_gpio_to_irq_gpi_p3(struct gpio_chip *chip, unsigned offset)
430{
431    if (offset < ARRAY_SIZE(lpc32xx_gpio_to_irq_gpi_p3_table))
432        return lpc32xx_gpio_to_irq_gpi_p3_table[offset];
433    return -ENXIO;
434}
435
436static struct lpc32xx_gpio_chip lpc32xx_gpiochip[] = {
437    {
438        .chip = {
439            .label = "gpio_p0",
440            .direction_input = lpc32xx_gpio_dir_input_p012,
441            .get = lpc32xx_gpio_get_value_p012,
442            .direction_output = lpc32xx_gpio_dir_output_p012,
443            .set = lpc32xx_gpio_set_value_p012,
444            .request = lpc32xx_gpio_request,
445            .to_irq = lpc32xx_gpio_to_irq_p01,
446            .base = LPC32XX_GPIO_P0_GRP,
447            .ngpio = LPC32XX_GPIO_P0_MAX,
448            .names = gpio_p0_names,
449            .can_sleep = 0,
450        },
451        .gpio_grp = &gpio_grp_regs_p0,
452    },
453    {
454        .chip = {
455            .label = "gpio_p1",
456            .direction_input = lpc32xx_gpio_dir_input_p012,
457            .get = lpc32xx_gpio_get_value_p012,
458            .direction_output = lpc32xx_gpio_dir_output_p012,
459            .set = lpc32xx_gpio_set_value_p012,
460            .request = lpc32xx_gpio_request,
461            .to_irq = lpc32xx_gpio_to_irq_p01,
462            .base = LPC32XX_GPIO_P1_GRP,
463            .ngpio = LPC32XX_GPIO_P1_MAX,
464            .names = gpio_p1_names,
465            .can_sleep = 0,
466        },
467        .gpio_grp = &gpio_grp_regs_p1,
468    },
469    {
470        .chip = {
471            .label = "gpio_p2",
472            .direction_input = lpc32xx_gpio_dir_input_p012,
473            .get = lpc32xx_gpio_get_value_p012,
474            .direction_output = lpc32xx_gpio_dir_output_p012,
475            .set = lpc32xx_gpio_set_value_p012,
476            .request = lpc32xx_gpio_request,
477            .base = LPC32XX_GPIO_P2_GRP,
478            .ngpio = LPC32XX_GPIO_P2_MAX,
479            .names = gpio_p2_names,
480            .can_sleep = 0,
481        },
482        .gpio_grp = &gpio_grp_regs_p2,
483    },
484    {
485        .chip = {
486            .label = "gpio_p3",
487            .direction_input = lpc32xx_gpio_dir_input_p3,
488            .get = lpc32xx_gpio_get_value_p3,
489            .direction_output = lpc32xx_gpio_dir_output_p3,
490            .set = lpc32xx_gpio_set_value_p3,
491            .request = lpc32xx_gpio_request,
492            .to_irq = lpc32xx_gpio_to_irq_gpio_p3,
493            .base = LPC32XX_GPIO_P3_GRP,
494            .ngpio = LPC32XX_GPIO_P3_MAX,
495            .names = gpio_p3_names,
496            .can_sleep = 0,
497        },
498        .gpio_grp = &gpio_grp_regs_p3,
499    },
500    {
501        .chip = {
502            .label = "gpi_p3",
503            .direction_input = lpc32xx_gpio_dir_in_always,
504            .get = lpc32xx_gpi_get_value,
505            .request = lpc32xx_gpio_request,
506            .to_irq = lpc32xx_gpio_to_irq_gpi_p3,
507            .base = LPC32XX_GPI_P3_GRP,
508            .ngpio = LPC32XX_GPI_P3_MAX,
509            .names = gpi_p3_names,
510            .can_sleep = 0,
511        },
512        .gpio_grp = &gpio_grp_regs_p3,
513    },
514    {
515        .chip = {
516            .label = "gpo_p3",
517            .direction_output = lpc32xx_gpio_dir_out_always,
518            .set = lpc32xx_gpo_set_value,
519            .get = lpc32xx_gpo_get_value,
520            .request = lpc32xx_gpio_request,
521            .base = LPC32XX_GPO_P3_GRP,
522            .ngpio = LPC32XX_GPO_P3_MAX,
523            .names = gpo_p3_names,
524            .can_sleep = 0,
525        },
526        .gpio_grp = &gpio_grp_regs_p3,
527    },
528};
529
530static int lpc32xx_of_xlate(struct gpio_chip *gc,
531                const struct of_phandle_args *gpiospec, u32 *flags)
532{
533    /* Is this the correct bank? */
534    u32 bank = gpiospec->args[0];
535    if ((bank > ARRAY_SIZE(lpc32xx_gpiochip) ||
536        (gc != &lpc32xx_gpiochip[bank].chip)))
537        return -EINVAL;
538
539    if (flags)
540        *flags = gpiospec->args[2];
541    return gpiospec->args[1];
542}
543
544static int __devinit lpc32xx_gpio_probe(struct platform_device *pdev)
545{
546    int i;
547
548    for (i = 0; i < ARRAY_SIZE(lpc32xx_gpiochip); i++) {
549        if (pdev->dev.of_node) {
550            lpc32xx_gpiochip[i].chip.of_xlate = lpc32xx_of_xlate;
551            lpc32xx_gpiochip[i].chip.of_gpio_n_cells = 3;
552            lpc32xx_gpiochip[i].chip.of_node = pdev->dev.of_node;
553        }
554        gpiochip_add(&lpc32xx_gpiochip[i].chip);
555    }
556
557    return 0;
558}
559
560#ifdef CONFIG_OF
561static struct of_device_id lpc32xx_gpio_of_match[] __devinitdata = {
562    { .compatible = "nxp,lpc3220-gpio", },
563    { },
564};
565#endif
566
567static struct platform_driver lpc32xx_gpio_driver = {
568    .driver = {
569        .name = "lpc32xx-gpio",
570        .owner = THIS_MODULE,
571        .of_match_table = of_match_ptr(lpc32xx_gpio_of_match),
572    },
573    .probe = lpc32xx_gpio_probe,
574};
575
576module_platform_driver(lpc32xx_gpio_driver);
577

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