Root/drivers/ide/pdc202xx_new.c

1/*
2 * Promise TX2/TX4/TX2000/133 IDE driver
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version
7 * 2 of the License, or (at your option) any later version.
8 *
9 * Split from:
10 * linux/drivers/ide/pdc202xx.c Version 0.35 Mar. 30, 2002
11 * Copyright (C) 1998-2002 Andre Hedrick <andre@linux-ide.org>
12 * Copyright (C) 2005-2007 MontaVista Software, Inc.
13 * Portions Copyright (C) 1999 Promise Technology, Inc.
14 * Author: Frank Tiernan (frankt@promise.com)
15 * Released under terms of General Public License
16 */
17
18#include <linux/module.h>
19#include <linux/types.h>
20#include <linux/kernel.h>
21#include <linux/delay.h>
22#include <linux/pci.h>
23#include <linux/init.h>
24#include <linux/ide.h>
25
26#include <asm/io.h>
27
28#ifdef CONFIG_PPC_PMAC
29#include <asm/prom.h>
30#include <asm/pci-bridge.h>
31#endif
32
33#define DRV_NAME "pdc202xx_new"
34
35#undef DEBUG
36
37#ifdef DEBUG
38#define DBG(fmt, args...) printk("%s: " fmt, __func__, ## args)
39#else
40#define DBG(fmt, args...)
41#endif
42
43static u8 max_dma_rate(struct pci_dev *pdev)
44{
45    u8 mode;
46
47    switch(pdev->device) {
48        case PCI_DEVICE_ID_PROMISE_20277:
49        case PCI_DEVICE_ID_PROMISE_20276:
50        case PCI_DEVICE_ID_PROMISE_20275:
51        case PCI_DEVICE_ID_PROMISE_20271:
52        case PCI_DEVICE_ID_PROMISE_20269:
53            mode = 4;
54            break;
55        case PCI_DEVICE_ID_PROMISE_20270:
56        case PCI_DEVICE_ID_PROMISE_20268:
57            mode = 3;
58            break;
59        default:
60            return 0;
61    }
62
63    return mode;
64}
65
66/**
67 * get_indexed_reg - Get indexed register
68 * @hwif: for the port address
69 * @index: index of the indexed register
70 */
71static u8 get_indexed_reg(ide_hwif_t *hwif, u8 index)
72{
73    u8 value;
74
75    outb(index, hwif->dma_base + 1);
76    value = inb(hwif->dma_base + 3);
77
78    DBG("index[%02X] value[%02X]\n", index, value);
79    return value;
80}
81
82/**
83 * set_indexed_reg - Set indexed register
84 * @hwif: for the port address
85 * @index: index of the indexed register
86 */
87static void set_indexed_reg(ide_hwif_t *hwif, u8 index, u8 value)
88{
89    outb(index, hwif->dma_base + 1);
90    outb(value, hwif->dma_base + 3);
91    DBG("index[%02X] value[%02X]\n", index, value);
92}
93
94/*
95 * ATA Timing Tables based on 133 MHz PLL output clock.
96 *
97 * If the PLL outputs 100 MHz clock, the ASIC hardware will set
98 * the timing registers automatically when "set features" command is
99 * issued to the device. However, if the PLL output clock is 133 MHz,
100 * the following tables must be used.
101 */
102static struct pio_timing {
103    u8 reg0c, reg0d, reg13;
104} pio_timings [] = {
105    { 0xfb, 0x2b, 0xac }, /* PIO mode 0, IORDY off, Prefetch off */
106    { 0x46, 0x29, 0xa4 }, /* PIO mode 1, IORDY off, Prefetch off */
107    { 0x23, 0x26, 0x64 }, /* PIO mode 2, IORDY off, Prefetch off */
108    { 0x27, 0x0d, 0x35 }, /* PIO mode 3, IORDY on, Prefetch off */
109    { 0x23, 0x09, 0x25 }, /* PIO mode 4, IORDY on, Prefetch off */
110};
111
112static struct mwdma_timing {
113    u8 reg0e, reg0f;
114} mwdma_timings [] = {
115    { 0xdf, 0x5f }, /* MWDMA mode 0 */
116    { 0x6b, 0x27 }, /* MWDMA mode 1 */
117    { 0x69, 0x25 }, /* MWDMA mode 2 */
118};
119
120static struct udma_timing {
121    u8 reg10, reg11, reg12;
122} udma_timings [] = {
123    { 0x4a, 0x0f, 0xd5 }, /* UDMA mode 0 */
124    { 0x3a, 0x0a, 0xd0 }, /* UDMA mode 1 */
125    { 0x2a, 0x07, 0xcd }, /* UDMA mode 2 */
126    { 0x1a, 0x05, 0xcd }, /* UDMA mode 3 */
127    { 0x1a, 0x03, 0xcd }, /* UDMA mode 4 */
128    { 0x1a, 0x02, 0xcb }, /* UDMA mode 5 */
129    { 0x1a, 0x01, 0xcb }, /* UDMA mode 6 */
130};
131
132static void pdcnew_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive)
133{
134    struct pci_dev *dev = to_pci_dev(hwif->dev);
135    u8 adj = (drive->dn & 1) ? 0x08 : 0x00;
136    const u8 speed = drive->dma_mode;
137
138    /*
139     * IDE core issues SETFEATURES_XFER to the drive first (thanks to
140     * IDE_HFLAG_POST_SET_MODE in ->host_flags). PDC202xx hardware will
141     * automatically set the timing registers based on 100 MHz PLL output.
142     *
143     * As we set up the PLL to output 133 MHz for UltraDMA/133 capable
144     * chips, we must override the default register settings...
145     */
146    if (max_dma_rate(dev) == 4) {
147        u8 mode = speed & 0x07;
148
149        if (speed >= XFER_UDMA_0) {
150            set_indexed_reg(hwif, 0x10 + adj,
151                    udma_timings[mode].reg10);
152            set_indexed_reg(hwif, 0x11 + adj,
153                    udma_timings[mode].reg11);
154            set_indexed_reg(hwif, 0x12 + adj,
155                    udma_timings[mode].reg12);
156        } else {
157            set_indexed_reg(hwif, 0x0e + adj,
158                    mwdma_timings[mode].reg0e);
159            set_indexed_reg(hwif, 0x0f + adj,
160                    mwdma_timings[mode].reg0f);
161        }
162    } else if (speed == XFER_UDMA_2) {
163        /* Set tHOLD bit to 0 if using UDMA mode 2 */
164        u8 tmp = get_indexed_reg(hwif, 0x10 + adj);
165
166        set_indexed_reg(hwif, 0x10 + adj, tmp & 0x7f);
167     }
168}
169
170static void pdcnew_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
171{
172    struct pci_dev *dev = to_pci_dev(hwif->dev);
173    u8 adj = (drive->dn & 1) ? 0x08 : 0x00;
174    const u8 pio = drive->pio_mode - XFER_PIO_0;
175
176    if (max_dma_rate(dev) == 4) {
177        set_indexed_reg(hwif, 0x0c + adj, pio_timings[pio].reg0c);
178        set_indexed_reg(hwif, 0x0d + adj, pio_timings[pio].reg0d);
179        set_indexed_reg(hwif, 0x13 + adj, pio_timings[pio].reg13);
180    }
181}
182
183static u8 pdcnew_cable_detect(ide_hwif_t *hwif)
184{
185    if (get_indexed_reg(hwif, 0x0b) & 0x04)
186        return ATA_CBL_PATA40;
187    else
188        return ATA_CBL_PATA80;
189}
190
191static void pdcnew_reset(ide_drive_t *drive)
192{
193    /*
194     * Deleted this because it is redundant from the caller.
195     */
196    printk(KERN_WARNING "pdc202xx_new: %s channel reset.\n",
197        drive->hwif->channel ? "Secondary" : "Primary");
198}
199
200/**
201 * read_counter - Read the byte count registers
202 * @dma_base: for the port address
203 */
204static long read_counter(u32 dma_base)
205{
206    u32 pri_dma_base = dma_base, sec_dma_base = dma_base + 0x08;
207    u8 cnt0, cnt1, cnt2, cnt3;
208    long count = 0, last;
209    int retry = 3;
210
211    do {
212        last = count;
213
214        /* Read the current count */
215        outb(0x20, pri_dma_base + 0x01);
216        cnt0 = inb(pri_dma_base + 0x03);
217        outb(0x21, pri_dma_base + 0x01);
218        cnt1 = inb(pri_dma_base + 0x03);
219        outb(0x20, sec_dma_base + 0x01);
220        cnt2 = inb(sec_dma_base + 0x03);
221        outb(0x21, sec_dma_base + 0x01);
222        cnt3 = inb(sec_dma_base + 0x03);
223
224        count = (cnt3 << 23) | (cnt2 << 15) | (cnt1 << 8) | cnt0;
225
226        /*
227         * The 30-bit decrementing counter is read in 4 pieces.
228         * Incorrect value may be read when the most significant bytes
229         * are changing...
230         */
231    } while (retry-- && (((last ^ count) & 0x3fff8000) || last < count));
232
233    DBG("cnt0[%02X] cnt1[%02X] cnt2[%02X] cnt3[%02X]\n",
234          cnt0, cnt1, cnt2, cnt3);
235
236    return count;
237}
238
239/**
240 * detect_pll_input_clock - Detect the PLL input clock in Hz.
241 * @dma_base: for the port address
242 * E.g. 16949000 on 33 MHz PCI bus, i.e. half of the PCI clock.
243 */
244static long detect_pll_input_clock(unsigned long dma_base)
245{
246    struct timeval start_time, end_time;
247    long start_count, end_count;
248    long pll_input, usec_elapsed;
249    u8 scr1;
250
251    start_count = read_counter(dma_base);
252    do_gettimeofday(&start_time);
253
254    /* Start the test mode */
255    outb(0x01, dma_base + 0x01);
256    scr1 = inb(dma_base + 0x03);
257    DBG("scr1[%02X]\n", scr1);
258    outb(scr1 | 0x40, dma_base + 0x03);
259
260    /* Let the counter run for 10 ms. */
261    mdelay(10);
262
263    end_count = read_counter(dma_base);
264    do_gettimeofday(&end_time);
265
266    /* Stop the test mode */
267    outb(0x01, dma_base + 0x01);
268    scr1 = inb(dma_base + 0x03);
269    DBG("scr1[%02X]\n", scr1);
270    outb(scr1 & ~0x40, dma_base + 0x03);
271
272    /*
273     * Calculate the input clock in Hz
274     * (the clock counter is 30 bit wide and counts down)
275     */
276    usec_elapsed = (end_time.tv_sec - start_time.tv_sec) * 1000000 +
277        (end_time.tv_usec - start_time.tv_usec);
278    pll_input = ((start_count - end_count) & 0x3fffffff) / 10 *
279        (10000000 / usec_elapsed);
280
281    DBG("start[%ld] end[%ld]\n", start_count, end_count);
282
283    return pll_input;
284}
285
286#ifdef CONFIG_PPC_PMAC
287static void apple_kiwi_init(struct pci_dev *pdev)
288{
289    struct device_node *np = pci_device_to_OF_node(pdev);
290    u8 conf;
291
292    if (np == NULL || !of_device_is_compatible(np, "kiwi-root"))
293        return;
294
295    if (pdev->revision >= 0x03) {
296        /* Setup chip magic config stuff (from darwin) */
297        pci_read_config_byte (pdev, 0x40, &conf);
298        pci_write_config_byte(pdev, 0x40, (conf | 0x01));
299    }
300}
301#endif /* CONFIG_PPC_PMAC */
302
303static int init_chipset_pdcnew(struct pci_dev *dev)
304{
305    const char *name = DRV_NAME;
306    unsigned long dma_base = pci_resource_start(dev, 4);
307    unsigned long sec_dma_base = dma_base + 0x08;
308    long pll_input, pll_output, ratio;
309    int f, r;
310    u8 pll_ctl0, pll_ctl1;
311
312    if (dma_base == 0)
313        return -EFAULT;
314
315#ifdef CONFIG_PPC_PMAC
316    apple_kiwi_init(dev);
317#endif
318
319    /* Calculate the required PLL output frequency */
320    switch(max_dma_rate(dev)) {
321        case 4: /* it's 133 MHz for Ultra133 chips */
322            pll_output = 133333333;
323            break;
324        case 3: /* and 100 MHz for Ultra100 chips */
325        default:
326            pll_output = 100000000;
327            break;
328    }
329
330    /*
331     * Detect PLL input clock.
332     * On some systems, where PCI bus is running at non-standard clock rate
333     * (e.g. 25 or 40 MHz), we have to adjust the cycle time.
334     * PDC20268 and newer chips employ PLL circuit to help correct timing
335     * registers setting.
336     */
337    pll_input = detect_pll_input_clock(dma_base);
338    printk(KERN_INFO "%s %s: PLL input clock is %ld kHz\n",
339        name, pci_name(dev), pll_input / 1000);
340
341    /* Sanity check */
342    if (unlikely(pll_input < 5000000L || pll_input > 70000000L)) {
343        printk(KERN_ERR "%s %s: Bad PLL input clock %ld Hz, giving up!"
344            "\n", name, pci_name(dev), pll_input);
345        goto out;
346    }
347
348#ifdef DEBUG
349    DBG("pll_output is %ld Hz\n", pll_output);
350
351    /* Show the current clock value of PLL control register
352     * (maybe already configured by the BIOS)
353     */
354    outb(0x02, sec_dma_base + 0x01);
355    pll_ctl0 = inb(sec_dma_base + 0x03);
356    outb(0x03, sec_dma_base + 0x01);
357    pll_ctl1 = inb(sec_dma_base + 0x03);
358
359    DBG("pll_ctl[%02X][%02X]\n", pll_ctl0, pll_ctl1);
360#endif
361
362    /*
363     * Calculate the ratio of F, R and NO
364     * POUT = (F + 2) / (( R + 2) * NO)
365     */
366    ratio = pll_output / (pll_input / 1000);
367    if (ratio < 8600L) { /* 8.6x */
368        /* Using NO = 0x01, R = 0x0d */
369        r = 0x0d;
370    } else if (ratio < 12900L) { /* 12.9x */
371        /* Using NO = 0x01, R = 0x08 */
372        r = 0x08;
373    } else if (ratio < 16100L) { /* 16.1x */
374        /* Using NO = 0x01, R = 0x06 */
375        r = 0x06;
376    } else if (ratio < 64000L) { /* 64x */
377        r = 0x00;
378    } else {
379        /* Invalid ratio */
380        printk(KERN_ERR "%s %s: Bad ratio %ld, giving up!\n",
381            name, pci_name(dev), ratio);
382        goto out;
383    }
384
385    f = (ratio * (r + 2)) / 1000 - 2;
386
387    DBG("F[%d] R[%d] ratio*1000[%ld]\n", f, r, ratio);
388
389    if (unlikely(f < 0 || f > 127)) {
390        /* Invalid F */
391        printk(KERN_ERR "%s %s: F[%d] invalid!\n",
392            name, pci_name(dev), f);
393        goto out;
394    }
395
396    pll_ctl0 = (u8) f;
397    pll_ctl1 = (u8) r;
398
399    DBG("Writing pll_ctl[%02X][%02X]\n", pll_ctl0, pll_ctl1);
400
401    outb(0x02, sec_dma_base + 0x01);
402    outb(pll_ctl0, sec_dma_base + 0x03);
403    outb(0x03, sec_dma_base + 0x01);
404    outb(pll_ctl1, sec_dma_base + 0x03);
405
406    /* Wait the PLL circuit to be stable */
407    mdelay(30);
408
409#ifdef DEBUG
410    /*
411     * Show the current clock value of PLL control register
412     */
413    outb(0x02, sec_dma_base + 0x01);
414    pll_ctl0 = inb(sec_dma_base + 0x03);
415    outb(0x03, sec_dma_base + 0x01);
416    pll_ctl1 = inb(sec_dma_base + 0x03);
417
418    DBG("pll_ctl[%02X][%02X]\n", pll_ctl0, pll_ctl1);
419#endif
420
421 out:
422    return 0;
423}
424
425static struct pci_dev * __devinit pdc20270_get_dev2(struct pci_dev *dev)
426{
427    struct pci_dev *dev2;
428
429    dev2 = pci_get_slot(dev->bus, PCI_DEVFN(PCI_SLOT(dev->devfn) + 1,
430                        PCI_FUNC(dev->devfn)));
431
432    if (dev2 &&
433        dev2->vendor == dev->vendor &&
434        dev2->device == dev->device) {
435
436        if (dev2->irq != dev->irq) {
437            dev2->irq = dev->irq;
438            printk(KERN_INFO DRV_NAME " %s: PCI config space "
439                "interrupt fixed\n", pci_name(dev));
440        }
441
442        return dev2;
443    }
444
445    return NULL;
446}
447
448static const struct ide_port_ops pdcnew_port_ops = {
449    .set_pio_mode = pdcnew_set_pio_mode,
450    .set_dma_mode = pdcnew_set_dma_mode,
451    .resetproc = pdcnew_reset,
452    .cable_detect = pdcnew_cable_detect,
453};
454
455#define DECLARE_PDCNEW_DEV(udma) \
456    { \
457        .name = DRV_NAME, \
458        .init_chipset = init_chipset_pdcnew, \
459        .port_ops = &pdcnew_port_ops, \
460        .host_flags = IDE_HFLAG_POST_SET_MODE | \
461                  IDE_HFLAG_ERROR_STOPS_FIFO | \
462                  IDE_HFLAG_OFF_BOARD, \
463        .pio_mask = ATA_PIO4, \
464        .mwdma_mask = ATA_MWDMA2, \
465        .udma_mask = udma, \
466    }
467
468static const struct ide_port_info pdcnew_chipsets[] __devinitdata = {
469    /* 0: PDC202{68,70} */ DECLARE_PDCNEW_DEV(ATA_UDMA5),
470    /* 1: PDC202{69,71,75,76,77} */ DECLARE_PDCNEW_DEV(ATA_UDMA6),
471};
472
473/**
474 * pdc202new_init_one - called when a pdc202xx is found
475 * @dev: the pdc202new device
476 * @id: the matching pci id
477 *
478 * Called when the PCI registration layer (or the IDE initialization)
479 * finds a device matching our IDE device tables.
480 */
481 
482static int __devinit pdc202new_init_one(struct pci_dev *dev, const struct pci_device_id *id)
483{
484    const struct ide_port_info *d = &pdcnew_chipsets[id->driver_data];
485    struct pci_dev *bridge = dev->bus->self;
486
487    if (dev->device == PCI_DEVICE_ID_PROMISE_20270 && bridge &&
488        bridge->vendor == PCI_VENDOR_ID_DEC &&
489        bridge->device == PCI_DEVICE_ID_DEC_21150) {
490        struct pci_dev *dev2;
491
492        if (PCI_SLOT(dev->devfn) & 2)
493            return -ENODEV;
494
495        dev2 = pdc20270_get_dev2(dev);
496
497        if (dev2) {
498            int ret = ide_pci_init_two(dev, dev2, d, NULL);
499            if (ret < 0)
500                pci_dev_put(dev2);
501            return ret;
502        }
503    }
504
505    if (dev->device == PCI_DEVICE_ID_PROMISE_20276 && bridge &&
506        bridge->vendor == PCI_VENDOR_ID_INTEL &&
507        (bridge->device == PCI_DEVICE_ID_INTEL_I960 ||
508         bridge->device == PCI_DEVICE_ID_INTEL_I960RM)) {
509        printk(KERN_INFO DRV_NAME " %s: attached to I2O RAID controller,"
510            " skipping\n", pci_name(dev));
511        return -ENODEV;
512    }
513
514    return ide_pci_init_one(dev, d, NULL);
515}
516
517static void __devexit pdc202new_remove(struct pci_dev *dev)
518{
519    struct ide_host *host = pci_get_drvdata(dev);
520    struct pci_dev *dev2 = host->dev[1] ? to_pci_dev(host->dev[1]) : NULL;
521
522    ide_pci_remove(dev);
523    pci_dev_put(dev2);
524}
525
526static const struct pci_device_id pdc202new_pci_tbl[] = {
527    { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20268), 0 },
528    { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20269), 1 },
529    { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20270), 0 },
530    { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20271), 1 },
531    { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20275), 1 },
532    { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20276), 1 },
533    { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20277), 1 },
534    { 0, },
535};
536MODULE_DEVICE_TABLE(pci, pdc202new_pci_tbl);
537
538static struct pci_driver pdc202new_pci_driver = {
539    .name = "Promise_IDE",
540    .id_table = pdc202new_pci_tbl,
541    .probe = pdc202new_init_one,
542    .remove = __devexit_p(pdc202new_remove),
543    .suspend = ide_pci_suspend,
544    .resume = ide_pci_resume,
545};
546
547static int __init pdc202new_ide_init(void)
548{
549    return ide_pci_register_driver(&pdc202new_pci_driver);
550}
551
552static void __exit pdc202new_ide_exit(void)
553{
554    pci_unregister_driver(&pdc202new_pci_driver);
555}
556
557module_init(pdc202new_ide_init);
558module_exit(pdc202new_ide_exit);
559
560MODULE_AUTHOR("Andre Hedrick, Frank Tiernan");
561MODULE_DESCRIPTION("PCI driver module for Promise PDC20268 and higher");
562MODULE_LICENSE("GPL");
563

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