Root/drivers/iio/frequency/ad9523.c

1/*
2 * AD9523 SPI Low Jitter Clock Generator
3 *
4 * Copyright 2012 Analog Devices Inc.
5 *
6 * Licensed under the GPL-2.
7 */
8
9#include <linux/device.h>
10#include <linux/kernel.h>
11#include <linux/slab.h>
12#include <linux/sysfs.h>
13#include <linux/spi/spi.h>
14#include <linux/regulator/consumer.h>
15#include <linux/err.h>
16#include <linux/module.h>
17#include <linux/delay.h>
18
19#include <linux/iio/iio.h>
20#include <linux/iio/sysfs.h>
21#include <linux/iio/frequency/ad9523.h>
22
23#define AD9523_READ (1 << 15)
24#define AD9523_WRITE (0 << 15)
25#define AD9523_CNT(x) (((x) - 1) << 13)
26#define AD9523_ADDR(x) ((x) & 0xFFF)
27
28#define AD9523_R1B (1 << 16)
29#define AD9523_R2B (2 << 16)
30#define AD9523_R3B (3 << 16)
31#define AD9523_TRANSF_LEN(x) ((x) >> 16)
32
33#define AD9523_SERIAL_PORT_CONFIG (AD9523_R1B | 0x0)
34#define AD9523_VERSION_REGISTER (AD9523_R1B | 0x2)
35#define AD9523_PART_REGISTER (AD9523_R1B | 0x3)
36#define AD9523_READBACK_CTRL (AD9523_R1B | 0x4)
37
38#define AD9523_EEPROM_CUSTOMER_VERSION_ID (AD9523_R2B | 0x6)
39
40#define AD9523_PLL1_REF_A_DIVIDER (AD9523_R2B | 0x11)
41#define AD9523_PLL1_REF_B_DIVIDER (AD9523_R2B | 0x13)
42#define AD9523_PLL1_REF_TEST_DIVIDER (AD9523_R1B | 0x14)
43#define AD9523_PLL1_FEEDBACK_DIVIDER (AD9523_R2B | 0x17)
44#define AD9523_PLL1_CHARGE_PUMP_CTRL (AD9523_R2B | 0x19)
45#define AD9523_PLL1_INPUT_RECEIVERS_CTRL (AD9523_R1B | 0x1A)
46#define AD9523_PLL1_REF_CTRL (AD9523_R1B | 0x1B)
47#define AD9523_PLL1_MISC_CTRL (AD9523_R1B | 0x1C)
48#define AD9523_PLL1_LOOP_FILTER_CTRL (AD9523_R1B | 0x1D)
49
50#define AD9523_PLL2_CHARGE_PUMP (AD9523_R1B | 0xF0)
51#define AD9523_PLL2_FEEDBACK_DIVIDER_AB (AD9523_R1B | 0xF1)
52#define AD9523_PLL2_CTRL (AD9523_R1B | 0xF2)
53#define AD9523_PLL2_VCO_CTRL (AD9523_R1B | 0xF3)
54#define AD9523_PLL2_VCO_DIVIDER (AD9523_R1B | 0xF4)
55#define AD9523_PLL2_LOOP_FILTER_CTRL (AD9523_R2B | 0xF6)
56#define AD9523_PLL2_R2_DIVIDER (AD9523_R1B | 0xF7)
57
58#define AD9523_CHANNEL_CLOCK_DIST(ch) (AD9523_R3B | (0x192 + 3 * ch))
59
60#define AD9523_PLL1_OUTPUT_CTRL (AD9523_R1B | 0x1BA)
61#define AD9523_PLL1_OUTPUT_CHANNEL_CTRL (AD9523_R1B | 0x1BB)
62
63#define AD9523_READBACK_0 (AD9523_R1B | 0x22C)
64#define AD9523_READBACK_1 (AD9523_R1B | 0x22D)
65
66#define AD9523_STATUS_SIGNALS (AD9523_R3B | 0x232)
67#define AD9523_POWER_DOWN_CTRL (AD9523_R1B | 0x233)
68#define AD9523_IO_UPDATE (AD9523_R1B | 0x234)
69
70#define AD9523_EEPROM_DATA_XFER_STATUS (AD9523_R1B | 0xB00)
71#define AD9523_EEPROM_ERROR_READBACK (AD9523_R1B | 0xB01)
72#define AD9523_EEPROM_CTRL1 (AD9523_R1B | 0xB02)
73#define AD9523_EEPROM_CTRL2 (AD9523_R1B | 0xB03)
74
75/* AD9523_SERIAL_PORT_CONFIG */
76
77#define AD9523_SER_CONF_SDO_ACTIVE (1 << 7)
78#define AD9523_SER_CONF_SOFT_RESET (1 << 5)
79
80/* AD9523_READBACK_CTRL */
81#define AD9523_READBACK_CTRL_READ_BUFFERED (1 << 0)
82
83/* AD9523_PLL1_CHARGE_PUMP_CTRL */
84#define AD9523_PLL1_CHARGE_PUMP_CURRENT_nA(x) (((x) / 500) & 0x7F)
85#define AD9523_PLL1_CHARGE_PUMP_TRISTATE (1 << 7)
86#define AD9523_PLL1_CHARGE_PUMP_MODE_NORMAL (3 << 8)
87#define AD9523_PLL1_CHARGE_PUMP_MODE_PUMP_DOWN (2 << 8)
88#define AD9523_PLL1_CHARGE_PUMP_MODE_PUMP_UP (1 << 8)
89#define AD9523_PLL1_CHARGE_PUMP_MODE_TRISTATE (0 << 8)
90#define AD9523_PLL1_BACKLASH_PW_MIN (0 << 10)
91#define AD9523_PLL1_BACKLASH_PW_LOW (1 << 10)
92#define AD9523_PLL1_BACKLASH_PW_HIGH (2 << 10)
93#define AD9523_PLL1_BACKLASH_PW_MAX (3 << 10)
94
95/* AD9523_PLL1_INPUT_RECEIVERS_CTRL */
96#define AD9523_PLL1_REF_TEST_RCV_EN (1 << 7)
97#define AD9523_PLL1_REFB_DIFF_RCV_EN (1 << 6)
98#define AD9523_PLL1_REFA_DIFF_RCV_EN (1 << 5)
99#define AD9523_PLL1_REFB_RCV_EN (1 << 4)
100#define AD9523_PLL1_REFA_RCV_EN (1 << 3)
101#define AD9523_PLL1_REFA_REFB_PWR_CTRL_EN (1 << 2)
102#define AD9523_PLL1_OSC_IN_CMOS_NEG_INP_EN (1 << 1)
103#define AD9523_PLL1_OSC_IN_DIFF_EN (1 << 0)
104
105/* AD9523_PLL1_REF_CTRL */
106#define AD9523_PLL1_BYPASS_REF_TEST_DIV_EN (1 << 7)
107#define AD9523_PLL1_BYPASS_FEEDBACK_DIV_EN (1 << 6)
108#define AD9523_PLL1_ZERO_DELAY_MODE_INT (1 << 5)
109#define AD9523_PLL1_ZERO_DELAY_MODE_EXT (0 << 5)
110#define AD9523_PLL1_OSC_IN_PLL_FEEDBACK_EN (1 << 4)
111#define AD9523_PLL1_ZD_IN_CMOS_NEG_INP_EN (1 << 3)
112#define AD9523_PLL1_ZD_IN_DIFF_EN (1 << 2)
113#define AD9523_PLL1_REFB_CMOS_NEG_INP_EN (1 << 1)
114#define AD9523_PLL1_REFA_CMOS_NEG_INP_EN (1 << 0)
115
116/* AD9523_PLL1_MISC_CTRL */
117#define AD9523_PLL1_REFB_INDEP_DIV_CTRL_EN (1 << 7)
118#define AD9523_PLL1_OSC_CTRL_FAIL_VCC_BY2_EN (1 << 6)
119#define AD9523_PLL1_REF_MODE(x) ((x) << 2)
120#define AD9523_PLL1_BYPASS_REFB_DIV (1 << 1)
121#define AD9523_PLL1_BYPASS_REFA_DIV (1 << 0)
122
123/* AD9523_PLL1_LOOP_FILTER_CTRL */
124#define AD9523_PLL1_LOOP_FILTER_RZERO(x) ((x) & 0xF)
125
126/* AD9523_PLL2_CHARGE_PUMP */
127#define AD9523_PLL2_CHARGE_PUMP_CURRENT_nA(x) ((x) / 3500)
128
129/* AD9523_PLL2_FEEDBACK_DIVIDER_AB */
130#define AD9523_PLL2_FB_NDIV_A_CNT(x) (((x) & 0x3) << 6)
131#define AD9523_PLL2_FB_NDIV_B_CNT(x) (((x) & 0x3F) << 0)
132#define AD9523_PLL2_FB_NDIV(a, b) (4 * (b) + (a))
133
134/* AD9523_PLL2_CTRL */
135#define AD9523_PLL2_CHARGE_PUMP_MODE_NORMAL (3 << 0)
136#define AD9523_PLL2_CHARGE_PUMP_MODE_PUMP_DOWN (2 << 0)
137#define AD9523_PLL2_CHARGE_PUMP_MODE_PUMP_UP (1 << 0)
138#define AD9523_PLL2_CHARGE_PUMP_MODE_TRISTATE (0 << 0)
139#define AD9523_PLL2_BACKLASH_PW_MIN (0 << 2)
140#define AD9523_PLL2_BACKLASH_PW_LOW (1 << 2)
141#define AD9523_PLL2_BACKLASH_PW_HIGH (2 << 2)
142#define AD9523_PLL2_BACKLASH_PW_MAX (3 << 1)
143#define AD9523_PLL2_BACKLASH_CTRL_EN (1 << 4)
144#define AD9523_PLL2_FREQ_DOUBLER_EN (1 << 5)
145#define AD9523_PLL2_LOCK_DETECT_PWR_DOWN_EN (1 << 7)
146
147/* AD9523_PLL2_VCO_CTRL */
148#define AD9523_PLL2_VCO_CALIBRATE (1 << 1)
149#define AD9523_PLL2_FORCE_VCO_MIDSCALE (1 << 2)
150#define AD9523_PLL2_FORCE_REFERENCE_VALID (1 << 3)
151#define AD9523_PLL2_FORCE_RELEASE_SYNC (1 << 4)
152
153/* AD9523_PLL2_VCO_DIVIDER */
154#define AD9523_PLL2_VCO_DIV_M1(x) ((((x) - 3) & 0x3) << 0)
155#define AD9523_PLL2_VCO_DIV_M2(x) ((((x) - 3) & 0x3) << 4)
156#define AD9523_PLL2_VCO_DIV_M1_PWR_DOWN_EN (1 << 2)
157#define AD9523_PLL2_VCO_DIV_M2_PWR_DOWN_EN (1 << 6)
158
159/* AD9523_PLL2_LOOP_FILTER_CTRL */
160#define AD9523_PLL2_LOOP_FILTER_CPOLE1(x) (((x) & 0x7) << 0)
161#define AD9523_PLL2_LOOP_FILTER_RZERO(x) (((x) & 0x7) << 3)
162#define AD9523_PLL2_LOOP_FILTER_RPOLE2(x) (((x) & 0x7) << 6)
163#define AD9523_PLL2_LOOP_FILTER_RZERO_BYPASS_EN (1 << 8)
164
165/* AD9523_PLL2_R2_DIVIDER */
166#define AD9523_PLL2_R2_DIVIDER_VAL(x) (((x) & 0x1F) << 0)
167
168/* AD9523_CHANNEL_CLOCK_DIST */
169#define AD9523_CLK_DIST_DIV_PHASE(x) (((x) & 0x3F) << 18)
170#define AD9523_CLK_DIST_DIV_PHASE_REV(x) ((ret >> 18) & 0x3F)
171#define AD9523_CLK_DIST_DIV(x) ((((x) - 1) & 0x3FF) << 8)
172#define AD9523_CLK_DIST_DIV_REV(x) (((ret >> 8) & 0x3FF) + 1)
173#define AD9523_CLK_DIST_INV_DIV_OUTPUT_EN (1 << 7)
174#define AD9523_CLK_DIST_IGNORE_SYNC_EN (1 << 6)
175#define AD9523_CLK_DIST_PWR_DOWN_EN (1 << 5)
176#define AD9523_CLK_DIST_LOW_PWR_MODE_EN (1 << 4)
177#define AD9523_CLK_DIST_DRIVER_MODE(x) (((x) & 0xF) << 0)
178
179/* AD9523_PLL1_OUTPUT_CTRL */
180#define AD9523_PLL1_OUTP_CTRL_VCO_DIV_SEL_CH6_M2 (1 << 7)
181#define AD9523_PLL1_OUTP_CTRL_VCO_DIV_SEL_CH5_M2 (1 << 6)
182#define AD9523_PLL1_OUTP_CTRL_VCO_DIV_SEL_CH4_M2 (1 << 5)
183#define AD9523_PLL1_OUTP_CTRL_CMOS_DRV_WEAK (1 << 4)
184#define AD9523_PLL1_OUTP_CTRL_OUTPUT_DIV_1 (0 << 0)
185#define AD9523_PLL1_OUTP_CTRL_OUTPUT_DIV_2 (1 << 0)
186#define AD9523_PLL1_OUTP_CTRL_OUTPUT_DIV_4 (2 << 0)
187#define AD9523_PLL1_OUTP_CTRL_OUTPUT_DIV_8 (4 << 0)
188#define AD9523_PLL1_OUTP_CTRL_OUTPUT_DIV_16 (8 << 0)
189
190/* AD9523_PLL1_OUTPUT_CHANNEL_CTRL */
191#define AD9523_PLL1_OUTP_CH_CTRL_OUTPUT_PWR_DOWN_EN (1 << 7)
192#define AD9523_PLL1_OUTP_CH_CTRL_VCO_DIV_SEL_CH9_M2 (1 << 6)
193#define AD9523_PLL1_OUTP_CH_CTRL_VCO_DIV_SEL_CH8_M2 (1 << 5)
194#define AD9523_PLL1_OUTP_CH_CTRL_VCO_DIV_SEL_CH7_M2 (1 << 4)
195#define AD9523_PLL1_OUTP_CH_CTRL_VCXO_SRC_SEL_CH3 (1 << 3)
196#define AD9523_PLL1_OUTP_CH_CTRL_VCXO_SRC_SEL_CH2 (1 << 2)
197#define AD9523_PLL1_OUTP_CH_CTRL_VCXO_SRC_SEL_CH1 (1 << 1)
198#define AD9523_PLL1_OUTP_CH_CTRL_VCXO_SRC_SEL_CH0 (1 << 0)
199
200/* AD9523_READBACK_0 */
201#define AD9523_READBACK_0_STAT_PLL2_REF_CLK (1 << 7)
202#define AD9523_READBACK_0_STAT_PLL2_FB_CLK (1 << 6)
203#define AD9523_READBACK_0_STAT_VCXO (1 << 5)
204#define AD9523_READBACK_0_STAT_REF_TEST (1 << 4)
205#define AD9523_READBACK_0_STAT_REFB (1 << 3)
206#define AD9523_READBACK_0_STAT_REFA (1 << 2)
207#define AD9523_READBACK_0_STAT_PLL2_LD (1 << 1)
208#define AD9523_READBACK_0_STAT_PLL1_LD (1 << 0)
209
210/* AD9523_READBACK_1 */
211#define AD9523_READBACK_1_HOLDOVER_ACTIVE (1 << 3)
212#define AD9523_READBACK_1_AUTOMODE_SEL_REFB (1 << 2)
213#define AD9523_READBACK_1_VCO_CALIB_IN_PROGRESS (1 << 0)
214
215/* AD9523_STATUS_SIGNALS */
216#define AD9523_STATUS_SIGNALS_SYNC_MAN_CTRL (1 << 16)
217#define AD9523_STATUS_MONITOR_01_PLL12_LOCKED (0x302)
218/* AD9523_POWER_DOWN_CTRL */
219#define AD9523_POWER_DOWN_CTRL_PLL1_PWR_DOWN (1 << 2)
220#define AD9523_POWER_DOWN_CTRL_PLL2_PWR_DOWN (1 << 1)
221#define AD9523_POWER_DOWN_CTRL_DIST_PWR_DOWN (1 << 0)
222
223/* AD9523_IO_UPDATE */
224#define AD9523_IO_UPDATE_EN (1 << 0)
225
226/* AD9523_EEPROM_DATA_XFER_STATUS */
227#define AD9523_EEPROM_DATA_XFER_IN_PROGRESS (1 << 0)
228
229/* AD9523_EEPROM_ERROR_READBACK */
230#define AD9523_EEPROM_ERROR_READBACK_FAIL (1 << 0)
231
232/* AD9523_EEPROM_CTRL1 */
233#define AD9523_EEPROM_CTRL1_SOFT_EEPROM (1 << 1)
234#define AD9523_EEPROM_CTRL1_EEPROM_WRITE_PROT_DIS (1 << 0)
235
236/* AD9523_EEPROM_CTRL2 */
237#define AD9523_EEPROM_CTRL2_REG2EEPROM (1 << 0)
238
239#define AD9523_NUM_CHAN 14
240#define AD9523_NUM_CHAN_ALT_CLK_SRC 10
241
242/* Helpers to avoid excess line breaks */
243#define AD_IFE(_pde, _a, _b) ((pdata->_pde) ? _a : _b)
244#define AD_IF(_pde, _a) AD_IFE(_pde, _a, 0)
245
246enum {
247    AD9523_STAT_PLL1_LD,
248    AD9523_STAT_PLL2_LD,
249    AD9523_STAT_REFA,
250    AD9523_STAT_REFB,
251    AD9523_STAT_REF_TEST,
252    AD9523_STAT_VCXO,
253    AD9523_STAT_PLL2_FB_CLK,
254    AD9523_STAT_PLL2_REF_CLK,
255    AD9523_SYNC,
256    AD9523_EEPROM,
257};
258
259enum {
260    AD9523_VCO1,
261    AD9523_VCO2,
262    AD9523_VCXO,
263    AD9523_NUM_CLK_SRC,
264};
265
266struct ad9523_state {
267    struct spi_device *spi;
268    struct regulator *reg;
269    struct ad9523_platform_data *pdata;
270    struct iio_chan_spec ad9523_channels[AD9523_NUM_CHAN];
271
272    unsigned long vcxo_freq;
273    unsigned long vco_freq;
274    unsigned long vco_out_freq[AD9523_NUM_CLK_SRC];
275    unsigned char vco_out_map[AD9523_NUM_CHAN_ALT_CLK_SRC];
276
277    /*
278     * DMA (thus cache coherency maintenance) requires the
279     * transfer buffers to live in their own cache lines.
280     */
281    union {
282        __be32 d32;
283        u8 d8[4];
284    } data[2] ____cacheline_aligned;
285};
286
287static int ad9523_read(struct iio_dev *indio_dev, unsigned addr)
288{
289    struct ad9523_state *st = iio_priv(indio_dev);
290    struct spi_message m;
291    int ret;
292
293    /* We encode the register size 1..3 bytes into the register address.
294     * On transfer we get the size from the register datum, and make sure
295     * the result is properly aligned.
296     */
297
298    struct spi_transfer t[] = {
299        {
300            .tx_buf = &st->data[0].d8[2],
301            .len = 2,
302        }, {
303            .rx_buf = &st->data[1].d8[4 - AD9523_TRANSF_LEN(addr)],
304            .len = AD9523_TRANSF_LEN(addr),
305        },
306    };
307
308    spi_message_init(&m);
309    spi_message_add_tail(&t[0], &m);
310    spi_message_add_tail(&t[1], &m);
311
312    st->data[0].d32 = cpu_to_be32(AD9523_READ |
313                      AD9523_CNT(AD9523_TRANSF_LEN(addr)) |
314                      AD9523_ADDR(addr));
315
316    ret = spi_sync(st->spi, &m);
317    if (ret < 0)
318        dev_err(&indio_dev->dev, "read failed (%d)", ret);
319    else
320        ret = be32_to_cpu(st->data[1].d32) & (0xFFFFFF >>
321                  (8 * (3 - AD9523_TRANSF_LEN(addr))));
322
323    return ret;
324};
325
326static int ad9523_write(struct iio_dev *indio_dev, unsigned addr, unsigned val)
327{
328    struct ad9523_state *st = iio_priv(indio_dev);
329    struct spi_message m;
330    int ret;
331    struct spi_transfer t[] = {
332        {
333            .tx_buf = &st->data[0].d8[2],
334            .len = 2,
335        }, {
336            .tx_buf = &st->data[1].d8[4 - AD9523_TRANSF_LEN(addr)],
337            .len = AD9523_TRANSF_LEN(addr),
338        },
339    };
340
341    spi_message_init(&m);
342    spi_message_add_tail(&t[0], &m);
343    spi_message_add_tail(&t[1], &m);
344
345    st->data[0].d32 = cpu_to_be32(AD9523_WRITE |
346                      AD9523_CNT(AD9523_TRANSF_LEN(addr)) |
347                      AD9523_ADDR(addr));
348    st->data[1].d32 = cpu_to_be32(val);
349
350    ret = spi_sync(st->spi, &m);
351
352    if (ret < 0)
353        dev_err(&indio_dev->dev, "write failed (%d)", ret);
354
355    return ret;
356}
357
358static int ad9523_io_update(struct iio_dev *indio_dev)
359{
360    return ad9523_write(indio_dev, AD9523_IO_UPDATE, AD9523_IO_UPDATE_EN);
361}
362
363static int ad9523_vco_out_map(struct iio_dev *indio_dev,
364                  unsigned ch, unsigned out)
365{
366    struct ad9523_state *st = iio_priv(indio_dev);
367    int ret;
368    unsigned mask;
369
370    switch (ch) {
371    case 0 ... 3:
372        ret = ad9523_read(indio_dev, AD9523_PLL1_OUTPUT_CHANNEL_CTRL);
373        if (ret < 0)
374            break;
375        mask = AD9523_PLL1_OUTP_CH_CTRL_VCXO_SRC_SEL_CH0 << ch;
376        if (out) {
377            ret |= mask;
378            out = 2;
379        } else {
380            ret &= ~mask;
381        }
382        ret = ad9523_write(indio_dev,
383                   AD9523_PLL1_OUTPUT_CHANNEL_CTRL, ret);
384        break;
385    case 4 ... 6:
386        ret = ad9523_read(indio_dev, AD9523_PLL1_OUTPUT_CTRL);
387        if (ret < 0)
388            break;
389        mask = AD9523_PLL1_OUTP_CTRL_VCO_DIV_SEL_CH4_M2 << (ch - 4);
390        if (out)
391            ret |= mask;
392        else
393            ret &= ~mask;
394        ret = ad9523_write(indio_dev, AD9523_PLL1_OUTPUT_CTRL, ret);
395        break;
396    case 7 ... 9:
397        ret = ad9523_read(indio_dev, AD9523_PLL1_OUTPUT_CHANNEL_CTRL);
398        if (ret < 0)
399            break;
400        mask = AD9523_PLL1_OUTP_CH_CTRL_VCO_DIV_SEL_CH7_M2 << (ch - 7);
401        if (out)
402            ret |= mask;
403        else
404            ret &= ~mask;
405        ret = ad9523_write(indio_dev,
406                   AD9523_PLL1_OUTPUT_CHANNEL_CTRL, ret);
407        break;
408    default:
409        return 0;
410    }
411
412    st->vco_out_map[ch] = out;
413
414    return ret;
415}
416
417static int ad9523_set_clock_provider(struct iio_dev *indio_dev,
418                  unsigned ch, unsigned long freq)
419{
420    struct ad9523_state *st = iio_priv(indio_dev);
421    long tmp1, tmp2;
422    bool use_alt_clk_src;
423
424    switch (ch) {
425    case 0 ... 3:
426        use_alt_clk_src = (freq == st->vco_out_freq[AD9523_VCXO]);
427        break;
428    case 4 ... 9:
429        tmp1 = st->vco_out_freq[AD9523_VCO1] / freq;
430        tmp2 = st->vco_out_freq[AD9523_VCO2] / freq;
431        tmp1 *= freq;
432        tmp2 *= freq;
433        use_alt_clk_src = (abs(tmp1 - freq) > abs(tmp2 - freq));
434        break;
435    default:
436        /* Ch 10..14: No action required, return success */
437        return 0;
438    }
439
440    return ad9523_vco_out_map(indio_dev, ch, use_alt_clk_src);
441}
442
443static int ad9523_store_eeprom(struct iio_dev *indio_dev)
444{
445    int ret, tmp;
446
447    ret = ad9523_write(indio_dev, AD9523_EEPROM_CTRL1,
448               AD9523_EEPROM_CTRL1_EEPROM_WRITE_PROT_DIS);
449    if (ret < 0)
450        return ret;
451    ret = ad9523_write(indio_dev, AD9523_EEPROM_CTRL2,
452               AD9523_EEPROM_CTRL2_REG2EEPROM);
453    if (ret < 0)
454        return ret;
455
456    tmp = 4;
457    do {
458        msleep(16);
459        ret = ad9523_read(indio_dev,
460                  AD9523_EEPROM_DATA_XFER_STATUS);
461        if (ret < 0)
462            return ret;
463    } while ((ret & AD9523_EEPROM_DATA_XFER_IN_PROGRESS) && tmp--);
464
465    ret = ad9523_write(indio_dev, AD9523_EEPROM_CTRL1, 0);
466    if (ret < 0)
467        return ret;
468
469    ret = ad9523_read(indio_dev, AD9523_EEPROM_ERROR_READBACK);
470    if (ret < 0)
471        return ret;
472
473    if (ret & AD9523_EEPROM_ERROR_READBACK_FAIL) {
474        dev_err(&indio_dev->dev, "Verify EEPROM failed");
475        ret = -EIO;
476    }
477
478    return ret;
479}
480
481static int ad9523_sync(struct iio_dev *indio_dev)
482{
483    int ret, tmp;
484
485    ret = ad9523_read(indio_dev, AD9523_STATUS_SIGNALS);
486    if (ret < 0)
487        return ret;
488
489    tmp = ret;
490    tmp |= AD9523_STATUS_SIGNALS_SYNC_MAN_CTRL;
491
492    ret = ad9523_write(indio_dev, AD9523_STATUS_SIGNALS, tmp);
493    if (ret < 0)
494        return ret;
495
496    ad9523_io_update(indio_dev);
497    tmp &= ~AD9523_STATUS_SIGNALS_SYNC_MAN_CTRL;
498
499    ret = ad9523_write(indio_dev, AD9523_STATUS_SIGNALS, tmp);
500    if (ret < 0)
501        return ret;
502
503    return ad9523_io_update(indio_dev);
504}
505
506static ssize_t ad9523_store(struct device *dev,
507                struct device_attribute *attr,
508                const char *buf, size_t len)
509{
510    struct iio_dev *indio_dev = dev_to_iio_dev(dev);
511    struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
512    bool state;
513    int ret;
514
515    ret = strtobool(buf, &state);
516    if (ret < 0)
517        return ret;
518
519    if (!state)
520        return 0;
521
522    mutex_lock(&indio_dev->mlock);
523    switch ((u32)this_attr->address) {
524    case AD9523_SYNC:
525        ret = ad9523_sync(indio_dev);
526        break;
527    case AD9523_EEPROM:
528        ret = ad9523_store_eeprom(indio_dev);
529        break;
530    default:
531        ret = -ENODEV;
532    }
533    mutex_unlock(&indio_dev->mlock);
534
535    return ret ? ret : len;
536}
537
538static ssize_t ad9523_show(struct device *dev,
539            struct device_attribute *attr,
540            char *buf)
541{
542    struct iio_dev *indio_dev = dev_to_iio_dev(dev);
543    struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
544    int ret;
545
546    mutex_lock(&indio_dev->mlock);
547    ret = ad9523_read(indio_dev, AD9523_READBACK_0);
548    if (ret >= 0) {
549        ret = sprintf(buf, "%d\n", !!(ret & (1 <<
550            (u32)this_attr->address)));
551    }
552    mutex_unlock(&indio_dev->mlock);
553
554    return ret;
555}
556
557static IIO_DEVICE_ATTR(pll1_locked, S_IRUGO,
558            ad9523_show,
559            NULL,
560            AD9523_STAT_PLL1_LD);
561
562static IIO_DEVICE_ATTR(pll2_locked, S_IRUGO,
563            ad9523_show,
564            NULL,
565            AD9523_STAT_PLL2_LD);
566
567static IIO_DEVICE_ATTR(pll1_reference_clk_a_present, S_IRUGO,
568            ad9523_show,
569            NULL,
570            AD9523_STAT_REFA);
571
572static IIO_DEVICE_ATTR(pll1_reference_clk_b_present, S_IRUGO,
573            ad9523_show,
574            NULL,
575            AD9523_STAT_REFB);
576
577static IIO_DEVICE_ATTR(pll1_reference_clk_test_present, S_IRUGO,
578            ad9523_show,
579            NULL,
580            AD9523_STAT_REF_TEST);
581
582static IIO_DEVICE_ATTR(vcxo_clk_present, S_IRUGO,
583            ad9523_show,
584            NULL,
585            AD9523_STAT_VCXO);
586
587static IIO_DEVICE_ATTR(pll2_feedback_clk_present, S_IRUGO,
588            ad9523_show,
589            NULL,
590            AD9523_STAT_PLL2_FB_CLK);
591
592static IIO_DEVICE_ATTR(pll2_reference_clk_present, S_IRUGO,
593            ad9523_show,
594            NULL,
595            AD9523_STAT_PLL2_REF_CLK);
596
597static IIO_DEVICE_ATTR(sync_dividers, S_IWUSR,
598            NULL,
599            ad9523_store,
600            AD9523_SYNC);
601
602static IIO_DEVICE_ATTR(store_eeprom, S_IWUSR,
603            NULL,
604            ad9523_store,
605            AD9523_EEPROM);
606
607static struct attribute *ad9523_attributes[] = {
608    &iio_dev_attr_sync_dividers.dev_attr.attr,
609    &iio_dev_attr_store_eeprom.dev_attr.attr,
610    &iio_dev_attr_pll2_feedback_clk_present.dev_attr.attr,
611    &iio_dev_attr_pll2_reference_clk_present.dev_attr.attr,
612    &iio_dev_attr_pll1_reference_clk_a_present.dev_attr.attr,
613    &iio_dev_attr_pll1_reference_clk_b_present.dev_attr.attr,
614    &iio_dev_attr_pll1_reference_clk_test_present.dev_attr.attr,
615    &iio_dev_attr_vcxo_clk_present.dev_attr.attr,
616    &iio_dev_attr_pll1_locked.dev_attr.attr,
617    &iio_dev_attr_pll2_locked.dev_attr.attr,
618    NULL,
619};
620
621static const struct attribute_group ad9523_attribute_group = {
622    .attrs = ad9523_attributes,
623};
624
625static int ad9523_read_raw(struct iio_dev *indio_dev,
626               struct iio_chan_spec const *chan,
627               int *val,
628               int *val2,
629               long m)
630{
631    struct ad9523_state *st = iio_priv(indio_dev);
632    unsigned code;
633    int ret;
634
635    mutex_lock(&indio_dev->mlock);
636    ret = ad9523_read(indio_dev, AD9523_CHANNEL_CLOCK_DIST(chan->channel));
637    mutex_unlock(&indio_dev->mlock);
638
639    if (ret < 0)
640        return ret;
641
642    switch (m) {
643    case IIO_CHAN_INFO_RAW:
644        *val = !(ret & AD9523_CLK_DIST_PWR_DOWN_EN);
645        return IIO_VAL_INT;
646    case IIO_CHAN_INFO_FREQUENCY:
647        *val = st->vco_out_freq[st->vco_out_map[chan->channel]] /
648            AD9523_CLK_DIST_DIV_REV(ret);
649        return IIO_VAL_INT;
650    case IIO_CHAN_INFO_PHASE:
651        code = (AD9523_CLK_DIST_DIV_PHASE_REV(ret) * 3141592) /
652            AD9523_CLK_DIST_DIV_REV(ret);
653        *val = code / 1000000;
654        *val2 = (code % 1000000) * 10;
655        return IIO_VAL_INT_PLUS_MICRO;
656    default:
657        return -EINVAL;
658    }
659};
660
661static int ad9523_write_raw(struct iio_dev *indio_dev,
662                struct iio_chan_spec const *chan,
663                int val,
664                int val2,
665                long mask)
666{
667    struct ad9523_state *st = iio_priv(indio_dev);
668    unsigned reg;
669    int ret, tmp, code;
670
671    mutex_lock(&indio_dev->mlock);
672    ret = ad9523_read(indio_dev, AD9523_CHANNEL_CLOCK_DIST(chan->channel));
673    if (ret < 0)
674        goto out;
675
676    reg = ret;
677
678    switch (mask) {
679    case IIO_CHAN_INFO_RAW:
680        if (val)
681            reg &= ~AD9523_CLK_DIST_PWR_DOWN_EN;
682        else
683            reg |= AD9523_CLK_DIST_PWR_DOWN_EN;
684        break;
685    case IIO_CHAN_INFO_FREQUENCY:
686        if (val <= 0) {
687            ret = -EINVAL;
688            goto out;
689        }
690        ret = ad9523_set_clock_provider(indio_dev, chan->channel, val);
691        if (ret < 0)
692            goto out;
693        tmp = st->vco_out_freq[st->vco_out_map[chan->channel]] / val;
694        tmp = clamp(tmp, 1, 1024);
695        reg &= ~(0x3FF << 8);
696        reg |= AD9523_CLK_DIST_DIV(tmp);
697        break;
698    case IIO_CHAN_INFO_PHASE:
699        code = val * 1000000 + val2 % 1000000;
700        tmp = (code * AD9523_CLK_DIST_DIV_REV(ret)) / 3141592;
701        tmp = clamp(tmp, 0, 63);
702        reg &= ~AD9523_CLK_DIST_DIV_PHASE(~0);
703        reg |= AD9523_CLK_DIST_DIV_PHASE(tmp);
704        break;
705    default:
706        ret = -EINVAL;
707        goto out;
708    }
709
710    ret = ad9523_write(indio_dev, AD9523_CHANNEL_CLOCK_DIST(chan->channel),
711               reg);
712    if (ret < 0)
713        goto out;
714
715    ad9523_io_update(indio_dev);
716out:
717    mutex_unlock(&indio_dev->mlock);
718    return ret;
719}
720
721static int ad9523_reg_access(struct iio_dev *indio_dev,
722                  unsigned reg, unsigned writeval,
723                  unsigned *readval)
724{
725    int ret;
726
727    mutex_lock(&indio_dev->mlock);
728    if (readval == NULL) {
729        ret = ad9523_write(indio_dev, reg | AD9523_R1B, writeval);
730        ad9523_io_update(indio_dev);
731    } else {
732        ret = ad9523_read(indio_dev, reg | AD9523_R1B);
733        if (ret < 0)
734            goto out_unlock;
735        *readval = ret;
736        ret = 0;
737    }
738
739out_unlock:
740    mutex_unlock(&indio_dev->mlock);
741
742    return ret;
743}
744
745static const struct iio_info ad9523_info = {
746    .read_raw = &ad9523_read_raw,
747    .write_raw = &ad9523_write_raw,
748    .debugfs_reg_access = &ad9523_reg_access,
749    .attrs = &ad9523_attribute_group,
750    .driver_module = THIS_MODULE,
751};
752
753static int ad9523_setup(struct iio_dev *indio_dev)
754{
755    struct ad9523_state *st = iio_priv(indio_dev);
756    struct ad9523_platform_data *pdata = st->pdata;
757    struct ad9523_channel_spec *chan;
758    unsigned long active_mask = 0;
759    int ret, i;
760
761    ret = ad9523_write(indio_dev, AD9523_SERIAL_PORT_CONFIG,
762               AD9523_SER_CONF_SOFT_RESET |
763              (st->spi->mode & SPI_3WIRE ? 0 :
764              AD9523_SER_CONF_SDO_ACTIVE));
765    if (ret < 0)
766        return ret;
767
768    ret = ad9523_write(indio_dev, AD9523_READBACK_CTRL,
769              AD9523_READBACK_CTRL_READ_BUFFERED);
770    if (ret < 0)
771        return ret;
772
773    ret = ad9523_io_update(indio_dev);
774    if (ret < 0)
775        return ret;
776
777    /*
778     * PLL1 Setup
779     */
780    ret = ad9523_write(indio_dev, AD9523_PLL1_REF_A_DIVIDER,
781        pdata->refa_r_div);
782    if (ret < 0)
783        return ret;
784
785    ret = ad9523_write(indio_dev, AD9523_PLL1_REF_B_DIVIDER,
786        pdata->refb_r_div);
787    if (ret < 0)
788        return ret;
789
790    ret = ad9523_write(indio_dev, AD9523_PLL1_FEEDBACK_DIVIDER,
791        pdata->pll1_feedback_div);
792    if (ret < 0)
793        return ret;
794
795    ret = ad9523_write(indio_dev, AD9523_PLL1_CHARGE_PUMP_CTRL,
796        AD9523_PLL1_CHARGE_PUMP_CURRENT_nA(pdata->
797            pll1_charge_pump_current_nA) |
798        AD9523_PLL1_CHARGE_PUMP_MODE_NORMAL |
799        AD9523_PLL1_BACKLASH_PW_MIN);
800    if (ret < 0)
801        return ret;
802
803    ret = ad9523_write(indio_dev, AD9523_PLL1_INPUT_RECEIVERS_CTRL,
804        AD_IF(refa_diff_rcv_en, AD9523_PLL1_REFA_RCV_EN) |
805        AD_IF(refb_diff_rcv_en, AD9523_PLL1_REFB_RCV_EN) |
806        AD_IF(osc_in_diff_en, AD9523_PLL1_OSC_IN_DIFF_EN) |
807        AD_IF(osc_in_cmos_neg_inp_en,
808              AD9523_PLL1_OSC_IN_CMOS_NEG_INP_EN) |
809        AD_IF(refa_diff_rcv_en, AD9523_PLL1_REFA_DIFF_RCV_EN) |
810        AD_IF(refb_diff_rcv_en, AD9523_PLL1_REFB_DIFF_RCV_EN));
811    if (ret < 0)
812        return ret;
813
814    ret = ad9523_write(indio_dev, AD9523_PLL1_REF_CTRL,
815        AD_IF(zd_in_diff_en, AD9523_PLL1_ZD_IN_DIFF_EN) |
816        AD_IF(zd_in_cmos_neg_inp_en,
817              AD9523_PLL1_ZD_IN_CMOS_NEG_INP_EN) |
818        AD_IF(zero_delay_mode_internal_en,
819              AD9523_PLL1_ZERO_DELAY_MODE_INT) |
820        AD_IF(osc_in_feedback_en, AD9523_PLL1_OSC_IN_PLL_FEEDBACK_EN) |
821        AD_IF(refa_cmos_neg_inp_en, AD9523_PLL1_REFA_CMOS_NEG_INP_EN) |
822        AD_IF(refb_cmos_neg_inp_en, AD9523_PLL1_REFB_CMOS_NEG_INP_EN));
823    if (ret < 0)
824        return ret;
825
826    ret = ad9523_write(indio_dev, AD9523_PLL1_MISC_CTRL,
827        AD9523_PLL1_REFB_INDEP_DIV_CTRL_EN |
828        AD9523_PLL1_REF_MODE(pdata->ref_mode));
829    if (ret < 0)
830        return ret;
831
832    ret = ad9523_write(indio_dev, AD9523_PLL1_LOOP_FILTER_CTRL,
833        AD9523_PLL1_LOOP_FILTER_RZERO(pdata->pll1_loop_filter_rzero));
834    if (ret < 0)
835        return ret;
836    /*
837     * PLL2 Setup
838     */
839
840    ret = ad9523_write(indio_dev, AD9523_PLL2_CHARGE_PUMP,
841        AD9523_PLL2_CHARGE_PUMP_CURRENT_nA(pdata->
842            pll2_charge_pump_current_nA));
843    if (ret < 0)
844        return ret;
845
846    ret = ad9523_write(indio_dev, AD9523_PLL2_FEEDBACK_DIVIDER_AB,
847        AD9523_PLL2_FB_NDIV_A_CNT(pdata->pll2_ndiv_a_cnt) |
848        AD9523_PLL2_FB_NDIV_B_CNT(pdata->pll2_ndiv_b_cnt));
849    if (ret < 0)
850        return ret;
851
852    ret = ad9523_write(indio_dev, AD9523_PLL2_CTRL,
853        AD9523_PLL2_CHARGE_PUMP_MODE_NORMAL |
854        AD9523_PLL2_BACKLASH_CTRL_EN |
855        AD_IF(pll2_freq_doubler_en, AD9523_PLL2_FREQ_DOUBLER_EN));
856    if (ret < 0)
857        return ret;
858
859    st->vco_freq = (pdata->vcxo_freq * (pdata->pll2_freq_doubler_en ? 2 : 1)
860            / pdata->pll2_r2_div) * AD9523_PLL2_FB_NDIV(pdata->
861            pll2_ndiv_a_cnt, pdata->pll2_ndiv_b_cnt);
862
863    ret = ad9523_write(indio_dev, AD9523_PLL2_VCO_CTRL,
864        AD9523_PLL2_VCO_CALIBRATE);
865    if (ret < 0)
866        return ret;
867
868    ret = ad9523_write(indio_dev, AD9523_PLL2_VCO_DIVIDER,
869        AD9523_PLL2_VCO_DIV_M1(pdata->pll2_vco_diff_m1) |
870        AD9523_PLL2_VCO_DIV_M2(pdata->pll2_vco_diff_m2) |
871        AD_IFE(pll2_vco_diff_m1, 0,
872               AD9523_PLL2_VCO_DIV_M1_PWR_DOWN_EN) |
873        AD_IFE(pll2_vco_diff_m2, 0,
874               AD9523_PLL2_VCO_DIV_M2_PWR_DOWN_EN));
875    if (ret < 0)
876        return ret;
877
878    if (pdata->pll2_vco_diff_m1)
879        st->vco_out_freq[AD9523_VCO1] =
880            st->vco_freq / pdata->pll2_vco_diff_m1;
881
882    if (pdata->pll2_vco_diff_m2)
883        st->vco_out_freq[AD9523_VCO2] =
884            st->vco_freq / pdata->pll2_vco_diff_m2;
885
886    st->vco_out_freq[AD9523_VCXO] = pdata->vcxo_freq;
887
888    ret = ad9523_write(indio_dev, AD9523_PLL2_R2_DIVIDER,
889        AD9523_PLL2_R2_DIVIDER_VAL(pdata->pll2_r2_div));
890    if (ret < 0)
891        return ret;
892
893    ret = ad9523_write(indio_dev, AD9523_PLL2_LOOP_FILTER_CTRL,
894        AD9523_PLL2_LOOP_FILTER_CPOLE1(pdata->cpole1) |
895        AD9523_PLL2_LOOP_FILTER_RZERO(pdata->rzero) |
896        AD9523_PLL2_LOOP_FILTER_RPOLE2(pdata->rpole2) |
897        AD_IF(rzero_bypass_en,
898              AD9523_PLL2_LOOP_FILTER_RZERO_BYPASS_EN));
899    if (ret < 0)
900        return ret;
901
902    for (i = 0; i < pdata->num_channels; i++) {
903        chan = &pdata->channels[i];
904        if (chan->channel_num < AD9523_NUM_CHAN) {
905            __set_bit(chan->channel_num, &active_mask);
906            ret = ad9523_write(indio_dev,
907                AD9523_CHANNEL_CLOCK_DIST(chan->channel_num),
908                AD9523_CLK_DIST_DRIVER_MODE(chan->driver_mode) |
909                AD9523_CLK_DIST_DIV(chan->channel_divider) |
910                AD9523_CLK_DIST_DIV_PHASE(chan->divider_phase) |
911                (chan->sync_ignore_en ?
912                    AD9523_CLK_DIST_IGNORE_SYNC_EN : 0) |
913                (chan->divider_output_invert_en ?
914                    AD9523_CLK_DIST_INV_DIV_OUTPUT_EN : 0) |
915                (chan->low_power_mode_en ?
916                    AD9523_CLK_DIST_LOW_PWR_MODE_EN : 0) |
917                (chan->output_dis ?
918                    AD9523_CLK_DIST_PWR_DOWN_EN : 0));
919            if (ret < 0)
920                return ret;
921
922            ret = ad9523_vco_out_map(indio_dev, chan->channel_num,
923                       chan->use_alt_clock_src);
924            if (ret < 0)
925                return ret;
926
927            st->ad9523_channels[i].type = IIO_ALTVOLTAGE;
928            st->ad9523_channels[i].output = 1;
929            st->ad9523_channels[i].indexed = 1;
930            st->ad9523_channels[i].channel = chan->channel_num;
931            st->ad9523_channels[i].extend_name =
932                chan->extended_name;
933            st->ad9523_channels[i].info_mask =
934                IIO_CHAN_INFO_RAW_SEPARATE_BIT |
935                IIO_CHAN_INFO_PHASE_SEPARATE_BIT |
936                IIO_CHAN_INFO_FREQUENCY_SEPARATE_BIT;
937        }
938    }
939
940    for_each_clear_bit(i, &active_mask, AD9523_NUM_CHAN)
941        ad9523_write(indio_dev,
942                 AD9523_CHANNEL_CLOCK_DIST(i),
943                 AD9523_CLK_DIST_DRIVER_MODE(TRISTATE) |
944                 AD9523_CLK_DIST_PWR_DOWN_EN);
945
946    ret = ad9523_write(indio_dev, AD9523_POWER_DOWN_CTRL, 0);
947    if (ret < 0)
948        return ret;
949
950    ret = ad9523_write(indio_dev, AD9523_STATUS_SIGNALS,
951               AD9523_STATUS_MONITOR_01_PLL12_LOCKED);
952    if (ret < 0)
953        return ret;
954
955    ret = ad9523_io_update(indio_dev);
956    if (ret < 0)
957        return ret;
958
959    return 0;
960}
961
962static int __devinit ad9523_probe(struct spi_device *spi)
963{
964    struct ad9523_platform_data *pdata = spi->dev.platform_data;
965    struct iio_dev *indio_dev;
966    struct ad9523_state *st;
967    int ret;
968
969    if (!pdata) {
970        dev_err(&spi->dev, "no platform data?\n");
971        return -EINVAL;
972    }
973
974    indio_dev = iio_device_alloc(sizeof(*st));
975    if (indio_dev == NULL)
976        return -ENOMEM;
977
978    st = iio_priv(indio_dev);
979
980    st->reg = regulator_get(&spi->dev, "vcc");
981    if (!IS_ERR(st->reg)) {
982        ret = regulator_enable(st->reg);
983        if (ret)
984            goto error_put_reg;
985    }
986
987    spi_set_drvdata(spi, indio_dev);
988    st->spi = spi;
989    st->pdata = pdata;
990
991    indio_dev->dev.parent = &spi->dev;
992    indio_dev->name = (pdata->name[0] != 0) ? pdata->name :
993              spi_get_device_id(spi)->name;
994    indio_dev->info = &ad9523_info;
995    indio_dev->modes = INDIO_DIRECT_MODE;
996    indio_dev->channels = st->ad9523_channels;
997    indio_dev->num_channels = pdata->num_channels;
998
999    ret = ad9523_setup(indio_dev);
1000    if (ret < 0)
1001        goto error_disable_reg;
1002
1003    ret = iio_device_register(indio_dev);
1004    if (ret)
1005        goto error_disable_reg;
1006
1007    dev_info(&spi->dev, "probed %s\n", indio_dev->name);
1008
1009    return 0;
1010
1011error_disable_reg:
1012    if (!IS_ERR(st->reg))
1013        regulator_disable(st->reg);
1014error_put_reg:
1015    if (!IS_ERR(st->reg))
1016        regulator_put(st->reg);
1017
1018    iio_device_free(indio_dev);
1019
1020    return ret;
1021}
1022
1023static int __devexit ad9523_remove(struct spi_device *spi)
1024{
1025    struct iio_dev *indio_dev = spi_get_drvdata(spi);
1026    struct ad9523_state *st = iio_priv(indio_dev);
1027
1028    iio_device_unregister(indio_dev);
1029
1030    if (!IS_ERR(st->reg)) {
1031        regulator_disable(st->reg);
1032        regulator_put(st->reg);
1033    }
1034
1035    iio_device_free(indio_dev);
1036
1037    return 0;
1038}
1039
1040static const struct spi_device_id ad9523_id[] = {
1041    {"ad9523-1", 9523},
1042    {}
1043};
1044MODULE_DEVICE_TABLE(spi, ad9523_id);
1045
1046static struct spi_driver ad9523_driver = {
1047    .driver = {
1048        .name = "ad9523",
1049        .owner = THIS_MODULE,
1050    },
1051    .probe = ad9523_probe,
1052    .remove = __devexit_p(ad9523_remove),
1053    .id_table = ad9523_id,
1054};
1055module_spi_driver(ad9523_driver);
1056
1057MODULE_AUTHOR("Michael Hennerich <hennerich@blackfin.uclinux.org>");
1058MODULE_DESCRIPTION("Analog Devices AD9523 CLOCKDIST/PLL");
1059MODULE_LICENSE("GPL v2");
1060

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