Root/drivers/memory/tegra20-mc.c

1/*
2 * Tegra20 Memory Controller
3 *
4 * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along with
16 * this program; if not, write to the Free Software Foundation, Inc.,
17 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18 */
19
20#include <linux/kernel.h>
21#include <linux/module.h>
22#include <linux/ratelimit.h>
23#include <linux/platform_device.h>
24#include <linux/interrupt.h>
25#include <linux/io.h>
26
27#define DRV_NAME "tegra20-mc"
28
29#define MC_INTSTATUS 0x0
30#define MC_INTMASK 0x4
31
32#define MC_INT_ERR_SHIFT 6
33#define MC_INT_ERR_MASK (0x1f << MC_INT_ERR_SHIFT)
34#define MC_INT_DECERR_EMEM BIT(MC_INT_ERR_SHIFT)
35#define MC_INT_INVALID_GART_PAGE BIT(MC_INT_ERR_SHIFT + 1)
36#define MC_INT_SECURITY_VIOLATION BIT(MC_INT_ERR_SHIFT + 2)
37#define MC_INT_ARBITRATION_EMEM BIT(MC_INT_ERR_SHIFT + 3)
38
39#define MC_GART_ERROR_REQ 0x30
40#define MC_DECERR_EMEM_OTHERS_STATUS 0x58
41#define MC_SECURITY_VIOLATION_STATUS 0x74
42
43#define SECURITY_VIOLATION_TYPE BIT(30) /* 0=TRUSTZONE, 1=CARVEOUT */
44
45#define MC_CLIENT_ID_MASK 0x3f
46
47#define NUM_MC_REG_BANKS 2
48
49struct tegra20_mc {
50    void __iomem *regs[NUM_MC_REG_BANKS];
51    struct device *dev;
52};
53
54static inline u32 mc_readl(struct tegra20_mc *mc, u32 offs)
55{
56    u32 val = 0;
57
58    if (offs < 0x24)
59        val = readl(mc->regs[0] + offs);
60    if (offs < 0x400)
61        val = readl(mc->regs[1] + offs - 0x3c);
62
63    return val;
64}
65
66static inline void mc_writel(struct tegra20_mc *mc, u32 val, u32 offs)
67{
68    if (offs < 0x24) {
69        writel(val, mc->regs[0] + offs);
70        return;
71    }
72    if (offs < 0x400) {
73        writel(val, mc->regs[1] + offs - 0x3c);
74        return;
75    }
76}
77
78static const char * const tegra20_mc_client[] = {
79    "cbr_display0a",
80    "cbr_display0ab",
81    "cbr_display0b",
82    "cbr_display0bb",
83    "cbr_display0c",
84    "cbr_display0cb",
85    "cbr_display1b",
86    "cbr_display1bb",
87    "cbr_eppup",
88    "cbr_g2pr",
89    "cbr_g2sr",
90    "cbr_mpeunifbr",
91    "cbr_viruv",
92    "csr_avpcarm7r",
93    "csr_displayhc",
94    "csr_displayhcb",
95    "csr_fdcdrd",
96    "csr_g2dr",
97    "csr_host1xdmar",
98    "csr_host1xr",
99    "csr_idxsrd",
100    "csr_mpcorer",
101    "csr_mpe_ipred",
102    "csr_mpeamemrd",
103    "csr_mpecsrd",
104    "csr_ppcsahbdmar",
105    "csr_ppcsahbslvr",
106    "csr_texsrd",
107    "csr_vdebsevr",
108    "csr_vdember",
109    "csr_vdemcer",
110    "csr_vdetper",
111    "cbw_eppu",
112    "cbw_eppv",
113    "cbw_eppy",
114    "cbw_mpeunifbw",
115    "cbw_viwsb",
116    "cbw_viwu",
117    "cbw_viwv",
118    "cbw_viwy",
119    "ccw_g2dw",
120    "csw_avpcarm7w",
121    "csw_fdcdwr",
122    "csw_host1xw",
123    "csw_ispw",
124    "csw_mpcorew",
125    "csw_mpecswr",
126    "csw_ppcsahbdmaw",
127    "csw_ppcsahbslvw",
128    "csw_vdebsevw",
129    "csw_vdembew",
130    "csw_vdetpmw",
131};
132
133static void tegra20_mc_decode(struct tegra20_mc *mc, int n)
134{
135    u32 addr, req;
136    const char *client = "Unknown";
137    int idx, cid;
138    const struct reg_info {
139        u32 offset;
140        u32 write_bit; /* 0=READ, 1=WRITE */
141        int cid_shift;
142        char *message;
143    } reg[] = {
144        {
145            .offset = MC_DECERR_EMEM_OTHERS_STATUS,
146            .write_bit = 31,
147            .message = "MC_DECERR",
148        },
149        {
150            .offset = MC_GART_ERROR_REQ,
151            .cid_shift = 1,
152            .message = "MC_GART_ERR",
153
154        },
155        {
156            .offset = MC_SECURITY_VIOLATION_STATUS,
157            .write_bit = 31,
158            .message = "MC_SECURITY_ERR",
159        },
160    };
161
162    idx = n - MC_INT_ERR_SHIFT;
163    if ((idx < 0) || (idx >= ARRAY_SIZE(reg))) {
164        dev_err_ratelimited(mc->dev, "Unknown interrupt status %08lx\n",
165                    BIT(n));
166        return;
167    }
168
169    req = mc_readl(mc, reg[idx].offset);
170    cid = (req >> reg[idx].cid_shift) & MC_CLIENT_ID_MASK;
171    if (cid < ARRAY_SIZE(tegra20_mc_client))
172        client = tegra20_mc_client[cid];
173
174    addr = mc_readl(mc, reg[idx].offset + sizeof(u32));
175
176    dev_err_ratelimited(mc->dev, "%s (0x%08x): 0x%08x %s (%s %s)\n",
177               reg[idx].message, req, addr, client,
178               (req & BIT(reg[idx].write_bit)) ? "write" : "read",
179               (reg[idx].offset == MC_SECURITY_VIOLATION_STATUS) ?
180               ((req & SECURITY_VIOLATION_TYPE) ?
181                "carveout" : "trustzone") : "");
182}
183
184static const struct of_device_id tegra20_mc_of_match[] __devinitconst = {
185    { .compatible = "nvidia,tegra20-mc", },
186    {},
187};
188
189static irqreturn_t tegra20_mc_isr(int irq, void *data)
190{
191    u32 stat, mask, bit;
192    struct tegra20_mc *mc = data;
193
194    stat = mc_readl(mc, MC_INTSTATUS);
195    mask = mc_readl(mc, MC_INTMASK);
196    mask &= stat;
197    if (!mask)
198        return IRQ_NONE;
199    while ((bit = ffs(mask)) != 0)
200        tegra20_mc_decode(mc, bit - 1);
201    mc_writel(mc, stat, MC_INTSTATUS);
202    return IRQ_HANDLED;
203}
204
205static int __devinit tegra20_mc_probe(struct platform_device *pdev)
206{
207    struct resource *irq;
208    struct tegra20_mc *mc;
209    int i, err;
210    u32 intmask;
211
212    mc = devm_kzalloc(&pdev->dev, sizeof(*mc), GFP_KERNEL);
213    if (!mc)
214        return -ENOMEM;
215    mc->dev = &pdev->dev;
216
217    for (i = 0; i < ARRAY_SIZE(mc->regs); i++) {
218        struct resource *res;
219
220        res = platform_get_resource(pdev, IORESOURCE_MEM, i);
221        if (!res)
222            return -ENODEV;
223        mc->regs[i] = devm_request_and_ioremap(&pdev->dev, res);
224        if (!mc->regs[i])
225            return -EBUSY;
226    }
227
228    irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
229    if (!irq)
230        return -ENODEV;
231    err = devm_request_irq(&pdev->dev, irq->start, tegra20_mc_isr,
232                   IRQF_SHARED, dev_name(&pdev->dev), mc);
233    if (err)
234        return -ENODEV;
235
236    platform_set_drvdata(pdev, mc);
237
238    intmask = MC_INT_INVALID_GART_PAGE |
239        MC_INT_DECERR_EMEM | MC_INT_SECURITY_VIOLATION;
240    mc_writel(mc, intmask, MC_INTMASK);
241    return 0;
242}
243
244static struct platform_driver tegra20_mc_driver = {
245    .probe = tegra20_mc_probe,
246    .driver = {
247        .name = DRV_NAME,
248        .owner = THIS_MODULE,
249        .of_match_table = tegra20_mc_of_match,
250    },
251};
252module_platform_driver(tegra20_mc_driver);
253
254MODULE_AUTHOR("Hiroshi DOYU <hdoyu@nvidia.com>");
255MODULE_DESCRIPTION("Tegra20 MC driver");
256MODULE_LICENSE("GPL v2");
257MODULE_ALIAS("platform:" DRV_NAME);
258

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