Kernel

Kernel Git Source Tree

Root/drivers/parisc/dino.c

1	/*
2	** DINO manager
3	**
4	** (c) Copyright 1999 Red Hat Software
5	** (c) Copyright 1999 SuSE GmbH
6	** (c) Copyright 1999,2000 Hewlett-Packard Company
7	** (c) Copyright 2000 Grant Grundler
8	** (c) Copyright 2006 Helge Deller
9	**
10	** This program is free software; you can redistribute it and/or modify
11	** it under the terms of the GNU General Public License as published by
12	** the Free Software Foundation; either version 2 of the License, or
13	** (at your option) any later version.
14	**
15	** This module provides access to Dino PCI bus (config/IOport spaces)
16	** and helps manage Dino IRQ lines.
17	**
18	** Dino interrupt handling is a bit complicated.
19	** Dino always writes to the broadcast EIR via irr0 for now.
20	** (BIG WARNING: using broadcast EIR is a really bad thing for SMP!)
21	** Only one processor interrupt is used for the 11 IRQ line
22	** inputs to dino.
23	**
24	** The different between Built-in Dino and Card-Mode
25	** dino is in chip initialization and pci device initialization.
26	**
27	** Linux drivers can only use Card-Mode Dino if pci devices I/O port
28	** BARs are configured and used by the driver. Programming MMIO address
29	** requires substantial knowledge of available Host I/O address ranges
30	** is currently not supported. Port/Config accessor functions are the
31	** same. "BIOS" differences are handled within the existing routines.
32	*/
33
34	/* Changes :
35	** 2001-06-14 : Clement Moyroud (moyroudc@esiee.fr)
36	** - added support for the integrated RS232.
37	*/
38
39	/*
40	** TODO: create a virtual address for each Dino HPA.
41	** GSC code might be able to do this since IODC data tells us
42	** how many pages are used. PCI subsystem could (must?) do this
43	** for PCI drivers devices which implement/use MMIO registers.
44	*/
45
46	#include <linux/delay.h>
47	#include <linux/types.h>
48	#include <linux/kernel.h>
49	#include <linux/pci.h>
50	#include <linux/init.h>
51	#include <linux/ioport.h>
52	#include <linux/slab.h>
53	#include <linux/interrupt.h> /* for struct irqaction */
54	#include <linux/spinlock.h> /* for spinlock_t and prototypes */
55
56	#include <asm/pdc.h>
57	#include <asm/page.h>
58	#include <asm/io.h>
59	#include <asm/hardware.h>
60
61	#include "gsc.h"
62
63	#undef DINO_DEBUG
64
65	#ifdef DINO_DEBUG
66	#define DBG(x...) printk(x)
67	#else
68	#define DBG(x...)
69	#endif
70
71	/*
72	** Config accessor functions only pass in the 8-bit bus number
73	** and not the 8-bit "PCI Segment" number. Each Dino will be
74	** assigned a PCI bus number based on "when" it's discovered.
75	**
76	** The "secondary" bus number is set to this before calling
77	** pci_scan_bus(). If any PPB's are present, the scan will
78	** discover them and update the "secondary" and "subordinate"
79	** fields in Dino's pci_bus structure.
80	**
81	** Changes in the configuration will result in a different
82	** bus number for each dino.
83	*/
84
85	#define is_card_dino(id) ((id)->hw_type == HPHW_A_DMA)
86	#define is_cujo(id) ((id)->hversion == 0x682)
87
88	#define DINO_IAR0 0x004
89	#define DINO_IODC_ADDR 0x008
90	#define DINO_IODC_DATA_0 0x008
91	#define DINO_IODC_DATA_1 0x008
92	#define DINO_IRR0 0x00C
93	#define DINO_IAR1 0x010
94	#define DINO_IRR1 0x014
95	#define DINO_IMR 0x018
96	#define DINO_IPR 0x01C
97	#define DINO_TOC_ADDR 0x020
98	#define DINO_ICR 0x024
99	#define DINO_ILR 0x028
100	#define DINO_IO_COMMAND 0x030
101	#define DINO_IO_STATUS 0x034
102	#define DINO_IO_CONTROL 0x038
103	#define DINO_IO_GSC_ERR_RESP 0x040
104	#define DINO_IO_ERR_INFO 0x044
105	#define DINO_IO_PCI_ERR_RESP 0x048
106	#define DINO_IO_FBB_EN 0x05c
107	#define DINO_IO_ADDR_EN 0x060
108	#define DINO_PCI_ADDR 0x064
109	#define DINO_CONFIG_DATA 0x068
110	#define DINO_IO_DATA 0x06c
111	#define DINO_MEM_DATA 0x070 /* Dino 3.x only */
112	#define DINO_GSC2X_CONFIG 0x7b4
113	#define DINO_GMASK 0x800
114	#define DINO_PAMR 0x804
115	#define DINO_PAPR 0x808
116	#define DINO_DAMODE 0x80c
117	#define DINO_PCICMD 0x810
118	#define DINO_PCISTS 0x814
119	#define DINO_MLTIM 0x81c
120	#define DINO_BRDG_FEAT 0x820
121	#define DINO_PCIROR 0x824
122	#define DINO_PCIWOR 0x828
123	#define DINO_TLTIM 0x830
124
125	#define DINO_IRQS 11 /* bits 0-10 are architected */
126	#define DINO_IRR_MASK 0x5ff /* only 10 bits are implemented */
127	#define DINO_LOCAL_IRQS (DINO_IRQS+1)
128
129	#define DINO_MASK_IRQ(x) (1<<(x))
130
131	#define PCIINTA 0x001
132	#define PCIINTB 0x002
133	#define PCIINTC 0x004
134	#define PCIINTD 0x008
135	#define PCIINTE 0x010
136	#define PCIINTF 0x020
137	#define GSCEXTINT 0x040
138	/* #define xxx 0x080 - bit 7 is "default" */
139	/* #define xxx 0x100 - bit 8 not used */
140	/* #define xxx 0x200 - bit 9 not used */
141	#define RS232INT 0x400
142
143	struct dino_device
144	{
145	struct pci_hba_data hba; /* 'C' inheritance - must be first */
146	spinlock_t dinosaur_pen;
147	unsigned long txn_addr; /* EIR addr to generate interrupt */
148	u32 txn_data; /* EIR data assign to each dino */
149	u32 imr; /* IRQ's which are enabled */
150	int global_irq[DINO_LOCAL_IRQS]; /* map IMR bit to global irq */
151	#ifdef DINO_DEBUG
152	unsigned int dino_irr0; /* save most recent IRQ line stat */
153	#endif
154	};
155
156	/* Looks nice and keeps the compiler happy */
157	#define DINO_DEV(d) ((struct dino_device *) d)
158
159
160	/*
161	* Dino Configuration Space Accessor Functions
162	*/
163
164	#define DINO_CFG_TOK(bus,dfn,pos) ((u32) ((bus)<<16 \| (dfn)<<8 \| (pos)))
165
166	/*
167	* keep the current highest bus count to assist in allocating busses. This
168	* tries to keep a global bus count total so that when we discover an
169	* entirely new bus, it can be given a unique bus number.
170	*/
171	static int dino_current_bus = 0;
172
173	static int dino_cfg_read(struct pci_bus *bus, unsigned int devfn, int where,
174	int size, u32 *val)
175	{
176	struct dino_device *d = DINO_DEV(parisc_walk_tree(bus->bridge));
177	u32 local_bus = (bus->parent == NULL) ? 0 : bus->busn_res.start;
178	u32 v = DINO_CFG_TOK(local_bus, devfn, where & ~3);
179	void __iomem *base_addr = d->hba.base_addr;
180	unsigned long flags;
181
182	DBG("%s: %p, %d, %d, %d\n", __func__, base_addr, devfn, where,
183	size);
184	spin_lock_irqsave(&d->dinosaur_pen, flags);
185
186	/* tell HW which CFG address */
187	__raw_writel(v, base_addr + DINO_PCI_ADDR);
188
189	/* generate cfg read cycle */
190	if (size == 1) {
191	*val = readb(base_addr + DINO_CONFIG_DATA + (where & 3));
192	} else if (size == 2) {
193	*val = readw(base_addr + DINO_CONFIG_DATA + (where & 2));
194	} else if (size == 4) {
195	*val = readl(base_addr + DINO_CONFIG_DATA);
196	}
197
198	spin_unlock_irqrestore(&d->dinosaur_pen, flags);
199	return 0;
200	}
201
202	/*
203	* Dino address stepping "feature":
204	* When address stepping, Dino attempts to drive the bus one cycle too soon
205	* even though the type of cycle (config vs. MMIO) might be different.
206	* The read of Ven/Prod ID is harmless and avoids Dino's address stepping.
207	*/
208	static int dino_cfg_write(struct pci_bus *bus, unsigned int devfn, int where,
209	int size, u32 val)
210	{
211	struct dino_device *d = DINO_DEV(parisc_walk_tree(bus->bridge));
212	u32 local_bus = (bus->parent == NULL) ? 0 : bus->busn_res.start;
213	u32 v = DINO_CFG_TOK(local_bus, devfn, where & ~3);
214	void __iomem *base_addr = d->hba.base_addr;
215	unsigned long flags;
216
217	DBG("%s: %p, %d, %d, %d\n", __func__, base_addr, devfn, where,
218	size);
219	spin_lock_irqsave(&d->dinosaur_pen, flags);
220
221	/* avoid address stepping feature */
222	__raw_writel(v & 0xffffff00, base_addr + DINO_PCI_ADDR);
223	__raw_readl(base_addr + DINO_CONFIG_DATA);
224
225	/* tell HW which CFG address */
226	__raw_writel(v, base_addr + DINO_PCI_ADDR);
227	/* generate cfg read cycle */
228	if (size == 1) {
229	writeb(val, base_addr + DINO_CONFIG_DATA + (where & 3));
230	} else if (size == 2) {
231	writew(val, base_addr + DINO_CONFIG_DATA + (where & 2));
232	} else if (size == 4) {
233	writel(val, base_addr + DINO_CONFIG_DATA);
234	}
235
236	spin_unlock_irqrestore(&d->dinosaur_pen, flags);
237	return 0;
238	}
239
240	static struct pci_ops dino_cfg_ops = {
241	.read = dino_cfg_read,
242	.write = dino_cfg_write,
243	};
244
245
246	/*
247	* Dino "I/O Port" Space Accessor Functions
248	*
249	* Many PCI devices don't require use of I/O port space (eg Tulip,
250	* NCR720) since they export the same registers to both MMIO and
251	* I/O port space. Performance is going to stink if drivers use
252	* I/O port instead of MMIO.
253	*/
254
255	#define DINO_PORT_IN(type, size, mask) \
256	static u##size dino_in##size (struct pci_hba_data *d, u16 addr) \
257	{ \
258	u##size v; \
259	unsigned long flags; \
260	spin_lock_irqsave(&(DINO_DEV(d)->dinosaur_pen), flags); \
261	/* tell HW which IO Port address */ \
262	__raw_writel((u32) addr, d->base_addr + DINO_PCI_ADDR); \
263	/* generate I/O PORT read cycle */ \
264	v = read##type(d->base_addr+DINO_IO_DATA+(addr&mask)); \
265	spin_unlock_irqrestore(&(DINO_DEV(d)->dinosaur_pen), flags); \
266	return v; \
267	}
268
269	DINO_PORT_IN(b, 8, 3)
270	DINO_PORT_IN(w, 16, 2)
271	DINO_PORT_IN(l, 32, 0)
272
273	#define DINO_PORT_OUT(type, size, mask) \
274	static void dino_out##size (struct pci_hba_data *d, u16 addr, u##size val) \
275	{ \
276	unsigned long flags; \
277	spin_lock_irqsave(&(DINO_DEV(d)->dinosaur_pen), flags); \
278	/* tell HW which IO port address */ \
279	__raw_writel((u32) addr, d->base_addr + DINO_PCI_ADDR); \
280	/* generate cfg write cycle */ \
281	write##type(val, d->base_addr+DINO_IO_DATA+(addr&mask)); \
282	spin_unlock_irqrestore(&(DINO_DEV(d)->dinosaur_pen), flags); \
283	}
284
285	DINO_PORT_OUT(b, 8, 3)
286	DINO_PORT_OUT(w, 16, 2)
287	DINO_PORT_OUT(l, 32, 0)
288
289	static struct pci_port_ops dino_port_ops = {
290	.inb = dino_in8,
291	.inw = dino_in16,
292	.inl = dino_in32,
293	.outb = dino_out8,
294	.outw = dino_out16,
295	.outl = dino_out32
296	};
297
298	static void dino_mask_irq(struct irq_data *d)
299	{
300	struct dino_device *dino_dev = irq_data_get_irq_chip_data(d);
301	int local_irq = gsc_find_local_irq(d->irq, dino_dev->global_irq, DINO_LOCAL_IRQS);
302
303	DBG(KERN_WARNING "%s(0x%p, %d)\n", __func__, dino_dev, d->irq);
304
305	/* Clear the matching bit in the IMR register */
306	dino_dev->imr &= ~(DINO_MASK_IRQ(local_irq));
307	__raw_writel(dino_dev->imr, dino_dev->hba.base_addr+DINO_IMR);
308	}
309
310	static void dino_unmask_irq(struct irq_data *d)
311	{
312	struct dino_device *dino_dev = irq_data_get_irq_chip_data(d);
313	int local_irq = gsc_find_local_irq(d->irq, dino_dev->global_irq, DINO_LOCAL_IRQS);
314	u32 tmp;
315
316	DBG(KERN_WARNING "%s(0x%p, %d)\n", __func__, dino_dev, d->irq);
317
318	/*
319	** clear pending IRQ bits
320	**
321	** This does NOT change ILR state!
322	** See comment below for ILR usage.
323	*/
324	__raw_readl(dino_dev->hba.base_addr+DINO_IPR);
325
326	/* set the matching bit in the IMR register */
327	dino_dev->imr \|= DINO_MASK_IRQ(local_irq); /* used in dino_isr() */
328	__raw_writel( dino_dev->imr, dino_dev->hba.base_addr+DINO_IMR);
329
330	/* Emulate "Level Triggered" Interrupt
331	** Basically, a driver is blowing it if the IRQ line is asserted
332	** while the IRQ is disabled. But tulip.c seems to do that....
333	** Give 'em a kluge award and a nice round of applause!
334	**
335	** The gsc_write will generate an interrupt which invokes dino_isr().
336	** dino_isr() will read IPR and find nothing. But then catch this
337	** when it also checks ILR.
338	*/
339	tmp = __raw_readl(dino_dev->hba.base_addr+DINO_ILR);
340	if (tmp & DINO_MASK_IRQ(local_irq)) {
341	DBG(KERN_WARNING "%s(): IRQ asserted! (ILR 0x%x)\n",
342	__func__, tmp);
343	gsc_writel(dino_dev->txn_data, dino_dev->txn_addr);
344	}
345	}
346
347	static struct irq_chip dino_interrupt_type = {
348	.name = "GSC-PCI",
349	.irq_unmask = dino_unmask_irq,
350	.irq_mask = dino_mask_irq,
351	};
352
353
354	/*
355	* Handle a Processor interrupt generated by Dino.
356	*
357	* ilr_loop counter is a kluge to prevent a "stuck" IRQ line from
358	* wedging the CPU. Could be removed or made optional at some point.
359	*/
360	static irqreturn_t dino_isr(int irq, void *intr_dev)
361	{
362	struct dino_device *dino_dev = intr_dev;
363	u32 mask;
364	int ilr_loop = 100;
365
366	/* read and acknowledge pending interrupts */
367	#ifdef DINO_DEBUG
368	dino_dev->dino_irr0 =
369	#endif
370	mask = __raw_readl(dino_dev->hba.base_addr+DINO_IRR0) & DINO_IRR_MASK;
371
372	if (mask == 0)
373	return IRQ_NONE;
374
375	ilr_again:
376	do {
377	int local_irq = __ffs(mask);
378	int irq = dino_dev->global_irq[local_irq];
379	DBG(KERN_DEBUG "%s(%d, %p) mask 0x%x\n",
380	__func__, irq, intr_dev, mask);
381	generic_handle_irq(irq);
382	mask &= ~(1 << local_irq);
383	} while (mask);
384
385	/* Support for level triggered IRQ lines.
386	**
387	** Dropping this support would make this routine much faster.
388	** But since PCI requires level triggered IRQ line to share lines...
389	** device drivers may assume lines are level triggered (and not
390	** edge triggered like EISA/ISA can be).
391	*/
392	mask = __raw_readl(dino_dev->hba.base_addr+DINO_ILR) & dino_dev->imr;
393	if (mask) {
394	if (--ilr_loop > 0)
395	goto ilr_again;
396	printk(KERN_ERR "Dino 0x%p: stuck interrupt %d\n",
397	dino_dev->hba.base_addr, mask);
398	return IRQ_NONE;
399	}
400	return IRQ_HANDLED;
401	}
402
403	static void dino_assign_irq(struct dino_device dino, int local_irq, int irqp)
404	{
405	int irq = gsc_assign_irq(&dino_interrupt_type, dino);
406	if (irq == NO_IRQ)
407	return;
408
409	*irqp = irq;
410	dino->global_irq[local_irq] = irq;
411	}
412
413	static void dino_choose_irq(struct parisc_device dev, void ctrl)
414	{
415	int irq;
416	struct dino_device *dino = ctrl;
417
418	switch (dev->id.sversion) {
419	case 0x00084: irq = 8; break; /* PS/2 */
420	case 0x0008c: irq = 10; break; /* RS232 */
421	case 0x00096: irq = 8; break; /* PS/2 */
422	default: return; /* Unknown */
423	}
424
425	dino_assign_irq(dino, irq, &dev->irq);
426	}
427
428
429	/*
430	* Cirrus 6832 Cardbus reports wrong irq on RDI Tadpole PARISC Laptop (deller@gmx.de)
431	* (the irqs are off-by-one, not sure yet if this is a cirrus, dino-hardware or dino-driver problem...)
432	*/
433	static void __devinit quirk_cirrus_cardbus(struct pci_dev *dev)
434	{
435	u8 new_irq = dev->irq - 1;
436	printk(KERN_INFO "PCI: Cirrus Cardbus IRQ fixup for %s, from %d to %d\n",
437	pci_name(dev), dev->irq, new_irq);
438	dev->irq = new_irq;
439	}
440	DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_CIRRUS, PCI_DEVICE_ID_CIRRUS_6832, quirk_cirrus_cardbus );
441
442
443	static void __init
444	dino_bios_init(void)
445	{
446	DBG("dino_bios_init\n");
447	}
448
449	/*
450	* dino_card_setup - Set up the memory space for a Dino in card mode.
451	* @bus: the bus under this dino
452	*
453	* Claim an 8MB chunk of unused IO space and call the generic PCI routines
454	* to set up the addresses of the devices on this bus.
455	*/
456	#define _8MB 0x00800000UL
457	static void __init
458	dino_card_setup(struct pci_bus bus, void __iomem base_addr)
459	{
460	int i;
461	struct dino_device *dino_dev = DINO_DEV(parisc_walk_tree(bus->bridge));
462	struct resource *res;
463	char name[128];
464	int size;
465
466	res = &dino_dev->hba.lmmio_space;
467	res->flags = IORESOURCE_MEM;
468	size = scnprintf(name, sizeof(name), "Dino LMMIO (%s)",
469	dev_name(bus->bridge));
470	res->name = kmalloc(size+1, GFP_KERNEL);
471	if(res->name)
472	strcpy((char *)res->name, name);
473	else
474	res->name = dino_dev->hba.lmmio_space.name;
475
476
477	if (ccio_allocate_resource(dino_dev->hba.dev, res, _8MB,
478	F_EXTEND(0xf0000000UL) \| _8MB,
479	F_EXTEND(0xffffffffUL) &~ _8MB, _8MB) < 0) {
480	struct list_head ln, tmp_ln;
481
482	printk(KERN_ERR "Dino: cannot attach bus %s\n",
483	dev_name(bus->bridge));
484	/* kill the bus, we can't do anything with it */
485	list_for_each_safe(ln, tmp_ln, &bus->devices) {
486	struct pci_dev *dev = pci_dev_b(ln);
487
488	list_del(&dev->bus_list);
489	}
490
491	return;
492	}
493	bus->resource[1] = res;
494	bus->resource[0] = &(dino_dev->hba.io_space);
495
496	/* Now tell dino what range it has */
497	for (i = 1; i < 31; i++) {
498	if (res->start == F_EXTEND(0xf0000000UL \| (i * _8MB)))
499	break;
500	}
501	DBG("DINO GSC WRITE i=%d, start=%lx, dino addr = %p\n",
502	i, res->start, base_addr + DINO_IO_ADDR_EN);
503	__raw_writel(1 << i, base_addr + DINO_IO_ADDR_EN);
504	}
505
506	static void __init
507	dino_card_fixup(struct pci_dev *dev)
508	{
509	u32 irq_pin;
510
511	/*
512	** REVISIT: card-mode PCI-PCI expansion chassis do exist.
513	** Not sure they were ever productized.
514	** Die here since we'll die later in dino_inb() anyway.
515	*/
516	if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
517	panic("Card-Mode Dino: PCI-PCI Bridge not supported\n");
518	}
519
520	/*
521	** Set Latency Timer to 0xff (not a shared bus)
522	** Set CACHELINE_SIZE.
523	*/
524	dino_cfg_write(dev->bus, dev->devfn,
525	PCI_CACHE_LINE_SIZE, 2, 0xff00 \| L1_CACHE_BYTES/4);
526
527	/*
528	** Program INT_LINE for card-mode devices.
529	** The cards are hardwired according to this algorithm.
530	** And it doesn't matter if PPB's are present or not since
531	** the IRQ lines bypass the PPB.
532	**
533	** "-1" converts INTA-D (1-4) to PCIINTA-D (0-3) range.
534	** The additional "-1" adjusts for skewing the IRQ<->slot.
535	*/
536	dino_cfg_read(dev->bus, dev->devfn, PCI_INTERRUPT_PIN, 1, &irq_pin);
537	dev->irq = pci_swizzle_interrupt_pin(dev, irq_pin) - 1;
538
539	/* Shouldn't really need to do this but it's in case someone tries
540	** to bypass PCI services and look at the card themselves.
541	*/
542	dino_cfg_write(dev->bus, dev->devfn, PCI_INTERRUPT_LINE, 1, dev->irq);
543	}
544
545	/* The alignment contraints for PCI bridges under dino */
546	#define DINO_BRIDGE_ALIGN 0x100000
547
548
549	static void __init
550	dino_fixup_bus(struct pci_bus *bus)
551	{
552	struct list_head *ln;
553	struct pci_dev *dev;
554	struct dino_device *dino_dev = DINO_DEV(parisc_walk_tree(bus->bridge));
555
556	DBG(KERN_WARNING "%s(0x%p) bus %d platform_data 0x%p\n",
557	__func__, bus, bus->busn_res.start,
558	bus->bridge->platform_data);
559
560	/* Firmware doesn't set up card-mode dino, so we have to */
561	if (is_card_dino(&dino_dev->hba.dev->id)) {
562	dino_card_setup(bus, dino_dev->hba.base_addr);
563	} else if (bus->parent) {
564	int i;
565
566	pci_read_bridge_bases(bus);
567
568
569	for(i = PCI_BRIDGE_RESOURCES; i < PCI_NUM_RESOURCES; i++) {
570	if((bus->self->resource[i].flags &
571	(IORESOURCE_IO \| IORESOURCE_MEM)) == 0)
572	continue;
573
574	if(bus->self->resource[i].flags & IORESOURCE_MEM) {
575	/* There's a quirk to alignment of
576	* bridge memory resources: the start
577	* is the alignment and start-end is
578	* the size. However, firmware will
579	* have assigned start and end, so we
580	* need to take this into account */
581	bus->self->resource[i].end = bus->self->resource[i].end - bus->self->resource[i].start + DINO_BRIDGE_ALIGN;
582	bus->self->resource[i].start = DINO_BRIDGE_ALIGN;
583
584	}
585
586	DBG("DEBUG %s assigning %d [0x%lx,0x%lx]\n",
587	dev_name(&bus->self->dev), i,
588	bus->self->resource[i].start,
589	bus->self->resource[i].end);
590	WARN_ON(pci_assign_resource(bus->self, i));
591	DBG("DEBUG %s after assign %d [0x%lx,0x%lx]\n",
592	dev_name(&bus->self->dev), i,
593	bus->self->resource[i].start,
594	bus->self->resource[i].end);
595	}
596	}
597
598
599	list_for_each(ln, &bus->devices) {
600	dev = pci_dev_b(ln);
601	if (is_card_dino(&dino_dev->hba.dev->id))
602	dino_card_fixup(dev);
603
604	/*
605	** P2PB's only have 2 BARs, no IRQs.
606	** I'd like to just ignore them for now.
607	*/
608	if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI)
609	continue;
610
611	/* null out the ROM resource if there is one (we don't
612	* care about an expansion rom on parisc, since it
613	* usually contains (x86) bios code) */
614	dev->resource[PCI_ROM_RESOURCE].flags = 0;
615
616	if(dev->irq == 255) {
617
618	#define DINO_FIX_UNASSIGNED_INTERRUPTS
619	#ifdef DINO_FIX_UNASSIGNED_INTERRUPTS
620
621	/* This code tries to assign an unassigned
622	* interrupt. Leave it disabled unless you
623	* really know what you're doing since the
624	* pin<->interrupt line mapping varies by bus
625	* and machine */
626
627	u32 irq_pin;
628
629	dino_cfg_read(dev->bus, dev->devfn,
630	PCI_INTERRUPT_PIN, 1, &irq_pin);
631	irq_pin = pci_swizzle_interrupt_pin(dev, irq_pin) - 1;
632	printk(KERN_WARNING "Device %s has undefined IRQ, "
633	"setting to %d\n", pci_name(dev), irq_pin);
634	dino_cfg_write(dev->bus, dev->devfn,
635	PCI_INTERRUPT_LINE, 1, irq_pin);
636	dino_assign_irq(dino_dev, irq_pin, &dev->irq);
637	#else
638	dev->irq = 65535;
639	printk(KERN_WARNING "Device %s has unassigned IRQ\n", pci_name(dev));
640	#endif
641	} else {
642	/* Adjust INT_LINE for that busses region */
643	dino_assign_irq(dino_dev, dev->irq, &dev->irq);
644	}
645	}
646	}
647
648
649	static struct pci_bios_ops dino_bios_ops = {
650	.init = dino_bios_init,
651	.fixup_bus = dino_fixup_bus
652	};
653
654
655	/*
656	* Initialise a DINO controller chip
657	*/
658	static void __init
659	dino_card_init(struct dino_device *dino_dev)
660	{
661	u32 brdg_feat = 0x00784e05;
662	unsigned long status;
663
664	status = __raw_readl(dino_dev->hba.base_addr+DINO_IO_STATUS);
665	if (status & 0x0000ff80) {
666	__raw_writel(0x00000005,
667	dino_dev->hba.base_addr+DINO_IO_COMMAND);
668	udelay(1);
669	}
670
671	__raw_writel(0x00000000, dino_dev->hba.base_addr+DINO_GMASK);
672	__raw_writel(0x00000001, dino_dev->hba.base_addr+DINO_IO_FBB_EN);
673	__raw_writel(0x00000000, dino_dev->hba.base_addr+DINO_ICR);
674
675	#if 1
676	/* REVISIT - should be a runtime check (eg if (CPU_IS_PCX_L) ...) */
677	/*
678	** PCX-L processors don't support XQL like Dino wants it.
679	** PCX-L2 ignore XQL signal and it doesn't matter.
680	*/
681	brdg_feat &= ~0x4; /* UXQL */
682	#endif
683	__raw_writel( brdg_feat, dino_dev->hba.base_addr+DINO_BRDG_FEAT);
684
685	/*
686	** Don't enable address decoding until we know which I/O range
687	** currently is available from the host. Only affects MMIO
688	** and not I/O port space.
689	*/
690	__raw_writel(0x00000000, dino_dev->hba.base_addr+DINO_IO_ADDR_EN);
691
692	__raw_writel(0x00000000, dino_dev->hba.base_addr+DINO_DAMODE);
693	__raw_writel(0x00222222, dino_dev->hba.base_addr+DINO_PCIROR);
694	__raw_writel(0x00222222, dino_dev->hba.base_addr+DINO_PCIWOR);
695
696	__raw_writel(0x00000040, dino_dev->hba.base_addr+DINO_MLTIM);
697	__raw_writel(0x00000080, dino_dev->hba.base_addr+DINO_IO_CONTROL);
698	__raw_writel(0x0000008c, dino_dev->hba.base_addr+DINO_TLTIM);
699
700	/* Disable PAMR before writing PAPR */
701	__raw_writel(0x0000007e, dino_dev->hba.base_addr+DINO_PAMR);
702	__raw_writel(0x0000007f, dino_dev->hba.base_addr+DINO_PAPR);
703	__raw_writel(0x00000000, dino_dev->hba.base_addr+DINO_PAMR);
704
705	/*
706	** Dino ERS encourages enabling FBB (0x6f).
707	** We can't until we know all devices below us can support it.
708	** (Something in device configuration header tells us).
709	*/
710	__raw_writel(0x0000004f, dino_dev->hba.base_addr+DINO_PCICMD);
711
712	/* Somewhere, the PCI spec says give devices 1 second
713	** to recover from the #RESET being de-asserted.
714	** Experience shows most devices only need 10ms.
715	** This short-cut speeds up booting significantly.
716	*/
717	mdelay(pci_post_reset_delay);
718	}
719
720	static int __init
721	dino_bridge_init(struct dino_device dino_dev, const char name)
722	{
723	unsigned long io_addr;
724	int result, i, count=0;
725	struct resource res, prevres = NULL;
726	/*
727	* Decoding IO_ADDR_EN only works for Built-in Dino
728	* since PDC has already initialized this.
729	*/
730
731	io_addr = __raw_readl(dino_dev->hba.base_addr + DINO_IO_ADDR_EN);
732	if (io_addr == 0) {
733	printk(KERN_WARNING "%s: No PCI devices enabled.\n", name);
734	return -ENODEV;
735	}
736
737	res = &dino_dev->hba.lmmio_space;
738	for (i = 0; i < 32; i++) {
739	unsigned long start, end;
740
741	if((io_addr & (1 << i)) == 0)
742	continue;
743
744	start = F_EXTEND(0xf0000000UL) \| (i << 23);
745	end = start + 8 * 1024 * 1024 - 1;
746
747	DBG("DINO RANGE %d is at 0x%lx-0x%lx\n", count,
748	start, end);
749
750	if(prevres && prevres->end + 1 == start) {
751	prevres->end = end;
752	} else {
753	if(count >= DINO_MAX_LMMIO_RESOURCES) {
754	printk(KERN_ERR "%s is out of resource windows for range %d (0x%lx-0x%lx)\n", name, count, start, end);
755	break;
756	}
757	prevres = res;
758	res->start = start;
759	res->end = end;
760	res->flags = IORESOURCE_MEM;
761	res->name = kmalloc(64, GFP_KERNEL);
762	if(res->name)
763	snprintf((char *)res->name, 64, "%s LMMIO %d",
764	name, count);
765	res++;
766	count++;
767	}
768	}
769
770	res = &dino_dev->hba.lmmio_space;
771
772	for(i = 0; i < DINO_MAX_LMMIO_RESOURCES; i++) {
773	if(res[i].flags == 0)
774	break;
775
776	result = ccio_request_resource(dino_dev->hba.dev, &res[i]);
777	if (result < 0) {
778	printk(KERN_ERR "%s: failed to claim PCI Bus address "
779	"space %d (0x%lx-0x%lx)!\n", name, i,
780	(unsigned long)res[i].start, (unsigned long)res[i].end);
781	return result;
782	}
783	}
784	return 0;
785	}
786
787	static int __init dino_common_init(struct parisc_device *dev,
788	struct dino_device dino_dev, const char name)
789	{
790	int status;
791	u32 eim;
792	struct gsc_irq gsc_irq;
793	struct resource *res;
794
795	pcibios_register_hba(&dino_dev->hba);
796
797	pci_bios = &dino_bios_ops; /* used by pci_scan_bus() */
798	pci_port = &dino_port_ops;
799
800	/*
801	** Note: SMP systems can make use of IRR1/IAR1 registers
802	** But it won't buy much performance except in very
803	** specific applications/configurations. Note Dino
804	** still only has 11 IRQ input lines - just map some of them
805	** to a different processor.
806	*/
807	dev->irq = gsc_alloc_irq(&gsc_irq);
808	dino_dev->txn_addr = gsc_irq.txn_addr;
809	dino_dev->txn_data = gsc_irq.txn_data;
810	eim = ((u32) gsc_irq.txn_addr) \| gsc_irq.txn_data;
811
812	/*
813	** Dino needs a PA "IRQ" to get a processor's attention.
814	** arch/parisc/kernel/irq.c returns an EIRR bit.
815	*/
816	if (dev->irq < 0) {
817	printk(KERN_WARNING "%s: gsc_alloc_irq() failed\n", name);
818	return 1;
819	}
820
821	status = request_irq(dev->irq, dino_isr, 0, name, dino_dev);
822	if (status) {
823	printk(KERN_WARNING "%s: request_irq() failed with %d\n",
824	name, status);
825	return 1;
826	}
827
828	/* Support the serial port which is sometimes attached on built-in
829	* Dino / Cujo chips.
830	*/
831
832	gsc_fixup_irqs(dev, dino_dev, dino_choose_irq);
833
834	/*
835	** This enables DINO to generate interrupts when it sees
836	** any of its inputs change. Just asserting an IRQ
837	** before it's enabled (ie unmasked) isn't good enough.
838	*/
839	__raw_writel(eim, dino_dev->hba.base_addr+DINO_IAR0);
840
841	/*
842	** Some platforms don't clear Dino's IRR0 register at boot time.
843	** Reading will clear it now.
844	*/
845	__raw_readl(dino_dev->hba.base_addr+DINO_IRR0);
846
847	/* allocate I/O Port resource region */
848	res = &dino_dev->hba.io_space;
849	if (!is_cujo(&dev->id)) {
850	res->name = "Dino I/O Port";
851	} else {
852	res->name = "Cujo I/O Port";
853	}
854	res->start = HBA_PORT_BASE(dino_dev->hba.hba_num);
855	res->end = res->start + (HBA_PORT_SPACE_SIZE - 1);
856	res->flags = IORESOURCE_IO; /* do not mark it busy ! */
857	if (request_resource(&ioport_resource, res) < 0) {
858	printk(KERN_ERR "%s: request I/O Port region failed "
859	"0x%lx/%lx (hpa 0x%p)\n",
860	name, (unsigned long)res->start, (unsigned long)res->end,
861	dino_dev->hba.base_addr);
862	return 1;
863	}
864
865	return 0;
866	}
867
868	#define CUJO_RAVEN_ADDR F_EXTEND(0xf1000000UL)
869	#define CUJO_FIREHAWK_ADDR F_EXTEND(0xf1604000UL)
870	#define CUJO_RAVEN_BADPAGE 0x01003000UL
871	#define CUJO_FIREHAWK_BADPAGE 0x01607000UL
872
873	static const char *dino_vers[] = {
874	"2.0",
875	"2.1",
876	"3.0",
877	"3.1"
878	};
879
880	static const char *cujo_vers[] = {
881	"1.0",
882	"2.0"
883	};
884
885	void ccio_cujo20_fixup(struct parisc_device *dev, u32 iovp);
886
887	/*
888	** Determine if dino should claim this chip (return 0) or not (return 1).
889	** If so, initialize the chip appropriately (card-mode vs bridge mode).
890	** Much of the initialization is common though.
891	*/
892	static int __init dino_probe(struct parisc_device *dev)
893	{
894	struct dino_device *dino_dev; // Dino specific control struct
895	const char *version = "unknown";
896	char *name;
897	int is_cujo = 0;
898	LIST_HEAD(resources);
899	struct pci_bus *bus;
900	unsigned long hpa = dev->hpa.start;
901	int max;
902
903	name = "Dino";
904	if (is_card_dino(&dev->id)) {
905	version = "3.x (card mode)";
906	} else {
907	if (!is_cujo(&dev->id)) {
908	if (dev->id.hversion_rev < 4) {
909	version = dino_vers[dev->id.hversion_rev];
910	}
911	} else {
912	name = "Cujo";
913	is_cujo = 1;
914	if (dev->id.hversion_rev < 2) {
915	version = cujo_vers[dev->id.hversion_rev];
916	}
917	}
918	}
919
920	printk("%s version %s found at 0x%lx\n", name, version, hpa);
921
922	if (!request_mem_region(hpa, PAGE_SIZE, name)) {
923	printk(KERN_ERR "DINO: Hey! Someone took my MMIO space (0x%ld)!\n",
924	hpa);
925	return 1;
926	}
927
928	/* Check for bugs */
929	if (is_cujo && dev->id.hversion_rev == 1) {
930	#ifdef CONFIG_IOMMU_CCIO
931	printk(KERN_WARNING "Enabling Cujo 2.0 bug workaround\n");
932	if (hpa == (unsigned long)CUJO_RAVEN_ADDR) {
933	ccio_cujo20_fixup(dev, CUJO_RAVEN_BADPAGE);
934	} else if (hpa == (unsigned long)CUJO_FIREHAWK_ADDR) {
935	ccio_cujo20_fixup(dev, CUJO_FIREHAWK_BADPAGE);
936	} else {
937	printk("Don't recognise Cujo at address 0x%lx, not enabling workaround\n", hpa);
938	}
939	#endif
940	} else if (!is_cujo && !is_card_dino(&dev->id) &&
941	dev->id.hversion_rev < 3) {
942	printk(KERN_WARNING
943	"The GSCtoPCI (Dino hrev %d) bus converter found may exhibit\n"
944	"data corruption. See Service Note Numbers: A4190A-01, A4191A-01.\n"
945	"Systems shipped after Aug 20, 1997 will not exhibit this problem.\n"
946	"Models affected: C180, C160, C160L, B160L, and B132L workstations.\n\n",
947	dev->id.hversion_rev);
948	/* REVISIT: why are C200/C240 listed in the README table but not
949	** "Models affected"? Could be an omission in the original literature.
950	*/
951	}
952
953	dino_dev = kzalloc(sizeof(struct dino_device), GFP_KERNEL);
954	if (!dino_dev) {
955	printk("dino_init_chip - couldn't alloc dino_device\n");
956	return 1;
957	}
958
959	dino_dev->hba.dev = dev;
960	dino_dev->hba.base_addr = ioremap_nocache(hpa, 4096);
961	dino_dev->hba.lmmio_space_offset = 0; /* CPU addrs == bus addrs */
962	spin_lock_init(&dino_dev->dinosaur_pen);
963	dino_dev->hba.iommu = ccio_get_iommu(dev);
964
965	if (is_card_dino(&dev->id)) {
966	dino_card_init(dino_dev);
967	} else {
968	dino_bridge_init(dino_dev, name);
969	}
970
971	if (dino_common_init(dev, dino_dev, name))
972	return 1;
973
974	dev->dev.platform_data = dino_dev;
975
976	pci_add_resource_offset(&resources, &dino_dev->hba.io_space,
977	HBA_PORT_BASE(dino_dev->hba.hba_num));
978	if (dino_dev->hba.lmmio_space.flags)
979	pci_add_resource_offset(&resources, &dino_dev->hba.lmmio_space,
980	dino_dev->hba.lmmio_space_offset);
981	if (dino_dev->hba.elmmio_space.flags)
982	pci_add_resource_offset(&resources, &dino_dev->hba.elmmio_space,
983	dino_dev->hba.lmmio_space_offset);
984	if (dino_dev->hba.gmmio_space.flags)
985	pci_add_resource(&resources, &dino_dev->hba.gmmio_space);
986
987	dino_dev->hba.bus_num.start = dino_current_bus;
988	dino_dev->hba.bus_num.end = 255;
989	dino_dev->hba.bus_num.flags = IORESOURCE_BUS;
990	pci_add_resource(&resources, &dino_dev->hba.bus_num);
991	/*
992	** It's not used to avoid chicken/egg problems
993	** with configuration accessor functions.
994	*/
995	dino_dev->hba.hba_bus = bus = pci_create_root_bus(&dev->dev,
996	dino_current_bus, &dino_cfg_ops, NULL, &resources);
997	if (!bus) {
998	printk(KERN_ERR "ERROR: failed to scan PCI bus on %s (duplicate bus number %d?)\n",
999	dev_name(&dev->dev), dino_current_bus);
1000	pci_free_resource_list(&resources);
1001	/* increment the bus number in case of duplicates */
1002	dino_current_bus++;
1003	return 0;
1004	}
1005
1006	max = pci_scan_child_bus(bus);
1007	pci_bus_update_busn_res_end(bus, max);
1008
1009	/* This code depends on scanning being single threaded
1010	* if it isn't, this global bus number count will fail
1011	*/
1012	dino_current_bus = max + 1;
1013	pci_bus_assign_resources(bus);
1014	pci_bus_add_devices(bus);
1015	return 0;
1016	}
1017
1018	/*
1019	* Normally, we would just test sversion. But the Elroy PCI adapter has
1020	* the same sversion as Dino, so we have to check hversion as well.
1021	* Unfortunately, the J2240 PDC reports the wrong hversion for the first
1022	* Dino, so we have to test for Dino, Cujo and Dino-in-a-J2240.
1023	* For card-mode Dino, most machines report an sversion of 9D. But 715
1024	* and 725 firmware misreport it as 0x08080 for no adequately explained
1025	* reason.
1026	*/
1027	static struct parisc_device_id dino_tbl[] = {
1028	{ HPHW_A_DMA, HVERSION_REV_ANY_ID, 0x004, 0x0009D },/* Card-mode Dino */
1029	{ HPHW_A_DMA, HVERSION_REV_ANY_ID, HVERSION_ANY_ID, 0x08080 }, /* XXX */
1030	{ HPHW_BRIDGE, HVERSION_REV_ANY_ID, 0x680, 0xa }, /* Bridge-mode Dino */
1031	{ HPHW_BRIDGE, HVERSION_REV_ANY_ID, 0x682, 0xa }, /* Bridge-mode Cujo */
1032	{ HPHW_BRIDGE, HVERSION_REV_ANY_ID, 0x05d, 0xa }, /* Dino in a J2240 */
1033	{ 0, }
1034	};
1035
1036	static struct parisc_driver dino_driver = {
1037	.name = "dino",
1038	.id_table = dino_tbl,
1039	.probe = dino_probe,
1040	};
1041
1042	/*
1043	* One time initialization to let the world know Dino is here.
1044	* This is the only routine which is NOT static.
1045	* Must be called exactly once before pci_init().
1046	*/
1047	int __init dino_init(void)
1048	{
1049	register_parisc_driver(&dino_driver);
1050	return 0;
1051	}
1052
1053

Download this file

Branches:
ben-wpan
ben-wpan-stefan
javiroman/ks7010
jz-2.6.34
jz-2.6.34-rc5
jz-2.6.34-rc6
jz-2.6.34-rc7
jz-2.6.35
jz-2.6.36
jz-2.6.37
jz-2.6.38
jz-2.6.39
jz-3.0
jz-3.1
jz-3.11
jz-3.12
jz-3.13
jz-3.15
jz-3.16
jz-3.18-dt
jz-3.2
jz-3.3
jz-3.4
jz-3.5
jz-3.6
jz-3.6-rc2-pwm
jz-3.9
jz-3.9-clk
jz-3.9-rc8
jz47xx
jz47xx-2.6.38
master

Tags:
od-2011-09-04
od-2011-09-18
v2.6.34-rc5
v2.6.34-rc6
v2.6.34-rc7
v3.9

Kernel

Kernel Git Source Tree

Root/drivers/parisc/dino.c

interactive