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Root/drivers/parport/parport_pc.c

1	/* Low-level parallel-port routines for 8255-based PC-style hardware.
2	*
3	* Authors: Phil Blundell <philb@gnu.org>
4	* Tim Waugh <tim@cyberelk.demon.co.uk>
5	* Jose Renau <renau@acm.org>
6	* David Campbell
7	* Andrea Arcangeli
8	*
9	* based on work by Grant Guenther <grant@torque.net> and Phil Blundell.
10	*
11	* Cleaned up include files - Russell King <linux@arm.uk.linux.org>
12	* DMA support - Bert De Jonghe <bert@sophis.be>
13	* Many ECP bugs fixed. Fred Barnes & Jamie Lokier, 1999
14	* More PCI support now conditional on CONFIG_PCI, 03/2001, Paul G.
15	* Various hacks, Fred Barnes, 04/2001
16	* Updated probing logic - Adam Belay <ambx1@neo.rr.com>
17	*/
18
19	/* This driver should work with any hardware that is broadly compatible
20	* with that in the IBM PC. This applies to the majority of integrated
21	* I/O chipsets that are commonly available. The expected register
22	* layout is:
23	*
24	* base+0 data
25	* base+1 status
26	* base+2 control
27	*
28	* In addition, there are some optional registers:
29	*
30	* base+3 EPP address
31	* base+4 EPP data
32	* base+0x400 ECP config A
33	* base+0x401 ECP config B
34	* base+0x402 ECP control
35	*
36	* All registers are 8 bits wide and read/write. If your hardware differs
37	* only in register addresses (eg because your registers are on 32-bit
38	* word boundaries) then you can alter the constants in parport_pc.h to
39	* accommodate this.
40	*
41	* Note that the ECP registers may not start at offset 0x400 for PCI cards,
42	* but rather will start at port->base_hi.
43	*/
44
45	#include <linux/module.h>
46	#include <linux/init.h>
47	#include <linux/sched.h>
48	#include <linux/delay.h>
49	#include <linux/errno.h>
50	#include <linux/interrupt.h>
51	#include <linux/ioport.h>
52	#include <linux/kernel.h>
53	#include <linux/slab.h>
54	#include <linux/dma-mapping.h>
55	#include <linux/pci.h>
56	#include <linux/pnp.h>
57	#include <linux/platform_device.h>
58	#include <linux/sysctl.h>
59	#include <linux/io.h>
60	#include <linux/uaccess.h>
61
62	#include <asm/dma.h>
63
64	#include <linux/parport.h>
65	#include <linux/parport_pc.h>
66	#include <linux/via.h>
67	#include <asm/parport.h>
68
69	#define PARPORT_PC_MAX_PORTS PARPORT_MAX
70
71	#ifdef CONFIG_ISA_DMA_API
72	#define HAS_DMA
73	#endif
74
75	/* ECR modes */
76	#define ECR_SPP 00
77	#define ECR_PS2 01
78	#define ECR_PPF 02
79	#define ECR_ECP 03
80	#define ECR_EPP 04
81	#define ECR_VND 05
82	#define ECR_TST 06
83	#define ECR_CNF 07
84	#define ECR_MODE_MASK 0xe0
85	#define ECR_WRITE(p, v) frob_econtrol((p), 0xff, (v))
86
87	#undef DEBUG
88
89	#ifdef DEBUG
90	#define DPRINTK printk
91	#else
92	#define DPRINTK(stuff...)
93	#endif
94
95
96	#define NR_SUPERIOS 3
97	static struct superio_struct { /* For Super-IO chips autodetection */
98	int io;
99	int irq;
100	int dma;
101	} superios[NR_SUPERIOS] = { {0,},};
102
103	static int user_specified;
104	#if defined(CONFIG_PARPORT_PC_SUPERIO) \|\| \
105	(defined(CONFIG_PARPORT_1284) && defined(CONFIG_PARPORT_PC_FIFO))
106	static int verbose_probing;
107	#endif
108	static int pci_registered_parport;
109	static int pnp_registered_parport;
110
111	/* frob_control, but for ECR */
112	static void frob_econtrol(struct parport *pb, unsigned char m,
113	unsigned char v)
114	{
115	unsigned char ectr = 0;
116
117	if (m != 0xff)
118	ectr = inb(ECONTROL(pb));
119
120	DPRINTK(KERN_DEBUG "frob_econtrol(%02x,%02x): %02x -> %02x\n",
121	m, v, ectr, (ectr & ~m) ^ v);
122
123	outb((ectr & ~m) ^ v, ECONTROL(pb));
124	}
125
126	static inline void frob_set_mode(struct parport *p, int mode)
127	{
128	frob_econtrol(p, ECR_MODE_MASK, mode << 5);
129	}
130
131	#ifdef CONFIG_PARPORT_PC_FIFO
132	/* Safely change the mode bits in the ECR
133	Returns:
134	0 : Success
135	-EBUSY: Could not drain FIFO in some finite amount of time,
136	mode not changed!
137	*/
138	static int change_mode(struct parport *p, int m)
139	{
140	const struct parport_pc_private *priv = p->physport->private_data;
141	unsigned char oecr;
142	int mode;
143
144	DPRINTK(KERN_INFO "parport change_mode ECP-ISA to mode 0x%02x\n", m);
145
146	if (!priv->ecr) {
147	printk(KERN_DEBUG "change_mode: but there's no ECR!\n");
148	return 0;
149	}
150
151	/* Bits <7:5> contain the mode. */
152	oecr = inb(ECONTROL(p));
153	mode = (oecr >> 5) & 0x7;
154	if (mode == m)
155	return 0;
156
157	if (mode >= 2 && !(priv->ctr & 0x20)) {
158	/* This mode resets the FIFO, so we may
159	* have to wait for it to drain first. */
160	unsigned long expire = jiffies + p->physport->cad->timeout;
161	int counter;
162	switch (mode) {
163	case ECR_PPF: /* Parallel Port FIFO mode */
164	case ECR_ECP: /* ECP Parallel Port mode */
165	/* Busy wait for 200us */
166	for (counter = 0; counter < 40; counter++) {
167	if (inb(ECONTROL(p)) & 0x01)
168	break;
169	if (signal_pending(current))
170	break;
171	udelay(5);
172	}
173
174	/* Poll slowly. */
175	while (!(inb(ECONTROL(p)) & 0x01)) {
176	if (time_after_eq(jiffies, expire))
177	/* The FIFO is stuck. */
178	return -EBUSY;
179	schedule_timeout_interruptible(
180	msecs_to_jiffies(10));
181	if (signal_pending(current))
182	break;
183	}
184	}
185	}
186
187	if (mode >= 2 && m >= 2) {
188	/* We have to go through mode 001 */
189	oecr &= ~(7 << 5);
190	oecr \|= ECR_PS2 << 5;
191	ECR_WRITE(p, oecr);
192	}
193
194	/* Set the mode. */
195	oecr &= ~(7 << 5);
196	oecr \|= m << 5;
197	ECR_WRITE(p, oecr);
198	return 0;
199	}
200	#endif /* FIFO support */
201
202	/*
203	* Clear TIMEOUT BIT in EPP MODE
204	*
205	* This is also used in SPP detection.
206	*/
207	static int clear_epp_timeout(struct parport *pb)
208	{
209	unsigned char r;
210
211	if (!(parport_pc_read_status(pb) & 0x01))
212	return 1;
213
214	/* To clear timeout some chips require double read */
215	parport_pc_read_status(pb);
216	r = parport_pc_read_status(pb);
217	outb(r \| 0x01, STATUS(pb)); /* Some reset by writing 1 */
218	outb(r & 0xfe, STATUS(pb)); /* Others by writing 0 */
219	r = parport_pc_read_status(pb);
220
221	return !(r & 0x01);
222	}
223
224	/*
225	* Access functions.
226	*
227	* Most of these aren't static because they may be used by the
228	* parport_xxx_yyy macros. extern __inline__ versions of several
229	* of these are in parport_pc.h.
230	*/
231
232	static void parport_pc_init_state(struct pardevice *dev,
233	struct parport_state *s)
234	{
235	s->u.pc.ctr = 0xc;
236	if (dev->irq_func &&
237	dev->port->irq != PARPORT_IRQ_NONE)
238	/* Set ackIntEn */
239	s->u.pc.ctr \|= 0x10;
240
241	s->u.pc.ecr = 0x34; /* NetMos chip can cause problems 0x24;
242	* D.Gruszka VScom */
243	}
244
245	static void parport_pc_save_state(struct parport p, struct parport_state s)
246	{
247	const struct parport_pc_private *priv = p->physport->private_data;
248	s->u.pc.ctr = priv->ctr;
249	if (priv->ecr)
250	s->u.pc.ecr = inb(ECONTROL(p));
251	}
252
253	static void parport_pc_restore_state(struct parport *p,
254	struct parport_state *s)
255	{
256	struct parport_pc_private *priv = p->physport->private_data;
257	register unsigned char c = s->u.pc.ctr & priv->ctr_writable;
258	outb(c, CONTROL(p));
259	priv->ctr = c;
260	if (priv->ecr)
261	ECR_WRITE(p, s->u.pc.ecr);
262	}
263
264	#ifdef CONFIG_PARPORT_1284
265	static size_t parport_pc_epp_read_data(struct parport port, void buf,
266	size_t length, int flags)
267	{
268	size_t got = 0;
269
270	if (flags & PARPORT_W91284PIC) {
271	unsigned char status;
272	size_t left = length;
273
274	/* use knowledge about data lines..:
275	* nFault is 0 if there is at least 1 byte in the Warp's FIFO
276	* pError is 1 if there are 16 bytes in the Warp's FIFO
277	*/
278	status = inb(STATUS(port));
279
280	while (!(status & 0x08) && got < length) {
281	if (left >= 16 && (status & 0x20) && !(status & 0x08)) {
282	/* can grab 16 bytes from warp fifo */
283	if (!((long)buf & 0x03))
284	insl(EPPDATA(port), buf, 4);
285	else
286	insb(EPPDATA(port), buf, 16);
287	buf += 16;
288	got += 16;
289	left -= 16;
290	} else {
291	/* grab single byte from the warp fifo */
292	((char )buf) = inb(EPPDATA(port));
293	buf++;
294	got++;
295	left--;
296	}
297	status = inb(STATUS(port));
298	if (status & 0x01) {
299	/* EPP timeout should never occur... */
300	printk(KERN_DEBUG
301	"%s: EPP timeout occurred while talking to w91284pic (should not have done)\n", port->name);
302	clear_epp_timeout(port);
303	}
304	}
305	return got;
306	}
307	if ((flags & PARPORT_EPP_FAST) && (length > 1)) {
308	if (!(((long)buf \| length) & 0x03))
309	insl(EPPDATA(port), buf, (length >> 2));
310	else
311	insb(EPPDATA(port), buf, length);
312	if (inb(STATUS(port)) & 0x01) {
313	clear_epp_timeout(port);
314	return -EIO;
315	}
316	return length;
317	}
318	for (; got < length; got++) {
319	((char )buf) = inb(EPPDATA(port));
320	buf++;
321	if (inb(STATUS(port)) & 0x01) {
322	/* EPP timeout */
323	clear_epp_timeout(port);
324	break;
325	}
326	}
327
328	return got;
329	}
330
331	static size_t parport_pc_epp_write_data(struct parport port, const void buf,
332	size_t length, int flags)
333	{
334	size_t written = 0;
335
336	if ((flags & PARPORT_EPP_FAST) && (length > 1)) {
337	if (!(((long)buf \| length) & 0x03))
338	outsl(EPPDATA(port), buf, (length >> 2));
339	else
340	outsb(EPPDATA(port), buf, length);
341	if (inb(STATUS(port)) & 0x01) {
342	clear_epp_timeout(port);
343	return -EIO;
344	}
345	return length;
346	}
347	for (; written < length; written++) {
348	outb(((char )buf), EPPDATA(port));
349	buf++;
350	if (inb(STATUS(port)) & 0x01) {
351	clear_epp_timeout(port);
352	break;
353	}
354	}
355
356	return written;
357	}
358
359	static size_t parport_pc_epp_read_addr(struct parport port, void buf,
360	size_t length, int flags)
361	{
362	size_t got = 0;
363
364	if ((flags & PARPORT_EPP_FAST) && (length > 1)) {
365	insb(EPPADDR(port), buf, length);
366	if (inb(STATUS(port)) & 0x01) {
367	clear_epp_timeout(port);
368	return -EIO;
369	}
370	return length;
371	}
372	for (; got < length; got++) {
373	((char )buf) = inb(EPPADDR(port));
374	buf++;
375	if (inb(STATUS(port)) & 0x01) {
376	clear_epp_timeout(port);
377	break;
378	}
379	}
380
381	return got;
382	}
383
384	static size_t parport_pc_epp_write_addr(struct parport *port,
385	const void *buf, size_t length,
386	int flags)
387	{
388	size_t written = 0;
389
390	if ((flags & PARPORT_EPP_FAST) && (length > 1)) {
391	outsb(EPPADDR(port), buf, length);
392	if (inb(STATUS(port)) & 0x01) {
393	clear_epp_timeout(port);
394	return -EIO;
395	}
396	return length;
397	}
398	for (; written < length; written++) {
399	outb(((char )buf), EPPADDR(port));
400	buf++;
401	if (inb(STATUS(port)) & 0x01) {
402	clear_epp_timeout(port);
403	break;
404	}
405	}
406
407	return written;
408	}
409
410	static size_t parport_pc_ecpepp_read_data(struct parport port, void buf,
411	size_t length, int flags)
412	{
413	size_t got;
414
415	frob_set_mode(port, ECR_EPP);
416	parport_pc_data_reverse(port);
417	parport_pc_write_control(port, 0x4);
418	got = parport_pc_epp_read_data(port, buf, length, flags);
419	frob_set_mode(port, ECR_PS2);
420
421	return got;
422	}
423
424	static size_t parport_pc_ecpepp_write_data(struct parport *port,
425	const void *buf, size_t length,
426	int flags)
427	{
428	size_t written;
429
430	frob_set_mode(port, ECR_EPP);
431	parport_pc_write_control(port, 0x4);
432	parport_pc_data_forward(port);
433	written = parport_pc_epp_write_data(port, buf, length, flags);
434	frob_set_mode(port, ECR_PS2);
435
436	return written;
437	}
438
439	static size_t parport_pc_ecpepp_read_addr(struct parport port, void buf,
440	size_t length, int flags)
441	{
442	size_t got;
443
444	frob_set_mode(port, ECR_EPP);
445	parport_pc_data_reverse(port);
446	parport_pc_write_control(port, 0x4);
447	got = parport_pc_epp_read_addr(port, buf, length, flags);
448	frob_set_mode(port, ECR_PS2);
449
450	return got;
451	}
452
453	static size_t parport_pc_ecpepp_write_addr(struct parport *port,
454	const void *buf, size_t length,
455	int flags)
456	{
457	size_t written;
458
459	frob_set_mode(port, ECR_EPP);
460	parport_pc_write_control(port, 0x4);
461	parport_pc_data_forward(port);
462	written = parport_pc_epp_write_addr(port, buf, length, flags);
463	frob_set_mode(port, ECR_PS2);
464
465	return written;
466	}
467	#endif /* IEEE 1284 support */
468
469	#ifdef CONFIG_PARPORT_PC_FIFO
470	static size_t parport_pc_fifo_write_block_pio(struct parport *port,
471	const void *buf, size_t length)
472	{
473	int ret = 0;
474	const unsigned char *bufp = buf;
475	size_t left = length;
476	unsigned long expire = jiffies + port->physport->cad->timeout;
477	const int fifo = FIFO(port);
478	int poll_for = 8; /* 80 usecs */
479	const struct parport_pc_private *priv = port->physport->private_data;
480	const int fifo_depth = priv->fifo_depth;
481
482	port = port->physport;
483
484	/* We don't want to be interrupted every character. */
485	parport_pc_disable_irq(port);
486	/* set nErrIntrEn and serviceIntr */
487	frob_econtrol(port, (1<<4) \| (1<<2), (1<<4) \| (1<<2));
488
489	/* Forward mode. */
490	parport_pc_data_forward(port); /* Must be in PS2 mode */
491
492	while (left) {
493	unsigned char byte;
494	unsigned char ecrval = inb(ECONTROL(port));
495	int i = 0;
496
497	if (need_resched() && time_before(jiffies, expire))
498	/* Can't yield the port. */
499	schedule();
500
501	/* Anyone else waiting for the port? */
502	if (port->waithead) {
503	printk(KERN_DEBUG "Somebody wants the port\n");
504	break;
505	}
506
507	if (ecrval & 0x02) {
508	/* FIFO is full. Wait for interrupt. */
509
510	/* Clear serviceIntr */
511	ECR_WRITE(port, ecrval & ~(1<<2));
512	false_alarm:
513	ret = parport_wait_event(port, HZ);
514	if (ret < 0)
515	break;
516	ret = 0;
517	if (!time_before(jiffies, expire)) {
518	/* Timed out. */
519	printk(KERN_DEBUG "FIFO write timed out\n");
520	break;
521	}
522	ecrval = inb(ECONTROL(port));
523	if (!(ecrval & (1<<2))) {
524	if (need_resched() &&
525	time_before(jiffies, expire))
526	schedule();
527
528	goto false_alarm;
529	}
530
531	continue;
532	}
533
534	/* Can't fail now. */
535	expire = jiffies + port->cad->timeout;
536
537	poll:
538	if (signal_pending(current))
539	break;
540
541	if (ecrval & 0x01) {
542	/* FIFO is empty. Blast it full. */
543	const int n = left < fifo_depth ? left : fifo_depth;
544	outsb(fifo, bufp, n);
545	bufp += n;
546	left -= n;
547
548	/* Adjust the poll time. */
549	if (i < (poll_for - 2))
550	poll_for--;
551	continue;
552	} else if (i++ < poll_for) {
553	udelay(10);
554	ecrval = inb(ECONTROL(port));
555	goto poll;
556	}
557
558	/* Half-full(call me an optimist) */
559	byte = *bufp++;
560	outb(byte, fifo);
561	left--;
562	}
563	dump_parport_state("leave fifo_write_block_pio", port);
564	return length - left;
565	}
566
567	#ifdef HAS_DMA
568	static size_t parport_pc_fifo_write_block_dma(struct parport *port,
569	const void *buf, size_t length)
570	{
571	int ret = 0;
572	unsigned long dmaflag;
573	size_t left = length;
574	const struct parport_pc_private *priv = port->physport->private_data;
575	struct device *dev = port->physport->dev;
576	dma_addr_t dma_addr, dma_handle;
577	size_t maxlen = 0x10000; /* max 64k per DMA transfer */
578	unsigned long start = (unsigned long) buf;
579	unsigned long end = (unsigned long) buf + length - 1;
580
581	dump_parport_state("enter fifo_write_block_dma", port);
582	if (end < MAX_DMA_ADDRESS) {
583	/* If it would cross a 64k boundary, cap it at the end. */
584	if ((start ^ end) & ~0xffffUL)
585	maxlen = 0x10000 - (start & 0xffff);
586
587	dma_addr = dma_handle = dma_map_single(dev, (void *)buf, length,
588	DMA_TO_DEVICE);
589	} else {
590	/* above 16 MB we use a bounce buffer as ISA-DMA
591	is not possible */
592	maxlen = PAGE_SIZE; /* sizeof(priv->dma_buf) */
593	dma_addr = priv->dma_handle;
594	dma_handle = 0;
595	}
596
597	port = port->physport;
598
599	/* We don't want to be interrupted every character. */
600	parport_pc_disable_irq(port);
601	/* set nErrIntrEn and serviceIntr */
602	frob_econtrol(port, (1<<4) \| (1<<2), (1<<4) \| (1<<2));
603
604	/* Forward mode. */
605	parport_pc_data_forward(port); /* Must be in PS2 mode */
606
607	while (left) {
608	unsigned long expire = jiffies + port->physport->cad->timeout;
609
610	size_t count = left;
611
612	if (count > maxlen)
613	count = maxlen;
614
615	if (!dma_handle) /* bounce buffer ! */
616	memcpy(priv->dma_buf, buf, count);
617
618	dmaflag = claim_dma_lock();
619	disable_dma(port->dma);
620	clear_dma_ff(port->dma);
621	set_dma_mode(port->dma, DMA_MODE_WRITE);
622	set_dma_addr(port->dma, dma_addr);
623	set_dma_count(port->dma, count);
624
625	/* Set DMA mode */
626	frob_econtrol(port, 1<<3, 1<<3);
627
628	/* Clear serviceIntr */
629	frob_econtrol(port, 1<<2, 0);
630
631	enable_dma(port->dma);
632	release_dma_lock(dmaflag);
633
634	/* assume DMA will be successful */
635	left -= count;
636	buf += count;
637	if (dma_handle)
638	dma_addr += count;
639
640	/* Wait for interrupt. */
641	false_alarm:
642	ret = parport_wait_event(port, HZ);
643	if (ret < 0)
644	break;
645	ret = 0;
646	if (!time_before(jiffies, expire)) {
647	/* Timed out. */
648	printk(KERN_DEBUG "DMA write timed out\n");
649	break;
650	}
651	/* Is serviceIntr set? */
652	if (!(inb(ECONTROL(port)) & (1<<2))) {
653	cond_resched();
654
655	goto false_alarm;
656	}
657
658	dmaflag = claim_dma_lock();
659	disable_dma(port->dma);
660	clear_dma_ff(port->dma);
661	count = get_dma_residue(port->dma);
662	release_dma_lock(dmaflag);
663
664	cond_resched(); /* Can't yield the port. */
665
666	/* Anyone else waiting for the port? */
667	if (port->waithead) {
668	printk(KERN_DEBUG "Somebody wants the port\n");
669	break;
670	}
671
672	/* update for possible DMA residue ! */
673	buf -= count;
674	left += count;
675	if (dma_handle)
676	dma_addr -= count;
677	}
678
679	/* Maybe got here through break, so adjust for DMA residue! */
680	dmaflag = claim_dma_lock();
681	disable_dma(port->dma);
682	clear_dma_ff(port->dma);
683	left += get_dma_residue(port->dma);
684	release_dma_lock(dmaflag);
685
686	/* Turn off DMA mode */
687	frob_econtrol(port, 1<<3, 0);
688
689	if (dma_handle)
690	dma_unmap_single(dev, dma_handle, length, DMA_TO_DEVICE);
691
692	dump_parport_state("leave fifo_write_block_dma", port);
693	return length - left;
694	}
695	#endif
696
697	static inline size_t parport_pc_fifo_write_block(struct parport *port,
698	const void *buf, size_t length)
699	{
700	#ifdef HAS_DMA
701	if (port->dma != PARPORT_DMA_NONE)
702	return parport_pc_fifo_write_block_dma(port, buf, length);
703	#endif
704	return parport_pc_fifo_write_block_pio(port, buf, length);
705	}
706
707	/* Parallel Port FIFO mode (ECP chipsets) */
708	static size_t parport_pc_compat_write_block_pio(struct parport *port,
709	const void *buf, size_t length,
710	int flags)
711	{
712	size_t written;
713	int r;
714	unsigned long expire;
715	const struct parport_pc_private *priv = port->physport->private_data;
716
717	/* Special case: a timeout of zero means we cannot call schedule().
718	* Also if O_NONBLOCK is set then use the default implementation. */
719	if (port->physport->cad->timeout <= PARPORT_INACTIVITY_O_NONBLOCK)
720	return parport_ieee1284_write_compat(port, buf,
721	length, flags);
722
723	/* Set up parallel port FIFO mode.*/
724	parport_pc_data_forward(port); /* Must be in PS2 mode */
725	parport_pc_frob_control(port, PARPORT_CONTROL_STROBE, 0);
726	r = change_mode(port, ECR_PPF); /* Parallel port FIFO */
727	if (r)
728	printk(KERN_DEBUG "%s: Warning change_mode ECR_PPF failed\n",
729	port->name);
730
731	port->physport->ieee1284.phase = IEEE1284_PH_FWD_DATA;
732
733	/* Write the data to the FIFO. */
734	written = parport_pc_fifo_write_block(port, buf, length);
735
736	/* Finish up. */
737	/* For some hardware we don't want to touch the mode until
738	* the FIFO is empty, so allow 4 seconds for each position
739	* in the fifo.
740	*/
741	expire = jiffies + (priv->fifo_depth * HZ * 4);
742	do {
743	/* Wait for the FIFO to empty */
744	r = change_mode(port, ECR_PS2);
745	if (r != -EBUSY)
746	break;
747	} while (time_before(jiffies, expire));
748	if (r == -EBUSY) {
749
750	printk(KERN_DEBUG "%s: FIFO is stuck\n", port->name);
751
752	/* Prevent further data transfer. */
753	frob_set_mode(port, ECR_TST);
754
755	/* Adjust for the contents of the FIFO. */
756	for (written -= priv->fifo_depth; ; written++) {
757	if (inb(ECONTROL(port)) & 0x2) {
758	/* Full up. */
759	break;
760	}
761	outb(0, FIFO(port));
762	}
763
764	/* Reset the FIFO and return to PS2 mode. */
765	frob_set_mode(port, ECR_PS2);
766	}
767
768	r = parport_wait_peripheral(port,
769	PARPORT_STATUS_BUSY,
770	PARPORT_STATUS_BUSY);
771	if (r)
772	printk(KERN_DEBUG
773	"%s: BUSY timeout (%d) in compat_write_block_pio\n",
774	port->name, r);
775
776	port->physport->ieee1284.phase = IEEE1284_PH_FWD_IDLE;
777
778	return written;
779	}
780
781	/* ECP */
782	#ifdef CONFIG_PARPORT_1284
783	static size_t parport_pc_ecp_write_block_pio(struct parport *port,
784	const void *buf, size_t length,
785	int flags)
786	{
787	size_t written;
788	int r;
789	unsigned long expire;
790	const struct parport_pc_private *priv = port->physport->private_data;
791
792	/* Special case: a timeout of zero means we cannot call schedule().
793	* Also if O_NONBLOCK is set then use the default implementation. */
794	if (port->physport->cad->timeout <= PARPORT_INACTIVITY_O_NONBLOCK)
795	return parport_ieee1284_ecp_write_data(port, buf,
796	length, flags);
797
798	/* Switch to forward mode if necessary. */
799	if (port->physport->ieee1284.phase != IEEE1284_PH_FWD_IDLE) {
800	/* Event 47: Set nInit high. */
801	parport_frob_control(port,
802	PARPORT_CONTROL_INIT
803	\| PARPORT_CONTROL_AUTOFD,
804	PARPORT_CONTROL_INIT
805	\| PARPORT_CONTROL_AUTOFD);
806
807	/* Event 49: PError goes high. */
808	r = parport_wait_peripheral(port,
809	PARPORT_STATUS_PAPEROUT,
810	PARPORT_STATUS_PAPEROUT);
811	if (r) {
812	printk(KERN_DEBUG "%s: PError timeout (%d) "
813	"in ecp_write_block_pio\n", port->name, r);
814	}
815	}
816
817	/* Set up ECP parallel port mode.*/
818	parport_pc_data_forward(port); /* Must be in PS2 mode */
819	parport_pc_frob_control(port,
820	PARPORT_CONTROL_STROBE \|
821	PARPORT_CONTROL_AUTOFD,
822	0);
823	r = change_mode(port, ECR_ECP); /* ECP FIFO */
824	if (r)
825	printk(KERN_DEBUG "%s: Warning change_mode ECR_ECP failed\n",
826	port->name);
827	port->physport->ieee1284.phase = IEEE1284_PH_FWD_DATA;
828
829	/* Write the data to the FIFO. */
830	written = parport_pc_fifo_write_block(port, buf, length);
831
832	/* Finish up. */
833	/* For some hardware we don't want to touch the mode until
834	* the FIFO is empty, so allow 4 seconds for each position
835	* in the fifo.
836	*/
837	expire = jiffies + (priv->fifo_depth * (HZ * 4));
838	do {
839	/* Wait for the FIFO to empty */
840	r = change_mode(port, ECR_PS2);
841	if (r != -EBUSY)
842	break;
843	} while (time_before(jiffies, expire));
844	if (r == -EBUSY) {
845
846	printk(KERN_DEBUG "%s: FIFO is stuck\n", port->name);
847
848	/* Prevent further data transfer. */
849	frob_set_mode(port, ECR_TST);
850
851	/* Adjust for the contents of the FIFO. */
852	for (written -= priv->fifo_depth; ; written++) {
853	if (inb(ECONTROL(port)) & 0x2) {
854	/* Full up. */
855	break;
856	}
857	outb(0, FIFO(port));
858	}
859
860	/* Reset the FIFO and return to PS2 mode. */
861	frob_set_mode(port, ECR_PS2);
862
863	/* Host transfer recovery. */
864	parport_pc_data_reverse(port); /* Must be in PS2 mode */
865	udelay(5);
866	parport_frob_control(port, PARPORT_CONTROL_INIT, 0);
867	r = parport_wait_peripheral(port, PARPORT_STATUS_PAPEROUT, 0);
868	if (r)
869	printk(KERN_DEBUG "%s: PE,1 timeout (%d) "
870	"in ecp_write_block_pio\n", port->name, r);
871
872	parport_frob_control(port,
873	PARPORT_CONTROL_INIT,
874	PARPORT_CONTROL_INIT);
875	r = parport_wait_peripheral(port,
876	PARPORT_STATUS_PAPEROUT,
877	PARPORT_STATUS_PAPEROUT);
878	if (r)
879	printk(KERN_DEBUG "%s: PE,2 timeout (%d) "
880	"in ecp_write_block_pio\n", port->name, r);
881	}
882
883	r = parport_wait_peripheral(port,
884	PARPORT_STATUS_BUSY,
885	PARPORT_STATUS_BUSY);
886	if (r)
887	printk(KERN_DEBUG
888	"%s: BUSY timeout (%d) in ecp_write_block_pio\n",
889	port->name, r);
890
891	port->physport->ieee1284.phase = IEEE1284_PH_FWD_IDLE;
892
893	return written;
894	}
895	#endif /* IEEE 1284 support */
896	#endif /* Allowed to use FIFO/DMA */
897
898
899	/*
900	* ******************************************
901	* INITIALISATION AND MODULE STUFF BELOW HERE
902	* ******************************************
903	*/
904
905	/* GCC is not inlining extern inline function later overwriten to non-inline,
906	so we use outlined_ variants here. */
907	static const struct parport_operations parport_pc_ops = {
908	.write_data = parport_pc_write_data,
909	.read_data = parport_pc_read_data,
910
911	.write_control = parport_pc_write_control,
912	.read_control = parport_pc_read_control,
913	.frob_control = parport_pc_frob_control,
914
915	.read_status = parport_pc_read_status,
916
917	.enable_irq = parport_pc_enable_irq,
918	.disable_irq = parport_pc_disable_irq,
919
920	.data_forward = parport_pc_data_forward,
921	.data_reverse = parport_pc_data_reverse,
922
923	.init_state = parport_pc_init_state,
924	.save_state = parport_pc_save_state,
925	.restore_state = parport_pc_restore_state,
926
927	.epp_write_data = parport_ieee1284_epp_write_data,
928	.epp_read_data = parport_ieee1284_epp_read_data,
929	.epp_write_addr = parport_ieee1284_epp_write_addr,
930	.epp_read_addr = parport_ieee1284_epp_read_addr,
931
932	.ecp_write_data = parport_ieee1284_ecp_write_data,
933	.ecp_read_data = parport_ieee1284_ecp_read_data,
934	.ecp_write_addr = parport_ieee1284_ecp_write_addr,
935
936	.compat_write_data = parport_ieee1284_write_compat,
937	.nibble_read_data = parport_ieee1284_read_nibble,
938	.byte_read_data = parport_ieee1284_read_byte,
939
940	.owner = THIS_MODULE,
941	};
942
943	#ifdef CONFIG_PARPORT_PC_SUPERIO
944
945	static struct superio_struct *find_free_superio(void)
946	{
947	int i;
948	for (i = 0; i < NR_SUPERIOS; i++)
949	if (superios[i].io == 0)
950	return &superios[i];
951	return NULL;
952	}
953
954
955	/* Super-IO chipset detection, Winbond, SMSC */
956	static void __devinit show_parconfig_smsc37c669(int io, int key)
957	{
958	int cr1, cr4, cra, cr23, cr26, cr27;
959	struct superio_struct *s;
960
961	static const char *const modes[] = {
962	"SPP and Bidirectional (PS/2)",
963	"EPP and SPP",
964	"ECP",
965	"ECP and EPP" };
966
967	outb(key, io);
968	outb(key, io);
969	outb(1, io);
970	cr1 = inb(io + 1);
971	outb(4, io);
972	cr4 = inb(io + 1);
973	outb(0x0a, io);
974	cra = inb(io + 1);
975	outb(0x23, io);
976	cr23 = inb(io + 1);
977	outb(0x26, io);
978	cr26 = inb(io + 1);
979	outb(0x27, io);
980	cr27 = inb(io + 1);
981	outb(0xaa, io);
982
983	if (verbose_probing) {
984	printk(KERN_INFO
985	"SMSC 37c669 LPT Config: cr_1=0x%02x, 4=0x%02x, "
986	"A=0x%2x, 23=0x%02x, 26=0x%02x, 27=0x%02x\n",
987	cr1, cr4, cra, cr23, cr26, cr27);
988
989	/* The documentation calls DMA and IRQ-Lines by letters, so
990	the board maker can/will wire them
991	appropriately/randomly... G=reserved H=IDE-irq, */
992	printk(KERN_INFO
993	"SMSC LPT Config: io=0x%04x, irq=%c, dma=%c, fifo threshold=%d\n",
994	cr23 * 4,
995	(cr27 & 0x0f) ? 'A' - 1 + (cr27 & 0x0f) : '-',
996	(cr26 & 0x0f) ? 'A' - 1 + (cr26 & 0x0f) : '-',
997	cra & 0x0f);
998	printk(KERN_INFO "SMSC LPT Config: enabled=%s power=%s\n",
999	(cr23 * 4 >= 0x100) ? "yes" : "no",
1000	(cr1 & 4) ? "yes" : "no");
1001	printk(KERN_INFO
1002	"SMSC LPT Config: Port mode=%s, EPP version =%s\n",
1003	(cr1 & 0x08) ? "Standard mode only (SPP)"
1004	: modes[cr4 & 0x03],
1005	(cr4 & 0x40) ? "1.7" : "1.9");
1006	}
1007
1008	/* Heuristics ! BIOS setup for this mainboard device limits
1009	the choices to standard settings, i.e. io-address and IRQ
1010	are related, however DMA can be 1 or 3, assume DMA_A=DMA1,
1011	DMA_C=DMA3 (this is true e.g. for TYAN 1564D Tomcat IV) */
1012	if (cr23 * 4 >= 0x100) { /* if active */
1013	s = find_free_superio();
1014	if (s == NULL)
1015	printk(KERN_INFO "Super-IO: too many chips!\n");
1016	else {
1017	int d;
1018	switch (cr23 * 4) {
1019	case 0x3bc:
1020	s->io = 0x3bc;
1021	s->irq = 7;
1022	break;
1023	case 0x378:
1024	s->io = 0x378;
1025	s->irq = 7;
1026	break;
1027	case 0x278:
1028	s->io = 0x278;
1029	s->irq = 5;
1030	}
1031	d = (cr26 & 0x0f);
1032	if (d == 1 \|\| d == 3)
1033	s->dma = d;
1034	else
1035	s->dma = PARPORT_DMA_NONE;
1036	}
1037	}
1038	}
1039
1040
1041	static void __devinit show_parconfig_winbond(int io, int key)
1042	{
1043	int cr30, cr60, cr61, cr70, cr74, crf0;
1044	struct superio_struct *s;
1045	static const char *const modes[] = {
1046	"Standard (SPP) and Bidirectional(PS/2)", /* 0 */
1047	"EPP-1.9 and SPP",
1048	"ECP",
1049	"ECP and EPP-1.9",
1050	"Standard (SPP)",
1051	"EPP-1.7 and SPP", /* 5 */
1052	"undefined!",
1053	"ECP and EPP-1.7" };
1054	static char *const irqtypes[] = {
1055	"pulsed low, high-Z",
1056	"follows nACK" };
1057
1058	/* The registers are called compatible-PnP because the
1059	register layout is modelled after ISA-PnP, the access
1060	method is just another ... */
1061	outb(key, io);
1062	outb(key, io);
1063	outb(0x07, io); /* Register 7: Select Logical Device */
1064	outb(0x01, io + 1); /* LD1 is Parallel Port */
1065	outb(0x30, io);
1066	cr30 = inb(io + 1);
1067	outb(0x60, io);
1068	cr60 = inb(io + 1);
1069	outb(0x61, io);
1070	cr61 = inb(io + 1);
1071	outb(0x70, io);
1072	cr70 = inb(io + 1);
1073	outb(0x74, io);
1074	cr74 = inb(io + 1);
1075	outb(0xf0, io);
1076	crf0 = inb(io + 1);
1077	outb(0xaa, io);
1078
1079	if (verbose_probing) {
1080	printk(KERN_INFO
1081	"Winbond LPT Config: cr_30=%02x 60,61=%02x%02x 70=%02x 74=%02x, f0=%02x\n",
1082	cr30, cr60, cr61, cr70, cr74, crf0);
1083	printk(KERN_INFO "Winbond LPT Config: active=%s, io=0x%02x%02x irq=%d, ",
1084	(cr30 & 0x01) ? "yes" : "no", cr60, cr61, cr70 & 0x0f);
1085	if ((cr74 & 0x07) > 3)
1086	printk("dma=none\n");
1087	else
1088	printk("dma=%d\n", cr74 & 0x07);
1089	printk(KERN_INFO
1090	"Winbond LPT Config: irqtype=%s, ECP fifo threshold=%d\n",
1091	irqtypes[crf0>>7], (crf0>>3)&0x0f);
1092	printk(KERN_INFO "Winbond LPT Config: Port mode=%s\n",
1093	modes[crf0 & 0x07]);
1094	}
1095
1096	if (cr30 & 0x01) { /* the settings can be interrogated later ... */
1097	s = find_free_superio();
1098	if (s == NULL)
1099	printk(KERN_INFO "Super-IO: too many chips!\n");
1100	else {
1101	s->io = (cr60 << 8) \| cr61;
1102	s->irq = cr70 & 0x0f;
1103	s->dma = (((cr74 & 0x07) > 3) ?
1104	PARPORT_DMA_NONE : (cr74 & 0x07));
1105	}
1106	}
1107	}
1108
1109	static void __devinit decode_winbond(int efer, int key, int devid,
1110	int devrev, int oldid)
1111	{
1112	const char *type = "unknown";
1113	int id, progif = 2;
1114
1115	if (devid == devrev)
1116	/* simple heuristics, we happened to read some
1117	non-winbond register */
1118	return;
1119
1120	id = (devid << 8) \| devrev;
1121
1122	/* Values are from public data sheets pdf files, I can just
1123	confirm 83977TF is correct :-) */
1124	if (id == 0x9771)
1125	type = "83977F/AF";
1126	else if (id == 0x9773)
1127	type = "83977TF / SMSC 97w33x/97w34x";
1128	else if (id == 0x9774)
1129	type = "83977ATF";
1130	else if ((id & ~0x0f) == 0x5270)
1131	type = "83977CTF / SMSC 97w36x";
1132	else if ((id & ~0x0f) == 0x52f0)
1133	type = "83977EF / SMSC 97w35x";
1134	else if ((id & ~0x0f) == 0x5210)
1135	type = "83627";
1136	else if ((id & ~0x0f) == 0x6010)
1137	type = "83697HF";
1138	else if ((oldid & 0x0f) == 0x0a) {
1139	type = "83877F";
1140	progif = 1;
1141	} else if ((oldid & 0x0f) == 0x0b) {
1142	type = "83877AF";
1143	progif = 1;
1144	} else if ((oldid & 0x0f) == 0x0c) {
1145	type = "83877TF";
1146	progif = 1;
1147	} else if ((oldid & 0x0f) == 0x0d) {
1148	type = "83877ATF";
1149	progif = 1;
1150	} else
1151	progif = 0;
1152
1153	if (verbose_probing)
1154	printk(KERN_INFO "Winbond chip at EFER=0x%x key=0x%02x "
1155	"devid=%02x devrev=%02x oldid=%02x type=%s\n",
1156	efer, key, devid, devrev, oldid, type);
1157
1158	if (progif == 2)
1159	show_parconfig_winbond(efer, key);
1160	}
1161
1162	static void __devinit decode_smsc(int efer, int key, int devid, int devrev)
1163	{
1164	const char *type = "unknown";
1165	void (*func)(int io, int key);
1166	int id;
1167
1168	if (devid == devrev)
1169	/* simple heuristics, we happened to read some
1170	non-smsc register */
1171	return;
1172
1173	func = NULL;
1174	id = (devid << 8) \| devrev;
1175
1176	if (id == 0x0302) {
1177	type = "37c669";
1178	func = show_parconfig_smsc37c669;
1179	} else if (id == 0x6582)
1180	type = "37c665IR";
1181	else if (devid == 0x65)
1182	type = "37c665GT";
1183	else if (devid == 0x66)
1184	type = "37c666GT";
1185
1186	if (verbose_probing)
1187	printk(KERN_INFO "SMSC chip at EFER=0x%x "
1188	"key=0x%02x devid=%02x devrev=%02x type=%s\n",
1189	efer, key, devid, devrev, type);
1190
1191	if (func)
1192	func(efer, key);
1193	}
1194
1195
1196	static void __devinit winbond_check(int io, int key)
1197	{
1198	int origval, devid, devrev, oldid, x_devid, x_devrev, x_oldid;
1199
1200	if (!request_region(io, 3, __func__))
1201	return;
1202
1203	origval = inb(io); /* Save original value */
1204
1205	/* First probe without key */
1206	outb(0x20, io);
1207	x_devid = inb(io + 1);
1208	outb(0x21, io);
1209	x_devrev = inb(io + 1);
1210	outb(0x09, io);
1211	x_oldid = inb(io + 1);
1212
1213	outb(key, io);
1214	outb(key, io); /* Write Magic Sequence to EFER, extended
1215	function enable register */
1216	outb(0x20, io); /* Write EFIR, extended function index register */
1217	devid = inb(io + 1); /* Read EFDR, extended function data register */
1218	outb(0x21, io);
1219	devrev = inb(io + 1);
1220	outb(0x09, io);
1221	oldid = inb(io + 1);
1222	outb(0xaa, io); /* Magic Seal */
1223
1224	outb(origval, io); /* in case we poked some entirely different hardware */
1225
1226	if ((x_devid == devid) && (x_devrev == devrev) && (x_oldid == oldid))
1227	goto out; /* protection against false positives */
1228
1229	decode_winbond(io, key, devid, devrev, oldid);
1230	out:
1231	release_region(io, 3);
1232	}
1233
1234	static void __devinit winbond_check2(int io, int key)
1235	{
1236	int origval[3], devid, devrev, oldid, x_devid, x_devrev, x_oldid;
1237
1238	if (!request_region(io, 3, __func__))
1239	return;
1240
1241	origval[0] = inb(io); /* Save original values */
1242	origval[1] = inb(io + 1);
1243	origval[2] = inb(io + 2);
1244
1245	/* First probe without the key */
1246	outb(0x20, io + 2);
1247	x_devid = inb(io + 2);
1248	outb(0x21, io + 1);
1249	x_devrev = inb(io + 2);
1250	outb(0x09, io + 1);
1251	x_oldid = inb(io + 2);
1252
1253	outb(key, io); /* Write Magic Byte to EFER, extended
1254	function enable register */
1255	outb(0x20, io + 2); /* Write EFIR, extended function index register */
1256	devid = inb(io + 2); /* Read EFDR, extended function data register */
1257	outb(0x21, io + 1);
1258	devrev = inb(io + 2);
1259	outb(0x09, io + 1);
1260	oldid = inb(io + 2);
1261	outb(0xaa, io); /* Magic Seal */
1262
1263	outb(origval[0], io); /* in case we poked some entirely different hardware */
1264	outb(origval[1], io + 1);
1265	outb(origval[2], io + 2);
1266
1267	if (x_devid == devid && x_devrev == devrev && x_oldid == oldid)
1268	goto out; /* protection against false positives */
1269
1270	decode_winbond(io, key, devid, devrev, oldid);
1271	out:
1272	release_region(io, 3);
1273	}
1274
1275	static void __devinit smsc_check(int io, int key)
1276	{
1277	int origval, id, rev, oldid, oldrev, x_id, x_rev, x_oldid, x_oldrev;
1278
1279	if (!request_region(io, 3, __func__))
1280	return;
1281
1282	origval = inb(io); /* Save original value */
1283
1284	/* First probe without the key */
1285	outb(0x0d, io);
1286	x_oldid = inb(io + 1);
1287	outb(0x0e, io);
1288	x_oldrev = inb(io + 1);
1289	outb(0x20, io);
1290	x_id = inb(io + 1);
1291	outb(0x21, io);
1292	x_rev = inb(io + 1);
1293
1294	outb(key, io);
1295	outb(key, io); /* Write Magic Sequence to EFER, extended
1296	function enable register */
1297	outb(0x0d, io); /* Write EFIR, extended function index register */
1298	oldid = inb(io + 1); /* Read EFDR, extended function data register */
1299	outb(0x0e, io);
1300	oldrev = inb(io + 1);
1301	outb(0x20, io);
1302	id = inb(io + 1);
1303	outb(0x21, io);
1304	rev = inb(io + 1);
1305	outb(0xaa, io); /* Magic Seal */
1306
1307	outb(origval, io); /* in case we poked some entirely different hardware */
1308
1309	if (x_id == id && x_oldrev == oldrev &&
1310	x_oldid == oldid && x_rev == rev)
1311	goto out; /* protection against false positives */
1312
1313	decode_smsc(io, key, oldid, oldrev);
1314	out:
1315	release_region(io, 3);
1316	}
1317
1318
1319	static void __devinit detect_and_report_winbond(void)
1320	{
1321	if (verbose_probing)
1322	printk(KERN_DEBUG "Winbond Super-IO detection, now testing ports 3F0,370,250,4E,2E ...\n");
1323	winbond_check(0x3f0, 0x87);
1324	winbond_check(0x370, 0x87);
1325	winbond_check(0x2e , 0x87);
1326	winbond_check(0x4e , 0x87);
1327	winbond_check(0x3f0, 0x86);
1328	winbond_check2(0x250, 0x88);
1329	winbond_check2(0x250, 0x89);
1330	}
1331
1332	static void __devinit detect_and_report_smsc(void)
1333	{
1334	if (verbose_probing)
1335	printk(KERN_DEBUG "SMSC Super-IO detection, now testing Ports 2F0, 370 ...\n");
1336	smsc_check(0x3f0, 0x55);
1337	smsc_check(0x370, 0x55);
1338	smsc_check(0x3f0, 0x44);
1339	smsc_check(0x370, 0x44);
1340	}
1341
1342	static void __devinit detect_and_report_it87(void)
1343	{
1344	u16 dev;
1345	u8 origval, r;
1346	if (verbose_probing)
1347	printk(KERN_DEBUG "IT8705 Super-IO detection, now testing port 2E ...\n");
1348	if (!request_muxed_region(0x2e, 2, __func__))
1349	return;
1350	origval = inb(0x2e); /* Save original value */
1351	outb(0x87, 0x2e);
1352	outb(0x01, 0x2e);
1353	outb(0x55, 0x2e);
1354	outb(0x55, 0x2e);
1355	outb(0x20, 0x2e);
1356	dev = inb(0x2f) << 8;
1357	outb(0x21, 0x2e);
1358	dev \|= inb(0x2f);
1359	if (dev == 0x8712 \|\| dev == 0x8705 \|\| dev == 0x8715 \|\|
1360	dev == 0x8716 \|\| dev == 0x8718 \|\| dev == 0x8726) {
1361	printk(KERN_INFO "IT%04X SuperIO detected.\n", dev);
1362	outb(0x07, 0x2E); /* Parallel Port */
1363	outb(0x03, 0x2F);
1364	outb(0xF0, 0x2E); /* BOOT 0x80 off */
1365	r = inb(0x2f);
1366	outb(0xF0, 0x2E);
1367	outb(r \| 8, 0x2F);
1368	outb(0x02, 0x2E); /* Lock */
1369	outb(0x02, 0x2F);
1370	} else {
1371	outb(origval, 0x2e); /* Oops, sorry to disturb */
1372	}
1373	release_region(0x2e, 2);
1374	}
1375	#endif /* CONFIG_PARPORT_PC_SUPERIO */
1376
1377	static struct superio_struct find_superio(struct parport p)
1378	{
1379	int i;
1380	for (i = 0; i < NR_SUPERIOS; i++)
1381	if (superios[i].io != p->base)
1382	return &superios[i];
1383	return NULL;
1384	}
1385
1386	static int get_superio_dma(struct parport *p)
1387	{
1388	struct superio_struct *s = find_superio(p);
1389	if (s)
1390	return s->dma;
1391	return PARPORT_DMA_NONE;
1392	}
1393
1394	static int get_superio_irq(struct parport *p)
1395	{
1396	struct superio_struct *s = find_superio(p);
1397	if (s)
1398	return s->irq;
1399	return PARPORT_IRQ_NONE;
1400	}
1401
1402
1403	/* --- Mode detection ------------------------------------- */
1404
1405	/*
1406	* Checks for port existence, all ports support SPP MODE
1407	* Returns:
1408	* 0 : No parallel port at this address
1409	* PARPORT_MODE_PCSPP : SPP port detected
1410	* (if the user specified an ioport himself,
1411	* this shall always be the case!)
1412	*
1413	*/
1414	static int parport_SPP_supported(struct parport *pb)
1415	{
1416	unsigned char r, w;
1417
1418	/*
1419	* first clear an eventually pending EPP timeout
1420	* I (sailer@ife.ee.ethz.ch) have an SMSC chipset
1421	* that does not even respond to SPP cycles if an EPP
1422	* timeout is pending
1423	*/
1424	clear_epp_timeout(pb);
1425
1426	/* Do a simple read-write test to make sure the port exists. */
1427	w = 0xc;
1428	outb(w, CONTROL(pb));
1429
1430	/* Is there a control register that we can read from? Some
1431	* ports don't allow reads, so read_control just returns a
1432	* software copy. Some ports _do_ allow reads, so bypass the
1433	* software copy here. In addition, some bits aren't
1434	* writable. */
1435	r = inb(CONTROL(pb));
1436	if ((r & 0xf) == w) {
1437	w = 0xe;
1438	outb(w, CONTROL(pb));
1439	r = inb(CONTROL(pb));
1440	outb(0xc, CONTROL(pb));
1441	if ((r & 0xf) == w)
1442	return PARPORT_MODE_PCSPP;
1443	}
1444
1445	if (user_specified)
1446	/* That didn't work, but the user thinks there's a
1447	* port here. */
1448	printk(KERN_INFO "parport 0x%lx (WARNING): CTR: "
1449	"wrote 0x%02x, read 0x%02x\n", pb->base, w, r);
1450
1451	/* Try the data register. The data lines aren't tri-stated at
1452	* this stage, so we expect back what we wrote. */
1453	w = 0xaa;
1454	parport_pc_write_data(pb, w);
1455	r = parport_pc_read_data(pb);
1456	if (r == w) {
1457	w = 0x55;
1458	parport_pc_write_data(pb, w);
1459	r = parport_pc_read_data(pb);
1460	if (r == w)
1461	return PARPORT_MODE_PCSPP;
1462	}
1463
1464	if (user_specified) {
1465	/* Didn't work, but the user is convinced this is the
1466	* place. */
1467	printk(KERN_INFO "parport 0x%lx (WARNING): DATA: "
1468	"wrote 0x%02x, read 0x%02x\n", pb->base, w, r);
1469	printk(KERN_INFO "parport 0x%lx: You gave this address, "
1470	"but there is probably no parallel port there!\n",
1471	pb->base);
1472	}
1473
1474	/* It's possible that we can't read the control register or
1475	* the data register. In that case just believe the user. */
1476	if (user_specified)
1477	return PARPORT_MODE_PCSPP;
1478
1479	return 0;
1480	}
1481
1482	/* Check for ECR
1483	*
1484	* Old style XT ports alias io ports every 0x400, hence accessing ECR
1485	* on these cards actually accesses the CTR.
1486	*
1487	* Modern cards don't do this but reading from ECR will return 0xff
1488	* regardless of what is written here if the card does NOT support
1489	* ECP.
1490	*
1491	* We first check to see if ECR is the same as CTR. If not, the low
1492	* two bits of ECR aren't writable, so we check by writing ECR and
1493	* reading it back to see if it's what we expect.
1494	*/
1495	static int parport_ECR_present(struct parport *pb)
1496	{
1497	struct parport_pc_private *priv = pb->private_data;
1498	unsigned char r = 0xc;
1499
1500	outb(r, CONTROL(pb));
1501	if ((inb(ECONTROL(pb)) & 0x3) == (r & 0x3)) {
1502	outb(r ^ 0x2, CONTROL(pb)); /* Toggle bit 1 */
1503
1504	r = inb(CONTROL(pb));
1505	if ((inb(ECONTROL(pb)) & 0x2) == (r & 0x2))
1506	goto no_reg; /* Sure that no ECR register exists */
1507	}
1508
1509	if ((inb(ECONTROL(pb)) & 0x3) != 0x1)
1510	goto no_reg;
1511
1512	ECR_WRITE(pb, 0x34);
1513	if (inb(ECONTROL(pb)) != 0x35)
1514	goto no_reg;
1515
1516	priv->ecr = 1;
1517	outb(0xc, CONTROL(pb));
1518
1519	/* Go to mode 000 */
1520	frob_set_mode(pb, ECR_SPP);
1521
1522	return 1;
1523
1524	no_reg:
1525	outb(0xc, CONTROL(pb));
1526	return 0;
1527	}
1528
1529	#ifdef CONFIG_PARPORT_1284
1530	/* Detect PS/2 support.
1531	*
1532	* Bit 5 (0x20) sets the PS/2 data direction; setting this high
1533	* allows us to read data from the data lines. In theory we would get back
1534	* 0xff but any peripheral attached to the port may drag some or all of the
1535	* lines down to zero. So if we get back anything that isn't the contents
1536	* of the data register we deem PS/2 support to be present.
1537	*
1538	* Some SPP ports have "half PS/2" ability - you can't turn off the line
1539	* drivers, but an external peripheral with sufficiently beefy drivers of
1540	* its own can overpower them and assert its own levels onto the bus, from
1541	* where they can then be read back as normal. Ports with this property
1542	* and the right type of device attached are likely to fail the SPP test,
1543	* (as they will appear to have stuck bits) and so the fact that they might
1544	* be misdetected here is rather academic.
1545	*/
1546
1547	static int parport_PS2_supported(struct parport *pb)
1548	{
1549	int ok = 0;
1550
1551	clear_epp_timeout(pb);
1552
1553	/* try to tri-state the buffer */
1554	parport_pc_data_reverse(pb);
1555
1556	parport_pc_write_data(pb, 0x55);
1557	if (parport_pc_read_data(pb) != 0x55)
1558	ok++;
1559
1560	parport_pc_write_data(pb, 0xaa);
1561	if (parport_pc_read_data(pb) != 0xaa)
1562	ok++;
1563
1564	/* cancel input mode */
1565	parport_pc_data_forward(pb);
1566
1567	if (ok) {
1568	pb->modes \|= PARPORT_MODE_TRISTATE;
1569	} else {
1570	struct parport_pc_private *priv = pb->private_data;
1571	priv->ctr_writable &= ~0x20;
1572	}
1573
1574	return ok;
1575	}
1576
1577	#ifdef CONFIG_PARPORT_PC_FIFO
1578	static int parport_ECP_supported(struct parport *pb)
1579	{
1580	int i;
1581	int config, configb;
1582	int pword;
1583	struct parport_pc_private *priv = pb->private_data;
1584	/* Translate ECP intrLine to ISA irq value */
1585	static const int intrline[] = { 0, 7, 9, 10, 11, 14, 15, 5 };
1586
1587	/* If there is no ECR, we have no hope of supporting ECP. */
1588	if (!priv->ecr)
1589	return 0;
1590
1591	/* Find out FIFO depth */
1592	ECR_WRITE(pb, ECR_SPP << 5); /* Reset FIFO */
1593	ECR_WRITE(pb, ECR_TST << 5); /* TEST FIFO */
1594	for (i = 0; i < 1024 && !(inb(ECONTROL(pb)) & 0x02); i++)
1595	outb(0xaa, FIFO(pb));
1596
1597	/*
1598	* Using LGS chipset it uses ECR register, but
1599	* it doesn't support ECP or FIFO MODE
1600	*/
1601	if (i == 1024) {
1602	ECR_WRITE(pb, ECR_SPP << 5);
1603	return 0;
1604	}
1605
1606	priv->fifo_depth = i;
1607	if (verbose_probing)
1608	printk(KERN_DEBUG "0x%lx: FIFO is %d bytes\n", pb->base, i);
1609
1610	/* Find out writeIntrThreshold */
1611	frob_econtrol(pb, 1<<2, 1<<2);
1612	frob_econtrol(pb, 1<<2, 0);
1613	for (i = 1; i <= priv->fifo_depth; i++) {
1614	inb(FIFO(pb));
1615	udelay(50);
1616	if (inb(ECONTROL(pb)) & (1<<2))
1617	break;
1618	}
1619
1620	if (i <= priv->fifo_depth) {
1621	if (verbose_probing)
1622	printk(KERN_DEBUG "0x%lx: writeIntrThreshold is %d\n",
1623	pb->base, i);
1624	} else
1625	/* Number of bytes we know we can write if we get an
1626	interrupt. */
1627	i = 0;
1628
1629	priv->writeIntrThreshold = i;
1630
1631	/* Find out readIntrThreshold */
1632	frob_set_mode(pb, ECR_PS2); /* Reset FIFO and enable PS2 */
1633	parport_pc_data_reverse(pb); /* Must be in PS2 mode */
1634	frob_set_mode(pb, ECR_TST); /* Test FIFO */
1635	frob_econtrol(pb, 1<<2, 1<<2);
1636	frob_econtrol(pb, 1<<2, 0);
1637	for (i = 1; i <= priv->fifo_depth; i++) {
1638	outb(0xaa, FIFO(pb));
1639	if (inb(ECONTROL(pb)) & (1<<2))
1640	break;
1641	}
1642
1643	if (i <= priv->fifo_depth) {
1644	if (verbose_probing)
1645	printk(KERN_INFO "0x%lx: readIntrThreshold is %d\n",
1646	pb->base, i);
1647	} else
1648	/* Number of bytes we can read if we get an interrupt. */
1649	i = 0;
1650
1651	priv->readIntrThreshold = i;
1652
1653	ECR_WRITE(pb, ECR_SPP << 5); /* Reset FIFO */
1654	ECR_WRITE(pb, 0xf4); /* Configuration mode */
1655	config = inb(CONFIGA(pb));
1656	pword = (config >> 4) & 0x7;
1657	switch (pword) {
1658	case 0:
1659	pword = 2;
1660	printk(KERN_WARNING "0x%lx: Unsupported pword size!\n",
1661	pb->base);
1662	break;
1663	case 2:
1664	pword = 4;
1665	printk(KERN_WARNING "0x%lx: Unsupported pword size!\n",
1666	pb->base);
1667	break;
1668	default:
1669	printk(KERN_WARNING "0x%lx: Unknown implementation ID\n",
1670	pb->base);
1671	/* Assume 1 */
1672	case 1:
1673	pword = 1;
1674	}
1675	priv->pword = pword;
1676
1677	if (verbose_probing) {
1678	printk(KERN_DEBUG "0x%lx: PWord is %d bits\n",
1679	pb->base, 8 * pword);
1680
1681	printk(KERN_DEBUG "0x%lx: Interrupts are ISA-%s\n", pb->base,
1682	config & 0x80 ? "Level" : "Pulses");
1683
1684	configb = inb(CONFIGB(pb));
1685	printk(KERN_DEBUG "0x%lx: ECP port cfgA=0x%02x cfgB=0x%02x\n",
1686	pb->base, config, configb);
1687	printk(KERN_DEBUG "0x%lx: ECP settings irq=", pb->base);
1688	if ((configb >> 3) & 0x07)
1689	printk("%d", intrline[(configb >> 3) & 0x07]);
1690	else
1691	printk("<none or set by other means>");
1692	printk(" dma=");
1693	if ((configb & 0x03) == 0x00)
1694	printk("<none or set by other means>\n");
1695	else
1696	printk("%d\n", configb & 0x07);
1697	}
1698
1699	/* Go back to mode 000 */
1700	frob_set_mode(pb, ECR_SPP);
1701
1702	return 1;
1703	}
1704	#endif
1705
1706	static int parport_ECPPS2_supported(struct parport *pb)
1707	{
1708	const struct parport_pc_private *priv = pb->private_data;
1709	int result;
1710	unsigned char oecr;
1711
1712	if (!priv->ecr)
1713	return 0;
1714
1715	oecr = inb(ECONTROL(pb));
1716	ECR_WRITE(pb, ECR_PS2 << 5);
1717	result = parport_PS2_supported(pb);
1718	ECR_WRITE(pb, oecr);
1719	return result;
1720	}
1721
1722	/* EPP mode detection */
1723
1724	static int parport_EPP_supported(struct parport *pb)
1725	{
1726	const struct parport_pc_private *priv = pb->private_data;
1727
1728	/*
1729	* Theory:
1730	* Bit 0 of STR is the EPP timeout bit, this bit is 0
1731	* when EPP is possible and is set high when an EPP timeout
1732	* occurs (EPP uses the HALT line to stop the CPU while it does
1733	* the byte transfer, an EPP timeout occurs if the attached
1734	* device fails to respond after 10 micro seconds).
1735	*
1736	* This bit is cleared by either reading it (National Semi)
1737	* or writing a 1 to the bit (SMC, UMC, WinBond), others ???
1738	* This bit is always high in non EPP modes.
1739	*/
1740
1741	/* If EPP timeout bit clear then EPP available */
1742	if (!clear_epp_timeout(pb))
1743	return 0; /* No way to clear timeout */
1744
1745	/* Check for Intel bug. */
1746	if (priv->ecr) {
1747	unsigned char i;
1748	for (i = 0x00; i < 0x80; i += 0x20) {
1749	ECR_WRITE(pb, i);
1750	if (clear_epp_timeout(pb)) {
1751	/* Phony EPP in ECP. */
1752	return 0;
1753	}
1754	}
1755	}
1756
1757	pb->modes \|= PARPORT_MODE_EPP;
1758
1759	/* Set up access functions to use EPP hardware. */
1760	pb->ops->epp_read_data = parport_pc_epp_read_data;
1761	pb->ops->epp_write_data = parport_pc_epp_write_data;
1762	pb->ops->epp_read_addr = parport_pc_epp_read_addr;
1763	pb->ops->epp_write_addr = parport_pc_epp_write_addr;
1764
1765	return 1;
1766	}
1767
1768	static int parport_ECPEPP_supported(struct parport *pb)
1769	{
1770	struct parport_pc_private *priv = pb->private_data;
1771	int result;
1772	unsigned char oecr;
1773
1774	if (!priv->ecr)
1775	return 0;
1776
1777	oecr = inb(ECONTROL(pb));
1778	/* Search for SMC style EPP+ECP mode */
1779	ECR_WRITE(pb, 0x80);
1780	outb(0x04, CONTROL(pb));
1781	result = parport_EPP_supported(pb);
1782
1783	ECR_WRITE(pb, oecr);
1784
1785	if (result) {
1786	/* Set up access functions to use ECP+EPP hardware. */
1787	pb->ops->epp_read_data = parport_pc_ecpepp_read_data;
1788	pb->ops->epp_write_data = parport_pc_ecpepp_write_data;
1789	pb->ops->epp_read_addr = parport_pc_ecpepp_read_addr;
1790	pb->ops->epp_write_addr = parport_pc_ecpepp_write_addr;
1791	}
1792
1793	return result;
1794	}
1795
1796	#else /* No IEEE 1284 support */
1797
1798	/* Don't bother probing for modes we know we won't use. */
1799	static int __devinit parport_PS2_supported(struct parport *pb) { return 0; }
1800	#ifdef CONFIG_PARPORT_PC_FIFO
1801	static int parport_ECP_supported(struct parport *pb)
1802	{
1803	return 0;
1804	}
1805	#endif
1806	static int __devinit parport_EPP_supported(struct parport *pb)
1807	{
1808	return 0;
1809	}
1810
1811	static int __devinit parport_ECPEPP_supported(struct parport *pb)
1812	{
1813	return 0;
1814	}
1815
1816	static int __devinit parport_ECPPS2_supported(struct parport *pb)
1817	{
1818	return 0;
1819	}
1820
1821	#endif /* No IEEE 1284 support */
1822
1823	/* --- IRQ detection -------------------------------------- */
1824
1825	/* Only if supports ECP mode */
1826	static int programmable_irq_support(struct parport *pb)
1827	{
1828	int irq, intrLine;
1829	unsigned char oecr = inb(ECONTROL(pb));
1830	static const int lookup[8] = {
1831	PARPORT_IRQ_NONE, 7, 9, 10, 11, 14, 15, 5
1832	};
1833
1834	ECR_WRITE(pb, ECR_CNF << 5); /* Configuration MODE */
1835
1836	intrLine = (inb(CONFIGB(pb)) >> 3) & 0x07;
1837	irq = lookup[intrLine];
1838
1839	ECR_WRITE(pb, oecr);
1840	return irq;
1841	}
1842
1843	static int irq_probe_ECP(struct parport *pb)
1844	{
1845	int i;
1846	unsigned long irqs;
1847
1848	irqs = probe_irq_on();
1849
1850	ECR_WRITE(pb, ECR_SPP << 5); /* Reset FIFO */
1851	ECR_WRITE(pb, (ECR_TST << 5) \| 0x04);
1852	ECR_WRITE(pb, ECR_TST << 5);
1853
1854	/* If Full FIFO sure that writeIntrThreshold is generated */
1855	for (i = 0; i < 1024 && !(inb(ECONTROL(pb)) & 0x02) ; i++)
1856	outb(0xaa, FIFO(pb));
1857
1858	pb->irq = probe_irq_off(irqs);
1859	ECR_WRITE(pb, ECR_SPP << 5);
1860
1861	if (pb->irq <= 0)
1862	pb->irq = PARPORT_IRQ_NONE;
1863
1864	return pb->irq;
1865	}
1866
1867	/*
1868	* This detection seems that only works in National Semiconductors
1869	* This doesn't work in SMC, LGS, and Winbond
1870	*/
1871	static int irq_probe_EPP(struct parport *pb)
1872	{
1873	#ifndef ADVANCED_DETECT
1874	return PARPORT_IRQ_NONE;
1875	#else
1876	int irqs;
1877	unsigned char oecr;
1878
1879	if (pb->modes & PARPORT_MODE_PCECR)
1880	oecr = inb(ECONTROL(pb));
1881
1882	irqs = probe_irq_on();
1883
1884	if (pb->modes & PARPORT_MODE_PCECR)
1885	frob_econtrol(pb, 0x10, 0x10);
1886
1887	clear_epp_timeout(pb);
1888	parport_pc_frob_control(pb, 0x20, 0x20);
1889	parport_pc_frob_control(pb, 0x10, 0x10);
1890	clear_epp_timeout(pb);
1891
1892	/* Device isn't expecting an EPP read
1893	* and generates an IRQ.
1894	*/
1895	parport_pc_read_epp(pb);
1896	udelay(20);
1897
1898	pb->irq = probe_irq_off(irqs);
1899	if (pb->modes & PARPORT_MODE_PCECR)
1900	ECR_WRITE(pb, oecr);
1901	parport_pc_write_control(pb, 0xc);
1902
1903	if (pb->irq <= 0)
1904	pb->irq = PARPORT_IRQ_NONE;
1905
1906	return pb->irq;
1907	#endif /* Advanced detection */
1908	}
1909
1910	static int irq_probe_SPP(struct parport *pb)
1911	{
1912	/* Don't even try to do this. */
1913	return PARPORT_IRQ_NONE;
1914	}
1915
1916	/* We will attempt to share interrupt requests since other devices
1917	* such as sound cards and network cards seem to like using the
1918	* printer IRQs.
1919	*
1920	* When ECP is available we can autoprobe for IRQs.
1921	* NOTE: If we can autoprobe it, we can register the IRQ.
1922	*/
1923	static int parport_irq_probe(struct parport *pb)
1924	{
1925	struct parport_pc_private *priv = pb->private_data;
1926
1927	if (priv->ecr) {
1928	pb->irq = programmable_irq_support(pb);
1929
1930	if (pb->irq == PARPORT_IRQ_NONE)
1931	pb->irq = irq_probe_ECP(pb);
1932	}
1933
1934	if ((pb->irq == PARPORT_IRQ_NONE) && priv->ecr &&
1935	(pb->modes & PARPORT_MODE_EPP))
1936	pb->irq = irq_probe_EPP(pb);
1937
1938	clear_epp_timeout(pb);
1939
1940	if (pb->irq == PARPORT_IRQ_NONE && (pb->modes & PARPORT_MODE_EPP))
1941	pb->irq = irq_probe_EPP(pb);
1942
1943	clear_epp_timeout(pb);
1944
1945	if (pb->irq == PARPORT_IRQ_NONE)
1946	pb->irq = irq_probe_SPP(pb);
1947
1948	if (pb->irq == PARPORT_IRQ_NONE)
1949	pb->irq = get_superio_irq(pb);
1950
1951	return pb->irq;
1952	}
1953
1954	/* --- DMA detection -------------------------------------- */
1955
1956	/* Only if chipset conforms to ECP ISA Interface Standard */
1957	static int programmable_dma_support(struct parport *p)
1958	{
1959	unsigned char oecr = inb(ECONTROL(p));
1960	int dma;
1961
1962	frob_set_mode(p, ECR_CNF);
1963
1964	dma = inb(CONFIGB(p)) & 0x07;
1965	/* 000: Indicates jumpered 8-bit DMA if read-only.
1966	100: Indicates jumpered 16-bit DMA if read-only. */
1967	if ((dma & 0x03) == 0)
1968	dma = PARPORT_DMA_NONE;
1969
1970	ECR_WRITE(p, oecr);
1971	return dma;
1972	}
1973
1974	static int parport_dma_probe(struct parport *p)
1975	{
1976	const struct parport_pc_private *priv = p->private_data;
1977	if (priv->ecr) /* ask ECP chipset first */
1978	p->dma = programmable_dma_support(p);
1979	if (p->dma == PARPORT_DMA_NONE) {
1980	/* ask known Super-IO chips proper, although these
1981	claim ECP compatible, some don't report their DMA
1982	conforming to ECP standards */
1983	p->dma = get_superio_dma(p);
1984	}
1985
1986	return p->dma;
1987	}
1988
1989	/* --- Initialisation code -------------------------------- */
1990
1991	static LIST_HEAD(ports_list);
1992	static DEFINE_SPINLOCK(ports_lock);
1993
1994	struct parport *parport_pc_probe_port(unsigned long int base,
1995	unsigned long int base_hi,
1996	int irq, int dma,
1997	struct device *dev,
1998	int irqflags)
1999	{
2000	struct parport_pc_private *priv;
2001	struct parport_operations *ops;
2002	struct parport *p;
2003	int probedirq = PARPORT_IRQ_NONE;
2004	struct resource *base_res;
2005	struct resource *ECR_res = NULL;
2006	struct resource *EPP_res = NULL;
2007	struct platform_device *pdev = NULL;
2008
2009	if (!dev) {
2010	/* We need a physical device to attach to, but none was
2011	* provided. Create our own. */
2012	pdev = platform_device_register_simple("parport_pc",
2013	base, NULL, 0);
2014	if (IS_ERR(pdev))
2015	return NULL;
2016	dev = &pdev->dev;
2017
2018	dev->coherent_dma_mask = DMA_BIT_MASK(24);
2019	dev->dma_mask = &dev->coherent_dma_mask;
2020	}
2021
2022	ops = kmalloc(sizeof(struct parport_operations), GFP_KERNEL);
2023	if (!ops)
2024	goto out1;
2025
2026	priv = kmalloc(sizeof(struct parport_pc_private), GFP_KERNEL);
2027	if (!priv)
2028	goto out2;
2029
2030	/* a misnomer, actually - it's allocate and reserve parport number */
2031	p = parport_register_port(base, irq, dma, ops);
2032	if (!p)
2033	goto out3;
2034
2035	base_res = request_region(base, 3, p->name);
2036	if (!base_res)
2037	goto out4;
2038
2039	memcpy(ops, &parport_pc_ops, sizeof(struct parport_operations));
2040	priv->ctr = 0xc;
2041	priv->ctr_writable = ~0x10;
2042	priv->ecr = 0;
2043	priv->fifo_depth = 0;
2044	priv->dma_buf = NULL;
2045	priv->dma_handle = 0;
2046	INIT_LIST_HEAD(&priv->list);
2047	priv->port = p;
2048
2049	p->dev = dev;
2050	p->base_hi = base_hi;
2051	p->modes = PARPORT_MODE_PCSPP \| PARPORT_MODE_SAFEININT;
2052	p->private_data = priv;
2053
2054	if (base_hi) {
2055	ECR_res = request_region(base_hi, 3, p->name);
2056	if (ECR_res)
2057	parport_ECR_present(p);
2058	}
2059
2060	if (base != 0x3bc) {
2061	EPP_res = request_region(base+0x3, 5, p->name);
2062	if (EPP_res)
2063	if (!parport_EPP_supported(p))
2064	parport_ECPEPP_supported(p);
2065	}
2066	if (!parport_SPP_supported(p))
2067	/* No port. */
2068	goto out5;
2069	if (priv->ecr)
2070	parport_ECPPS2_supported(p);
2071	else
2072	parport_PS2_supported(p);
2073
2074	p->size = (p->modes & PARPORT_MODE_EPP) ? 8 : 3;
2075
2076	printk(KERN_INFO "%s: PC-style at 0x%lx", p->name, p->base);
2077	if (p->base_hi && priv->ecr)
2078	printk(KERN_CONT " (0x%lx)", p->base_hi);
2079	if (p->irq == PARPORT_IRQ_AUTO) {
2080	p->irq = PARPORT_IRQ_NONE;
2081	parport_irq_probe(p);
2082	} else if (p->irq == PARPORT_IRQ_PROBEONLY) {
2083	p->irq = PARPORT_IRQ_NONE;
2084	parport_irq_probe(p);
2085	probedirq = p->irq;
2086	p->irq = PARPORT_IRQ_NONE;
2087	}
2088	if (p->irq != PARPORT_IRQ_NONE) {
2089	printk(KERN_CONT ", irq %d", p->irq);
2090	priv->ctr_writable \|= 0x10;
2091
2092	if (p->dma == PARPORT_DMA_AUTO) {
2093	p->dma = PARPORT_DMA_NONE;
2094	parport_dma_probe(p);
2095	}
2096	}
2097	if (p->dma == PARPORT_DMA_AUTO) /* To use DMA, giving the irq
2098	is mandatory (see above) */
2099	p->dma = PARPORT_DMA_NONE;
2100
2101	#ifdef CONFIG_PARPORT_PC_FIFO
2102	if (parport_ECP_supported(p) &&
2103	p->dma != PARPORT_DMA_NOFIFO &&
2104	priv->fifo_depth > 0 && p->irq != PARPORT_IRQ_NONE) {
2105	p->modes \|= PARPORT_MODE_ECP \| PARPORT_MODE_COMPAT;
2106	p->ops->compat_write_data = parport_pc_compat_write_block_pio;
2107	#ifdef CONFIG_PARPORT_1284
2108	p->ops->ecp_write_data = parport_pc_ecp_write_block_pio;
2109	/* currently broken, but working on it.. (FB) */
2110	/* p->ops->ecp_read_data = parport_pc_ecp_read_block_pio; */
2111	#endif /* IEEE 1284 support */
2112	if (p->dma != PARPORT_DMA_NONE) {
2113	printk(KERN_CONT ", dma %d", p->dma);
2114	p->modes \|= PARPORT_MODE_DMA;
2115	} else
2116	printk(KERN_CONT ", using FIFO");
2117	} else
2118	/* We can't use the DMA channel after all. */
2119	p->dma = PARPORT_DMA_NONE;
2120	#endif /* Allowed to use FIFO/DMA */
2121
2122	printk(KERN_CONT " [");
2123
2124	#define printmode(x) \
2125	{\
2126	if (p->modes & PARPORT_MODE_##x) {\
2127	printk(KERN_CONT "%s%s", f ? "," : "", #x);\
2128	f++;\
2129	} \
2130	}
2131
2132	{
2133	int f = 0;
2134	printmode(PCSPP);
2135	printmode(TRISTATE);
2136	printmode(COMPAT)
2137	printmode(EPP);
2138	printmode(ECP);
2139	printmode(DMA);
2140	}
2141	#undef printmode
2142	#ifndef CONFIG_PARPORT_1284
2143	printk(KERN_CONT "(,...)");
2144	#endif /* CONFIG_PARPORT_1284 */
2145	printk(KERN_CONT "]\n");
2146	if (probedirq != PARPORT_IRQ_NONE)
2147	printk(KERN_INFO "%s: irq %d detected\n", p->name, probedirq);
2148
2149	/* If No ECP release the ports grabbed above. */
2150	if (ECR_res && (p->modes & PARPORT_MODE_ECP) == 0) {
2151	release_region(base_hi, 3);
2152	ECR_res = NULL;
2153	}
2154	/* Likewise for EEP ports */
2155	if (EPP_res && (p->modes & PARPORT_MODE_EPP) == 0) {
2156	release_region(base+3, 5);
2157	EPP_res = NULL;
2158	}
2159	if (p->irq != PARPORT_IRQ_NONE) {
2160	if (request_irq(p->irq, parport_irq_handler,
2161	irqflags, p->name, p)) {
2162	printk(KERN_WARNING "%s: irq %d in use, "
2163	"resorting to polled operation\n",
2164	p->name, p->irq);
2165	p->irq = PARPORT_IRQ_NONE;
2166	p->dma = PARPORT_DMA_NONE;
2167	}
2168
2169	#ifdef CONFIG_PARPORT_PC_FIFO
2170	#ifdef HAS_DMA
2171	if (p->dma != PARPORT_DMA_NONE) {
2172	if (request_dma(p->dma, p->name)) {
2173	printk(KERN_WARNING "%s: dma %d in use, "
2174	"resorting to PIO operation\n",
2175	p->name, p->dma);
2176	p->dma = PARPORT_DMA_NONE;
2177	} else {
2178	priv->dma_buf =
2179	dma_alloc_coherent(dev,
2180	PAGE_SIZE,
2181	&priv->dma_handle,
2182	GFP_KERNEL);
2183	if (!priv->dma_buf) {
2184	printk(KERN_WARNING "%s: "
2185	"cannot get buffer for DMA, "
2186	"resorting to PIO operation\n",
2187	p->name);
2188	free_dma(p->dma);
2189	p->dma = PARPORT_DMA_NONE;
2190	}
2191	}
2192	}
2193	#endif
2194	#endif
2195	}
2196
2197	/* Done probing. Now put the port into a sensible start-up state. */
2198	if (priv->ecr)
2199	/*
2200	* Put the ECP detected port in PS2 mode.
2201	* Do this also for ports that have ECR but don't do ECP.
2202	*/
2203	ECR_WRITE(p, 0x34);
2204
2205	parport_pc_write_data(p, 0);
2206	parport_pc_data_forward(p);
2207
2208	/* Now that we've told the sharing engine about the port, and
2209	found out its characteristics, let the high-level drivers
2210	know about it. */
2211	spin_lock(&ports_lock);
2212	list_add(&priv->list, &ports_list);
2213	spin_unlock(&ports_lock);
2214	parport_announce_port(p);
2215
2216	return p;
2217
2218	out5:
2219	if (ECR_res)
2220	release_region(base_hi, 3);
2221	if (EPP_res)
2222	release_region(base+0x3, 5);
2223	release_region(base, 3);
2224	out4:
2225	parport_put_port(p);
2226	out3:
2227	kfree(priv);
2228	out2:
2229	kfree(ops);
2230	out1:
2231	if (pdev)
2232	platform_device_unregister(pdev);
2233	return NULL;
2234	}
2235	EXPORT_SYMBOL(parport_pc_probe_port);
2236
2237	void parport_pc_unregister_port(struct parport *p)
2238	{
2239	struct parport_pc_private *priv = p->private_data;
2240	struct parport_operations *ops = p->ops;
2241
2242	parport_remove_port(p);
2243	spin_lock(&ports_lock);
2244	list_del_init(&priv->list);
2245	spin_unlock(&ports_lock);
2246	#if defined(CONFIG_PARPORT_PC_FIFO) && defined(HAS_DMA)
2247	if (p->dma != PARPORT_DMA_NONE)
2248	free_dma(p->dma);
2249	#endif
2250	if (p->irq != PARPORT_IRQ_NONE)
2251	free_irq(p->irq, p);
2252	release_region(p->base, 3);
2253	if (p->size > 3)
2254	release_region(p->base + 3, p->size - 3);
2255	if (p->modes & PARPORT_MODE_ECP)
2256	release_region(p->base_hi, 3);
2257	#if defined(CONFIG_PARPORT_PC_FIFO) && defined(HAS_DMA)
2258	if (priv->dma_buf)
2259	dma_free_coherent(p->physport->dev, PAGE_SIZE,
2260	priv->dma_buf,
2261	priv->dma_handle);
2262	#endif
2263	kfree(p->private_data);
2264	parport_put_port(p);
2265	kfree(ops); /* hope no-one cached it */
2266	}
2267	EXPORT_SYMBOL(parport_pc_unregister_port);
2268
2269	#ifdef CONFIG_PCI
2270
2271	/* ITE support maintained by Rich Liu <richliu@poorman.org> */
2272	static int __devinit sio_ite_8872_probe(struct pci_dev *pdev, int autoirq,
2273	int autodma,
2274	const struct parport_pc_via_data *via)
2275	{
2276	short inta_addr[6] = { 0x2A0, 0x2C0, 0x220, 0x240, 0x1E0 };
2277	u32 ite8872set;
2278	u32 ite8872_lpt, ite8872_lpthi;
2279	u8 ite8872_irq, type;
2280	int irq;
2281	int i;
2282
2283	DPRINTK(KERN_DEBUG "sio_ite_8872_probe()\n");
2284
2285	/* make sure which one chip */
2286	for (i = 0; i < 5; i++) {
2287	if (request_region(inta_addr[i], 32, "it887x")) {
2288	int test;
2289	pci_write_config_dword(pdev, 0x60,
2290	0xe5000000 \| inta_addr[i]);
2291	pci_write_config_dword(pdev, 0x78,
2292	0x00000000 \| inta_addr[i]);
2293	test = inb(inta_addr[i]);
2294	if (test != 0xff)
2295	break;
2296	release_region(inta_addr[i], 32);
2297	}
2298	}
2299	if (i >= 5) {
2300	printk(KERN_INFO "parport_pc: cannot find ITE8872 INTA\n");
2301	return 0;
2302	}
2303
2304	type = inb(inta_addr[i] + 0x18);
2305	type &= 0x0f;
2306
2307	switch (type) {
2308	case 0x2:
2309	printk(KERN_INFO "parport_pc: ITE8871 found (1P)\n");
2310	ite8872set = 0x64200000;
2311	break;
2312	case 0xa:
2313	printk(KERN_INFO "parport_pc: ITE8875 found (1P)\n");
2314	ite8872set = 0x64200000;
2315	break;
2316	case 0xe:
2317	printk(KERN_INFO "parport_pc: ITE8872 found (2S1P)\n");
2318	ite8872set = 0x64e00000;
2319	break;
2320	case 0x6:
2321	printk(KERN_INFO "parport_pc: ITE8873 found (1S)\n");
2322	release_region(inta_addr[i], 32);
2323	return 0;
2324	case 0x8:
2325	printk(KERN_INFO "parport_pc: ITE8874 found (2S)\n");
2326	release_region(inta_addr[i], 32);
2327	return 0;
2328	default:
2329	printk(KERN_INFO "parport_pc: unknown ITE887x\n");
2330	printk(KERN_INFO "parport_pc: please mail 'lspci -nvv' "
2331	"output to Rich.Liu@ite.com.tw\n");
2332	release_region(inta_addr[i], 32);
2333	return 0;
2334	}
2335
2336	pci_read_config_byte(pdev, 0x3c, &ite8872_irq);
2337	pci_read_config_dword(pdev, 0x1c, &ite8872_lpt);
2338	ite8872_lpt &= 0x0000ff00;
2339	pci_read_config_dword(pdev, 0x20, &ite8872_lpthi);
2340	ite8872_lpthi &= 0x0000ff00;
2341	pci_write_config_dword(pdev, 0x6c, 0xe3000000 \| ite8872_lpt);
2342	pci_write_config_dword(pdev, 0x70, 0xe3000000 \| ite8872_lpthi);
2343	pci_write_config_dword(pdev, 0x80, (ite8872_lpthi<<16) \| ite8872_lpt);
2344	/* SET SPP&EPP , Parallel Port NO DMA , Enable All Function */
2345	/* SET Parallel IRQ */
2346	pci_write_config_dword(pdev, 0x9c,
2347	ite8872set \| (ite8872_irq * 0x11111));
2348
2349	DPRINTK(KERN_DEBUG "ITE887x: The IRQ is %d.\n", ite8872_irq);
2350	DPRINTK(KERN_DEBUG "ITE887x: The PARALLEL I/O port is 0x%x.\n",
2351	ite8872_lpt);
2352	DPRINTK(KERN_DEBUG "ITE887x: The PARALLEL I/O porthi is 0x%x.\n",
2353	ite8872_lpthi);
2354
2355	/* Let the user (or defaults) steer us away from interrupts */
2356	irq = ite8872_irq;
2357	if (autoirq != PARPORT_IRQ_AUTO)
2358	irq = PARPORT_IRQ_NONE;
2359
2360	/*
2361	* Release the resource so that parport_pc_probe_port can get it.
2362	*/
2363	release_region(inta_addr[i], 32);
2364	if (parport_pc_probe_port(ite8872_lpt, ite8872_lpthi,
2365	irq, PARPORT_DMA_NONE, &pdev->dev, 0)) {
2366	printk(KERN_INFO
2367	"parport_pc: ITE 8872 parallel port: io=0x%X",
2368	ite8872_lpt);
2369	if (irq != PARPORT_IRQ_NONE)
2370	printk(", irq=%d", irq);
2371	printk("\n");
2372	return 1;
2373	}
2374
2375	return 0;
2376	}
2377
2378	/* VIA 8231 support by Pavel Fedin <sonic_amiga@rambler.ru>
2379	based on VIA 686a support code by Jeff Garzik <jgarzik@pobox.com> */
2380	static int __devinitdata parport_init_mode;
2381
2382	/* Data for two known VIA chips */
2383	static struct parport_pc_via_data via_686a_data __devinitdata = {
2384	0x51,
2385	0x50,
2386	0x85,
2387	0x02,
2388	0xE2,
2389	0xF0,
2390	0xE6
2391	};
2392	static struct parport_pc_via_data via_8231_data __devinitdata = {
2393	0x45,
2394	0x44,
2395	0x50,
2396	0x04,
2397	0xF2,
2398	0xFA,
2399	0xF6
2400	};
2401
2402	static int __devinit sio_via_probe(struct pci_dev *pdev, int autoirq,
2403	int autodma,
2404	const struct parport_pc_via_data *via)
2405	{
2406	u8 tmp, tmp2, siofunc;
2407	u8 ppcontrol = 0;
2408	int dma, irq;
2409	unsigned port1, port2;
2410	unsigned have_epp = 0;
2411
2412	printk(KERN_DEBUG "parport_pc: VIA 686A/8231 detected\n");
2413
2414	switch (parport_init_mode) {
2415	case 1:
2416	printk(KERN_DEBUG "parport_pc: setting SPP mode\n");
2417	siofunc = VIA_FUNCTION_PARPORT_SPP;
2418	break;
2419	case 2:
2420	printk(KERN_DEBUG "parport_pc: setting PS/2 mode\n");
2421	siofunc = VIA_FUNCTION_PARPORT_SPP;
2422	ppcontrol = VIA_PARPORT_BIDIR;
2423	break;
2424	case 3:
2425	printk(KERN_DEBUG "parport_pc: setting EPP mode\n");
2426	siofunc = VIA_FUNCTION_PARPORT_EPP;
2427	ppcontrol = VIA_PARPORT_BIDIR;
2428	have_epp = 1;
2429	break;
2430	case 4:
2431	printk(KERN_DEBUG "parport_pc: setting ECP mode\n");
2432	siofunc = VIA_FUNCTION_PARPORT_ECP;
2433	ppcontrol = VIA_PARPORT_BIDIR;
2434	break;
2435	case 5:
2436	printk(KERN_DEBUG "parport_pc: setting EPP+ECP mode\n");
2437	siofunc = VIA_FUNCTION_PARPORT_ECP;
2438	ppcontrol = VIA_PARPORT_BIDIR\|VIA_PARPORT_ECPEPP;
2439	have_epp = 1;
2440	break;
2441	default:
2442	printk(KERN_DEBUG
2443	"parport_pc: probing current configuration\n");
2444	siofunc = VIA_FUNCTION_PROBE;
2445	break;
2446	}
2447	/*
2448	* unlock super i/o configuration
2449	*/
2450	pci_read_config_byte(pdev, via->via_pci_superio_config_reg, &tmp);
2451	tmp \|= via->via_pci_superio_config_data;
2452	pci_write_config_byte(pdev, via->via_pci_superio_config_reg, tmp);
2453
2454	/* Bits 1-0: Parallel Port Mode / Enable */
2455	outb(via->viacfg_function, VIA_CONFIG_INDEX);
2456	tmp = inb(VIA_CONFIG_DATA);
2457	/* Bit 5: EPP+ECP enable; bit 7: PS/2 bidirectional port enable */
2458	outb(via->viacfg_parport_control, VIA_CONFIG_INDEX);
2459	tmp2 = inb(VIA_CONFIG_DATA);
2460	if (siofunc == VIA_FUNCTION_PROBE) {
2461	siofunc = tmp & VIA_FUNCTION_PARPORT_DISABLE;
2462	ppcontrol = tmp2;
2463	} else {
2464	tmp &= ~VIA_FUNCTION_PARPORT_DISABLE;
2465	tmp \|= siofunc;
2466	outb(via->viacfg_function, VIA_CONFIG_INDEX);
2467	outb(tmp, VIA_CONFIG_DATA);
2468	tmp2 &= ~(VIA_PARPORT_BIDIR\|VIA_PARPORT_ECPEPP);
2469	tmp2 \|= ppcontrol;
2470	outb(via->viacfg_parport_control, VIA_CONFIG_INDEX);
2471	outb(tmp2, VIA_CONFIG_DATA);
2472	}
2473
2474	/* Parallel Port I/O Base Address, bits 9-2 */
2475	outb(via->viacfg_parport_base, VIA_CONFIG_INDEX);
2476	port1 = inb(VIA_CONFIG_DATA) << 2;
2477
2478	printk(KERN_DEBUG "parport_pc: Current parallel port base: 0x%X\n",
2479	port1);
2480	if (port1 == 0x3BC && have_epp) {
2481	outb(via->viacfg_parport_base, VIA_CONFIG_INDEX);
2482	outb((0x378 >> 2), VIA_CONFIG_DATA);
2483	printk(KERN_DEBUG
2484	"parport_pc: Parallel port base changed to 0x378\n");
2485	port1 = 0x378;
2486	}
2487
2488	/*
2489	* lock super i/o configuration
2490	*/
2491	pci_read_config_byte(pdev, via->via_pci_superio_config_reg, &tmp);
2492	tmp &= ~via->via_pci_superio_config_data;
2493	pci_write_config_byte(pdev, via->via_pci_superio_config_reg, tmp);
2494
2495	if (siofunc == VIA_FUNCTION_PARPORT_DISABLE) {
2496	printk(KERN_INFO "parport_pc: VIA parallel port disabled in BIOS\n");
2497	return 0;
2498	}
2499
2500	/* Bits 7-4: PnP Routing for Parallel Port IRQ */
2501	pci_read_config_byte(pdev, via->via_pci_parport_irq_reg, &tmp);
2502	irq = ((tmp & VIA_IRQCONTROL_PARALLEL) >> 4);
2503
2504	if (siofunc == VIA_FUNCTION_PARPORT_ECP) {
2505	/* Bits 3-2: PnP Routing for Parallel Port DMA */
2506	pci_read_config_byte(pdev, via->via_pci_parport_dma_reg, &tmp);
2507	dma = ((tmp & VIA_DMACONTROL_PARALLEL) >> 2);
2508	} else
2509	/* if ECP not enabled, DMA is not enabled, assumed
2510	bogus 'dma' value */
2511	dma = PARPORT_DMA_NONE;
2512
2513	/* Let the user (or defaults) steer us away from interrupts and DMA */
2514	if (autoirq == PARPORT_IRQ_NONE) {
2515	irq = PARPORT_IRQ_NONE;
2516	dma = PARPORT_DMA_NONE;
2517	}
2518	if (autodma == PARPORT_DMA_NONE)
2519	dma = PARPORT_DMA_NONE;
2520
2521	switch (port1) {
2522	case 0x3bc:
2523	port2 = 0x7bc; break;
2524	case 0x378:
2525	port2 = 0x778; break;
2526	case 0x278:
2527	port2 = 0x678; break;
2528	default:
2529	printk(KERN_INFO
2530	"parport_pc: Weird VIA parport base 0x%X, ignoring\n",
2531	port1);
2532	return 0;
2533	}
2534
2535	/* filter bogus IRQs */
2536	switch (irq) {
2537	case 0:
2538	case 2:
2539	case 8:
2540	case 13:
2541	irq = PARPORT_IRQ_NONE;
2542	break;
2543
2544	default: /* do nothing */
2545	break;
2546	}
2547
2548	/* finally, do the probe with values obtained */
2549	if (parport_pc_probe_port(port1, port2, irq, dma, &pdev->dev, 0)) {
2550	printk(KERN_INFO
2551	"parport_pc: VIA parallel port: io=0x%X", port1);
2552	if (irq != PARPORT_IRQ_NONE)
2553	printk(", irq=%d", irq);
2554	if (dma != PARPORT_DMA_NONE)
2555	printk(", dma=%d", dma);
2556	printk("\n");
2557	return 1;
2558	}
2559
2560	printk(KERN_WARNING "parport_pc: Strange, can't probe VIA parallel port: io=0x%X, irq=%d, dma=%d\n",
2561	port1, irq, dma);
2562	return 0;
2563	}
2564
2565
2566	enum parport_pc_sio_types {
2567	sio_via_686a = 0, /* Via VT82C686A motherboard Super I/O */
2568	sio_via_8231, /* Via VT8231 south bridge integrated Super IO */
2569	sio_ite_8872,
2570	last_sio
2571	};
2572
2573	/* each element directly indexed from enum list, above */
2574	static struct parport_pc_superio {
2575	int (probe) (struct pci_dev pdev, int autoirq, int autodma,
2576	const struct parport_pc_via_data *via);
2577	const struct parport_pc_via_data *via;
2578	} parport_pc_superio_info[] __devinitdata = {
2579	{ sio_via_probe, &via_686a_data, },
2580	{ sio_via_probe, &via_8231_data, },
2581	{ sio_ite_8872_probe, NULL, },
2582	};
2583
2584	enum parport_pc_pci_cards {
2585	siig_1p_10x = last_sio,
2586	siig_2p_10x,
2587	siig_1p_20x,
2588	siig_2p_20x,
2589	lava_parallel,
2590	lava_parallel_dual_a,
2591	lava_parallel_dual_b,
2592	boca_ioppar,
2593	plx_9050,
2594	timedia_4006a,
2595	timedia_4014,
2596	timedia_4008a,
2597	timedia_4018,
2598	timedia_9018a,
2599	syba_2p_epp,
2600	syba_1p_ecp,
2601	titan_010l,
2602	titan_1284p1,
2603	titan_1284p2,
2604	avlab_1p,
2605	avlab_2p,
2606	oxsemi_952,
2607	oxsemi_954,
2608	oxsemi_840,
2609	oxsemi_pcie_pport,
2610	aks_0100,
2611	mobility_pp,
2612	netmos_9705,
2613	netmos_9715,
2614	netmos_9755,
2615	netmos_9805,
2616	netmos_9815,
2617	netmos_9901,
2618	netmos_9865,
2619	quatech_sppxp100,
2620	};
2621
2622
2623	/* each element directly indexed from enum list, above
2624	* (but offset by last_sio) */
2625	static struct parport_pc_pci {
2626	int numports;
2627	struct { /* BAR (base address registers) numbers in the config
2628	space header */
2629	int lo;
2630	int hi;
2631	/* -1 if not there, >6 for offset-method (max BAR is 6) */
2632	} addr[4];
2633
2634	/* If set, this is called immediately after pci_enable_device.
2635	* If it returns non-zero, no probing will take place and the
2636	* ports will not be used. */
2637	int (preinit_hook) (struct pci_dev pdev, int autoirq, int autodma);
2638
2639	/* If set, this is called after probing for ports. If 'failed'
2640	* is non-zero we couldn't use any of the ports. */
2641	void (postinit_hook) (struct pci_dev pdev, int failed);
2642	} cards[] = {
2643	/* siig_1p_10x */ { 1, { { 2, 3 }, } },
2644	/* siig_2p_10x */ { 2, { { 2, 3 }, { 4, 5 }, } },
2645	/* siig_1p_20x */ { 1, { { 0, 1 }, } },
2646	/* siig_2p_20x */ { 2, { { 0, 1 }, { 2, 3 }, } },
2647	/* lava_parallel */ { 1, { { 0, -1 }, } },
2648	/* lava_parallel_dual_a */ { 1, { { 0, -1 }, } },
2649	/* lava_parallel_dual_b */ { 1, { { 0, -1 }, } },
2650	/* boca_ioppar */ { 1, { { 0, -1 }, } },
2651	/* plx_9050 */ { 2, { { 4, -1 }, { 5, -1 }, } },
2652	/* timedia_4006a */ { 1, { { 0, -1 }, } },
2653	/* timedia_4014 */ { 2, { { 0, -1 }, { 2, -1 }, } },
2654	/* timedia_4008a */ { 1, { { 0, 1 }, } },
2655	/* timedia_4018 */ { 2, { { 0, 1 }, { 2, 3 }, } },
2656	/* timedia_9018a */ { 2, { { 0, 1 }, { 2, 3 }, } },
2657	/* SYBA uses fixed offsets in
2658	a 1K io window */
2659	/* syba_2p_epp AP138B */ { 2, { { 0, 0x078 }, { 0, 0x178 }, } },
2660	/* syba_1p_ecp W83787 */ { 1, { { 0, 0x078 }, } },
2661	/* titan_010l */ { 1, { { 3, -1 }, } },
2662	/* titan_1284p1 */ { 1, { { 0, 1 }, } },
2663	/* titan_1284p2 */ { 2, { { 0, 1 }, { 2, 3 }, } },
2664	/* avlab_1p */ { 1, { { 0, 1}, } },
2665	/* avlab_2p */ { 2, { { 0, 1}, { 2, 3 },} },
2666	/* The Oxford Semi cards are unusual: 954 doesn't support ECP,
2667	* and 840 locks up if you write 1 to bit 2! */
2668	/* oxsemi_952 */ { 1, { { 0, 1 }, } },
2669	/* oxsemi_954 */ { 1, { { 0, -1 }, } },
2670	/* oxsemi_840 */ { 1, { { 0, 1 }, } },
2671	/* oxsemi_pcie_pport */ { 1, { { 0, 1 }, } },
2672	/* aks_0100 */ { 1, { { 0, -1 }, } },
2673	/* mobility_pp */ { 1, { { 0, 1 }, } },
2674
2675	/* The netmos entries below are untested */
2676	/* netmos_9705 */ { 1, { { 0, -1 }, } },
2677	/* netmos_9715 */ { 2, { { 0, 1 }, { 2, 3 },} },
2678	/* netmos_9755 */ { 2, { { 0, 1 }, { 2, 3 },} },
2679	/* netmos_9805 */ { 1, { { 0, -1 }, } },
2680	/* netmos_9815 */ { 2, { { 0, -1 }, { 2, -1 }, } },
2681	/* netmos_9901 */ { 1, { { 0, -1 }, } },
2682	/* netmos_9865 */ { 1, { { 0, -1 }, } },
2683	/* quatech_sppxp100 */ { 1, { { 0, 1 }, } },
2684	};
2685
2686	static const struct pci_device_id parport_pc_pci_tbl[] = {
2687	/* Super-IO onboard chips */
2688	{ 0x1106, 0x0686, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sio_via_686a },
2689	{ 0x1106, 0x8231, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sio_via_8231 },
2690	{ PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872,
2691	PCI_ANY_ID, PCI_ANY_ID, 0, 0, sio_ite_8872 },
2692
2693	/* PCI cards */
2694	{ PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1P_10x,
2695	PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_1p_10x },
2696	{ PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2P_10x,
2697	PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_2p_10x },
2698	{ PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1P_20x,
2699	PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_1p_20x },
2700	{ PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2P_20x,
2701	PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_2p_20x },
2702	{ PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PARALLEL,
2703	PCI_ANY_ID, PCI_ANY_ID, 0, 0, lava_parallel },
2704	{ PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DUAL_PAR_A,
2705	PCI_ANY_ID, PCI_ANY_ID, 0, 0, lava_parallel_dual_a },
2706	{ PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DUAL_PAR_B,
2707	PCI_ANY_ID, PCI_ANY_ID, 0, 0, lava_parallel_dual_b },
2708	{ PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_BOCA_IOPPAR,
2709	PCI_ANY_ID, PCI_ANY_ID, 0, 0, boca_ioppar },
2710	{ PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2711	PCI_SUBVENDOR_ID_EXSYS, PCI_SUBDEVICE_ID_EXSYS_4014, 0, 0, plx_9050 },
2712	/* PCI_VENDOR_ID_TIMEDIA/SUNIX has many differing cards ...*/
2713	{ 0x1409, 0x7268, 0x1409, 0x0101, 0, 0, timedia_4006a },
2714	{ 0x1409, 0x7268, 0x1409, 0x0102, 0, 0, timedia_4014 },
2715	{ 0x1409, 0x7268, 0x1409, 0x0103, 0, 0, timedia_4008a },
2716	{ 0x1409, 0x7268, 0x1409, 0x0104, 0, 0, timedia_4018 },
2717	{ 0x1409, 0x7268, 0x1409, 0x9018, 0, 0, timedia_9018a },
2718	{ PCI_VENDOR_ID_SYBA, PCI_DEVICE_ID_SYBA_2P_EPP,
2719	PCI_ANY_ID, PCI_ANY_ID, 0, 0, syba_2p_epp },
2720	{ PCI_VENDOR_ID_SYBA, PCI_DEVICE_ID_SYBA_1P_ECP,
2721	PCI_ANY_ID, PCI_ANY_ID, 0, 0, syba_1p_ecp },
2722	{ PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_010L,
2723	PCI_ANY_ID, PCI_ANY_ID, 0, 0, titan_010l },
2724	{ 0x9710, 0x9805, 0x1000, 0x0010, 0, 0, titan_1284p1 },
2725	{ 0x9710, 0x9815, 0x1000, 0x0020, 0, 0, titan_1284p2 },
2726	/* PCI_VENDOR_ID_AVLAB/Intek21 has another bunch of cards ...*/
2727	/* AFAVLAB_TK9902 */
2728	{ 0x14db, 0x2120, PCI_ANY_ID, PCI_ANY_ID, 0, 0, avlab_1p},
2729	{ 0x14db, 0x2121, PCI_ANY_ID, PCI_ANY_ID, 0, 0, avlab_2p},
2730	{ PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952PP,
2731	PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_952 },
2732	{ PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954PP,
2733	PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_954 },
2734	{ PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_12PCI840,
2735	PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_840 },
2736	{ PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_PCIe840,
2737	PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport },
2738	{ PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_PCIe840_G,
2739	PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport },
2740	{ PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_PCIe952_0,
2741	PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport },
2742	{ PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_PCIe952_0_G,
2743	PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport },
2744	{ PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_PCIe952_1,
2745	PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport },
2746	{ PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_PCIe952_1_G,
2747	PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport },
2748	{ PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_PCIe952_1_U,
2749	PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport },
2750	{ PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_PCIe952_1_GU,
2751	PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport },
2752	{ PCI_VENDOR_ID_AKS, PCI_DEVICE_ID_AKS_ALADDINCARD,
2753	PCI_ANY_ID, PCI_ANY_ID, 0, 0, aks_0100 },
2754	{ 0x14f2, 0x0121, PCI_ANY_ID, PCI_ANY_ID, 0, 0, mobility_pp },
2755	/* NetMos communication controllers */
2756	{ PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9705,
2757	PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9705 },
2758	{ PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9715,
2759	PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9715 },
2760	{ PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9755,
2761	PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9755 },
2762	{ PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9805,
2763	PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9805 },
2764	{ PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9815,
2765	PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9815 },
2766	{ PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9901,
2767	0xA000, 0x2000, 0, 0, netmos_9901 },
2768	{ PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
2769	0xA000, 0x1000, 0, 0, netmos_9865 },
2770	{ PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
2771	0xA000, 0x2000, 0, 0, netmos_9865 },
2772	/* Quatech SPPXP-100 Parallel port PCI ExpressCard */
2773	{ PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SPPXP_100,
2774	PCI_ANY_ID, PCI_ANY_ID, 0, 0, quatech_sppxp100 },
2775	{ 0, } /* terminate list */
2776	};
2777	MODULE_DEVICE_TABLE(pci, parport_pc_pci_tbl);
2778
2779	struct pci_parport_data {
2780	int num;
2781	struct parport *ports[2];
2782	};
2783
2784	static int parport_pc_pci_probe(struct pci_dev *dev,
2785	const struct pci_device_id *id)
2786	{
2787	int err, count, n, i = id->driver_data;
2788	struct pci_parport_data *data;
2789
2790	if (i < last_sio)
2791	/* This is an onboard Super-IO and has already been probed */
2792	return 0;
2793
2794	/* This is a PCI card */
2795	i -= last_sio;
2796	count = 0;
2797	err = pci_enable_device(dev);
2798	if (err)
2799	return err;
2800
2801	data = kmalloc(sizeof(struct pci_parport_data), GFP_KERNEL);
2802	if (!data)
2803	return -ENOMEM;
2804
2805	if (cards[i].preinit_hook &&
2806	cards[i].preinit_hook(dev, PARPORT_IRQ_NONE, PARPORT_DMA_NONE)) {
2807	kfree(data);
2808	return -ENODEV;
2809	}
2810
2811	for (n = 0; n < cards[i].numports; n++) {
2812	int lo = cards[i].addr[n].lo;
2813	int hi = cards[i].addr[n].hi;
2814	int irq;
2815	unsigned long io_lo, io_hi;
2816	io_lo = pci_resource_start(dev, lo);
2817	io_hi = 0;
2818	if ((hi >= 0) && (hi <= 6))
2819	io_hi = pci_resource_start(dev, hi);
2820	else if (hi > 6)
2821	io_lo += hi; /* Reinterpret the meaning of
2822	"hi" as an offset (see SYBA
2823	def.) */
2824	/* TODO: test if sharing interrupts works */
2825	irq = dev->irq;
2826	if (irq == IRQ_NONE) {
2827	printk(KERN_DEBUG
2828	"PCI parallel port detected: %04x:%04x, I/O at %#lx(%#lx)\n",
2829	parport_pc_pci_tbl[i + last_sio].vendor,
2830	parport_pc_pci_tbl[i + last_sio].device,
2831	io_lo, io_hi);
2832	irq = PARPORT_IRQ_NONE;
2833	} else {
2834	printk(KERN_DEBUG
2835	"PCI parallel port detected: %04x:%04x, I/O at %#lx(%#lx), IRQ %d\n",
2836	parport_pc_pci_tbl[i + last_sio].vendor,
2837	parport_pc_pci_tbl[i + last_sio].device,
2838	io_lo, io_hi, irq);
2839	}
2840	data->ports[count] =
2841	parport_pc_probe_port(io_lo, io_hi, irq,
2842	PARPORT_DMA_NONE, &dev->dev,
2843	IRQF_SHARED);
2844	if (data->ports[count])
2845	count++;
2846	}
2847
2848	data->num = count;
2849
2850	if (cards[i].postinit_hook)
2851	cards[i].postinit_hook(dev, count == 0);
2852
2853	if (count) {
2854	pci_set_drvdata(dev, data);
2855	return 0;
2856	}
2857
2858	kfree(data);
2859
2860	return -ENODEV;
2861	}
2862
2863	static void __devexit parport_pc_pci_remove(struct pci_dev *dev)
2864	{
2865	struct pci_parport_data *data = pci_get_drvdata(dev);
2866	int i;
2867
2868	pci_set_drvdata(dev, NULL);
2869
2870	if (data) {
2871	for (i = data->num - 1; i >= 0; i--)
2872	parport_pc_unregister_port(data->ports[i]);
2873
2874	kfree(data);
2875	}
2876	}
2877
2878	static struct pci_driver parport_pc_pci_driver = {
2879	.name = "parport_pc",
2880	.id_table = parport_pc_pci_tbl,
2881	.probe = parport_pc_pci_probe,
2882	.remove = __devexit_p(parport_pc_pci_remove),
2883	};
2884
2885	static int __init parport_pc_init_superio(int autoirq, int autodma)
2886	{
2887	const struct pci_device_id *id;
2888	struct pci_dev *pdev = NULL;
2889	int ret = 0;
2890
2891	for_each_pci_dev(pdev) {
2892	id = pci_match_id(parport_pc_pci_tbl, pdev);
2893	if (id == NULL \|\| id->driver_data >= last_sio)
2894	continue;
2895
2896	if (parport_pc_superio_info[id->driver_data].probe(
2897	pdev, autoirq, autodma,
2898	parport_pc_superio_info[id->driver_data].via)) {
2899	ret++;
2900	}
2901	}
2902
2903	return ret; /* number of devices found */
2904	}
2905	#else
2906	static struct pci_driver parport_pc_pci_driver;
2907	static int __init parport_pc_init_superio(int autoirq, int autodma)
2908	{
2909	return 0;
2910	}
2911	#endif /* CONFIG_PCI */
2912
2913	#ifdef CONFIG_PNP
2914
2915	static const struct pnp_device_id parport_pc_pnp_tbl[] = {
2916	/* Standard LPT Printer Port */
2917	{.id = "PNP0400", .driver_data = 0},
2918	/* ECP Printer Port */
2919	{.id = "PNP0401", .driver_data = 0},
2920	{ }
2921	};
2922
2923	MODULE_DEVICE_TABLE(pnp, parport_pc_pnp_tbl);
2924
2925	static int parport_pc_pnp_probe(struct pnp_dev *dev,
2926	const struct pnp_device_id *id)
2927	{
2928	struct parport *pdata;
2929	unsigned long io_lo, io_hi;
2930	int dma, irq;
2931
2932	if (pnp_port_valid(dev, 0) &&
2933	!(pnp_port_flags(dev, 0) & IORESOURCE_DISABLED)) {
2934	io_lo = pnp_port_start(dev, 0);
2935	} else
2936	return -EINVAL;
2937
2938	if (pnp_port_valid(dev, 1) &&
2939	!(pnp_port_flags(dev, 1) & IORESOURCE_DISABLED)) {
2940	io_hi = pnp_port_start(dev, 1);
2941	} else
2942	io_hi = 0;
2943
2944	if (pnp_irq_valid(dev, 0) &&
2945	!(pnp_irq_flags(dev, 0) & IORESOURCE_DISABLED)) {
2946	irq = pnp_irq(dev, 0);
2947	} else
2948	irq = PARPORT_IRQ_NONE;
2949
2950	if (pnp_dma_valid(dev, 0) &&
2951	!(pnp_dma_flags(dev, 0) & IORESOURCE_DISABLED)) {
2952	dma = pnp_dma(dev, 0);
2953	} else
2954	dma = PARPORT_DMA_NONE;
2955
2956	dev_info(&dev->dev, "reported by %s\n", dev->protocol->name);
2957	pdata = parport_pc_probe_port(io_lo, io_hi, irq, dma, &dev->dev, 0);
2958	if (pdata == NULL)
2959	return -ENODEV;
2960
2961	pnp_set_drvdata(dev, pdata);
2962	return 0;
2963	}
2964
2965	static void parport_pc_pnp_remove(struct pnp_dev *dev)
2966	{
2967	struct parport pdata = (struct parport )pnp_get_drvdata(dev);
2968	if (!pdata)
2969	return;
2970
2971	parport_pc_unregister_port(pdata);
2972	}
2973
2974	/* we only need the pnp layer to activate the device, at least for now */
2975	static struct pnp_driver parport_pc_pnp_driver = {
2976	.name = "parport_pc",
2977	.id_table = parport_pc_pnp_tbl,
2978	.probe = parport_pc_pnp_probe,
2979	.remove = parport_pc_pnp_remove,
2980	};
2981
2982	#else
2983	static struct pnp_driver parport_pc_pnp_driver;
2984	#endif /* CONFIG_PNP */
2985
2986	static int __devinit parport_pc_platform_probe(struct platform_device *pdev)
2987	{
2988	/* Always succeed, the actual probing is done in
2989	* parport_pc_probe_port(). */
2990	return 0;
2991	}
2992
2993	static struct platform_driver parport_pc_platform_driver = {
2994	.driver = {
2995	.owner = THIS_MODULE,
2996	.name = "parport_pc",
2997	},
2998	.probe = parport_pc_platform_probe,
2999	};
3000
3001	/* This is called by parport_pc_find_nonpci_ports (in asm/parport.h) */
3002	static int __devinit __attribute__((unused))
3003	parport_pc_find_isa_ports(int autoirq, int autodma)
3004	{
3005	int count = 0;
3006
3007	if (parport_pc_probe_port(0x3bc, 0x7bc, autoirq, autodma, NULL, 0))
3008	count++;
3009	if (parport_pc_probe_port(0x378, 0x778, autoirq, autodma, NULL, 0))
3010	count++;
3011	if (parport_pc_probe_port(0x278, 0x678, autoirq, autodma, NULL, 0))
3012	count++;
3013
3014	return count;
3015	}
3016
3017	/* This function is called by parport_pc_init if the user didn't
3018	* specify any ports to probe. Its job is to find some ports. Order
3019	* is important here -- we want ISA ports to be registered first,
3020	* followed by PCI cards (for least surprise), but before that we want
3021	* to do chipset-specific tests for some onboard ports that we know
3022	* about.
3023	*
3024	* autoirq is PARPORT_IRQ_NONE, PARPORT_IRQ_AUTO, or PARPORT_IRQ_PROBEONLY
3025	* autodma is PARPORT_DMA_NONE or PARPORT_DMA_AUTO
3026	*/
3027	static void __init parport_pc_find_ports(int autoirq, int autodma)
3028	{
3029	int count = 0, err;
3030
3031	#ifdef CONFIG_PARPORT_PC_SUPERIO
3032	detect_and_report_it87();
3033	detect_and_report_winbond();
3034	detect_and_report_smsc();
3035	#endif
3036
3037	/* Onboard SuperIO chipsets that show themselves on the PCI bus. */
3038	count += parport_pc_init_superio(autoirq, autodma);
3039
3040	/* PnP ports, skip detection if SuperIO already found them */
3041	if (!count) {
3042	err = pnp_register_driver(&parport_pc_pnp_driver);
3043	if (!err)
3044	pnp_registered_parport = 1;
3045	}
3046
3047	/* ISA ports and whatever (see asm/parport.h). */
3048	parport_pc_find_nonpci_ports(autoirq, autodma);
3049
3050	err = pci_register_driver(&parport_pc_pci_driver);
3051	if (!err)
3052	pci_registered_parport = 1;
3053	}
3054
3055	/*
3056	* Piles of crap below pretend to be a parser for module and kernel
3057	* parameters. Say "thank you" to whoever had come up with that
3058	* syntax and keep in mind that code below is a cleaned up version.
3059	*/
3060
3061	static int __initdata io[PARPORT_PC_MAX_PORTS+1] = {
3062	[0 ... PARPORT_PC_MAX_PORTS] = 0
3063	};
3064	static int __initdata io_hi[PARPORT_PC_MAX_PORTS+1] = {
3065	[0 ... PARPORT_PC_MAX_PORTS] = PARPORT_IOHI_AUTO
3066	};
3067	static int __initdata dmaval[PARPORT_PC_MAX_PORTS] = {
3068	[0 ... PARPORT_PC_MAX_PORTS-1] = PARPORT_DMA_NONE
3069	};
3070	static int __initdata irqval[PARPORT_PC_MAX_PORTS] = {
3071	[0 ... PARPORT_PC_MAX_PORTS-1] = PARPORT_IRQ_PROBEONLY
3072	};
3073
3074	static int __init parport_parse_param(const char s, int val,
3075	int automatic, int none, int nofifo)
3076	{
3077	if (!s)
3078	return 0;
3079	if (!strncmp(s, "auto", 4))
3080	*val = automatic;
3081	else if (!strncmp(s, "none", 4))
3082	*val = none;
3083	else if (nofifo && !strncmp(s, "nofifo", 6))
3084	*val = nofifo;
3085	else {
3086	char *ep;
3087	unsigned long r = simple_strtoul(s, &ep, 0);
3088	if (ep != s)
3089	*val = r;
3090	else {
3091	printk(KERN_ERR "parport: bad specifier `%s'\n", s);
3092	return -1;
3093	}
3094	}
3095	return 0;
3096	}
3097
3098	static int __init parport_parse_irq(const char irqstr, int val)
3099	{
3100	return parport_parse_param(irqstr, val, PARPORT_IRQ_AUTO,
3101	PARPORT_IRQ_NONE, 0);
3102	}
3103
3104	static int __init parport_parse_dma(const char dmastr, int val)
3105	{
3106	return parport_parse_param(dmastr, val, PARPORT_DMA_AUTO,
3107	PARPORT_DMA_NONE, PARPORT_DMA_NOFIFO);
3108	}
3109
3110	#ifdef CONFIG_PCI
3111	static int __init parport_init_mode_setup(char *str)
3112	{
3113	printk(KERN_DEBUG
3114	"parport_pc.c: Specified parameter parport_init_mode=%s\n", str);
3115
3116	if (!strcmp(str, "spp"))
3117	parport_init_mode = 1;
3118	if (!strcmp(str, "ps2"))
3119	parport_init_mode = 2;
3120	if (!strcmp(str, "epp"))
3121	parport_init_mode = 3;
3122	if (!strcmp(str, "ecp"))
3123	parport_init_mode = 4;
3124	if (!strcmp(str, "ecpepp"))
3125	parport_init_mode = 5;
3126	return 1;
3127	}
3128	#endif
3129
3130	#ifdef MODULE
3131	static char *irq[PARPORT_PC_MAX_PORTS];
3132	static char *dma[PARPORT_PC_MAX_PORTS];
3133
3134	MODULE_PARM_DESC(io, "Base I/O address (SPP regs)");
3135	module_param_array(io, int, NULL, 0);
3136	MODULE_PARM_DESC(io_hi, "Base I/O address (ECR)");
3137	module_param_array(io_hi, int, NULL, 0);
3138	MODULE_PARM_DESC(irq, "IRQ line");
3139	module_param_array(irq, charp, NULL, 0);
3140	MODULE_PARM_DESC(dma, "DMA channel");
3141	module_param_array(dma, charp, NULL, 0);
3142	#if defined(CONFIG_PARPORT_PC_SUPERIO) \|\| \
3143	(defined(CONFIG_PARPORT_1284) && defined(CONFIG_PARPORT_PC_FIFO))
3144	MODULE_PARM_DESC(verbose_probing, "Log chit-chat during initialisation");
3145	module_param(verbose_probing, int, 0644);
3146	#endif
3147	#ifdef CONFIG_PCI
3148	static char *init_mode;
3149	MODULE_PARM_DESC(init_mode,
3150	"Initialise mode for VIA VT8231 port (spp, ps2, epp, ecp or ecpepp)");
3151	module_param(init_mode, charp, 0);
3152	#endif
3153
3154	static int __init parse_parport_params(void)
3155	{
3156	unsigned int i;
3157	int val;
3158
3159	#ifdef CONFIG_PCI
3160	if (init_mode)
3161	parport_init_mode_setup(init_mode);
3162	#endif
3163
3164	for (i = 0; i < PARPORT_PC_MAX_PORTS && io[i]; i++) {
3165	if (parport_parse_irq(irq[i], &val))
3166	return 1;
3167	irqval[i] = val;
3168	if (parport_parse_dma(dma[i], &val))
3169	return 1;
3170	dmaval[i] = val;
3171	}
3172	if (!io[0]) {
3173	/* The user can make us use any IRQs or DMAs we find. */
3174	if (irq[0] && !parport_parse_irq(irq[0], &val))
3175	switch (val) {
3176	case PARPORT_IRQ_NONE:
3177	case PARPORT_IRQ_AUTO:
3178	irqval[0] = val;
3179	break;
3180	default:
3181	printk(KERN_WARNING
3182	"parport_pc: irq specified "
3183	"without base address. Use 'io=' "
3184	"to specify one\n");
3185	}
3186
3187	if (dma[0] && !parport_parse_dma(dma[0], &val))
3188	switch (val) {
3189	case PARPORT_DMA_NONE:
3190	case PARPORT_DMA_AUTO:
3191	dmaval[0] = val;
3192	break;
3193	default:
3194	printk(KERN_WARNING
3195	"parport_pc: dma specified "
3196	"without base address. Use 'io=' "
3197	"to specify one\n");
3198	}
3199	}
3200	return 0;
3201	}
3202
3203	#else
3204
3205	static int parport_setup_ptr __initdata;
3206
3207	/*
3208	* Acceptable parameters:
3209	*
3210	* parport=0
3211	* parport=auto
3212	* parport=0xBASE[,IRQ[,DMA]]
3213	*
3214	* IRQ/DMA may be numeric or 'auto' or 'none'
3215	*/
3216	static int __init parport_setup(char *str)
3217	{
3218	char *endptr;
3219	char *sep;
3220	int val;
3221
3222	if (!str \|\| !str \|\| (str == '0' && !*(str+1))) {
3223	/* Disable parport if "parport=0" in cmdline */
3224	io[0] = PARPORT_DISABLE;
3225	return 1;
3226	}
3227
3228	if (!strncmp(str, "auto", 4)) {
3229	irqval[0] = PARPORT_IRQ_AUTO;
3230	dmaval[0] = PARPORT_DMA_AUTO;
3231	return 1;
3232	}
3233
3234	val = simple_strtoul(str, &endptr, 0);
3235	if (endptr == str) {
3236	printk(KERN_WARNING "parport=%s not understood\n", str);
3237	return 1;
3238	}
3239
3240	if (parport_setup_ptr == PARPORT_PC_MAX_PORTS) {
3241	printk(KERN_ERR "parport=%s ignored, too many ports\n", str);
3242	return 1;
3243	}
3244
3245	io[parport_setup_ptr] = val;
3246	irqval[parport_setup_ptr] = PARPORT_IRQ_NONE;
3247	dmaval[parport_setup_ptr] = PARPORT_DMA_NONE;
3248
3249	sep = strchr(str, ',');
3250	if (sep++) {
3251	if (parport_parse_irq(sep, &val))
3252	return 1;
3253	irqval[parport_setup_ptr] = val;
3254	sep = strchr(sep, ',');
3255	if (sep++) {
3256	if (parport_parse_dma(sep, &val))
3257	return 1;
3258	dmaval[parport_setup_ptr] = val;
3259	}
3260	}
3261	parport_setup_ptr++;
3262	return 1;
3263	}
3264
3265	static int __init parse_parport_params(void)
3266	{
3267	return io[0] == PARPORT_DISABLE;
3268	}
3269
3270	__setup("parport=", parport_setup);
3271
3272	/*
3273	* Acceptable parameters:
3274	*
3275	* parport_init_mode=[spp\|ps2\|epp\|ecp\|ecpepp]
3276	*/
3277	#ifdef CONFIG_PCI
3278	__setup("parport_init_mode=", parport_init_mode_setup);
3279	#endif
3280	#endif
3281
3282	/* "Parser" ends here */
3283
3284	static int __init parport_pc_init(void)
3285	{
3286	int err;
3287
3288	if (parse_parport_params())
3289	return -EINVAL;
3290
3291	err = platform_driver_register(&parport_pc_platform_driver);
3292	if (err)
3293	return err;
3294
3295	if (io[0]) {
3296	int i;
3297	/* Only probe the ports we were given. */
3298	user_specified = 1;
3299	for (i = 0; i < PARPORT_PC_MAX_PORTS; i++) {
3300	if (!io[i])
3301	break;
3302	if (io_hi[i] == PARPORT_IOHI_AUTO)
3303	io_hi[i] = 0x400 + io[i];
3304	parport_pc_probe_port(io[i], io_hi[i],
3305	irqval[i], dmaval[i], NULL, 0);
3306	}
3307	} else
3308	parport_pc_find_ports(irqval[0], dmaval[0]);
3309
3310	return 0;
3311	}
3312
3313	static void __exit parport_pc_exit(void)
3314	{
3315	if (pci_registered_parport)
3316	pci_unregister_driver(&parport_pc_pci_driver);
3317	if (pnp_registered_parport)
3318	pnp_unregister_driver(&parport_pc_pnp_driver);
3319	platform_driver_unregister(&parport_pc_platform_driver);
3320
3321	while (!list_empty(&ports_list)) {
3322	struct parport_pc_private *priv;
3323	struct parport *port;
3324	priv = list_entry(ports_list.next,
3325	struct parport_pc_private, list);
3326	port = priv->port;
3327	if (port->dev && port->dev->bus == &platform_bus_type)
3328	platform_device_unregister(
3329	to_platform_device(port->dev));
3330	parport_pc_unregister_port(port);
3331	}
3332	}
3333
3334	MODULE_AUTHOR("Phil Blundell, Tim Waugh, others");
3335	MODULE_DESCRIPTION("PC-style parallel port driver");
3336	MODULE_LICENSE("GPL");
3337	module_init(parport_pc_init)
3338	module_exit(parport_pc_exit)
3339

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