Root/drivers/pci/pci.h

1#ifndef DRIVERS_PCI_H
2#define DRIVERS_PCI_H
3
4#include <linux/workqueue.h>
5
6#define PCI_CFG_SPACE_SIZE 256
7#define PCI_CFG_SPACE_EXP_SIZE 4096
8
9/* Functions internal to the PCI core code */
10
11extern int pci_uevent(struct device *dev, struct kobj_uevent_env *env);
12extern int pci_create_sysfs_dev_files(struct pci_dev *pdev);
13extern void pci_remove_sysfs_dev_files(struct pci_dev *pdev);
14#if !defined(CONFIG_DMI) && !defined(CONFIG_ACPI)
15static inline void pci_create_firmware_label_files(struct pci_dev *pdev)
16{ return; }
17static inline void pci_remove_firmware_label_files(struct pci_dev *pdev)
18{ return; }
19#else
20extern void pci_create_firmware_label_files(struct pci_dev *pdev);
21extern void pci_remove_firmware_label_files(struct pci_dev *pdev);
22#endif
23extern void pci_cleanup_rom(struct pci_dev *dev);
24#ifdef HAVE_PCI_MMAP
25enum pci_mmap_api {
26    PCI_MMAP_SYSFS, /* mmap on /sys/bus/pci/devices/<BDF>/resource<N> */
27    PCI_MMAP_PROCFS /* mmap on /proc/bus/pci/<BDF> */
28};
29extern int pci_mmap_fits(struct pci_dev *pdev, int resno,
30             struct vm_area_struct *vmai,
31             enum pci_mmap_api mmap_api);
32#endif
33int pci_probe_reset_function(struct pci_dev *dev);
34
35/**
36 * struct pci_platform_pm_ops - Firmware PM callbacks
37 *
38 * @is_manageable: returns 'true' if given device is power manageable by the
39 * platform firmware
40 *
41 * @set_state: invokes the platform firmware to set the device's power state
42 *
43 * @choose_state: returns PCI power state of given device preferred by the
44 * platform; to be used during system-wide transitions from a
45 * sleeping state to the working state and vice versa
46 *
47 * @can_wakeup: returns 'true' if given device is capable of waking up the
48 * system from a sleeping state
49 *
50 * @sleep_wake: enables/disables the system wake up capability of given device
51 *
52 * @run_wake: enables/disables the platform to generate run-time wake-up events
53 * for given device (the device's wake-up capability has to be
54 * enabled by @sleep_wake for this feature to work)
55 *
56 * If given platform is generally capable of power managing PCI devices, all of
57 * these callbacks are mandatory.
58 */
59struct pci_platform_pm_ops {
60    bool (*is_manageable)(struct pci_dev *dev);
61    int (*set_state)(struct pci_dev *dev, pci_power_t state);
62    pci_power_t (*choose_state)(struct pci_dev *dev);
63    bool (*can_wakeup)(struct pci_dev *dev);
64    int (*sleep_wake)(struct pci_dev *dev, bool enable);
65    int (*run_wake)(struct pci_dev *dev, bool enable);
66};
67
68extern int pci_set_platform_pm(struct pci_platform_pm_ops *ops);
69extern void pci_update_current_state(struct pci_dev *dev, pci_power_t state);
70extern void pci_power_up(struct pci_dev *dev);
71extern void pci_disable_enabled_device(struct pci_dev *dev);
72extern int pci_finish_runtime_suspend(struct pci_dev *dev);
73extern int __pci_pme_wakeup(struct pci_dev *dev, void *ign);
74extern void pci_wakeup_bus(struct pci_bus *bus);
75extern void pci_pm_init(struct pci_dev *dev);
76extern void platform_pci_wakeup_init(struct pci_dev *dev);
77extern void pci_allocate_cap_save_buffers(struct pci_dev *dev);
78void pci_free_cap_save_buffers(struct pci_dev *dev);
79
80static inline void pci_wakeup_event(struct pci_dev *dev)
81{
82    /* Wait 100 ms before the system can be put into a sleep state. */
83    pm_wakeup_event(&dev->dev, 100);
84}
85
86static inline bool pci_is_bridge(struct pci_dev *pci_dev)
87{
88    return !!(pci_dev->subordinate);
89}
90
91struct pci_vpd_ops {
92    ssize_t (*read)(struct pci_dev *dev, loff_t pos, size_t count, void *buf);
93    ssize_t (*write)(struct pci_dev *dev, loff_t pos, size_t count, const void *buf);
94    void (*release)(struct pci_dev *dev);
95};
96
97struct pci_vpd {
98    unsigned int len;
99    const struct pci_vpd_ops *ops;
100    struct bin_attribute *attr; /* descriptor for sysfs VPD entry */
101};
102
103extern int pci_vpd_pci22_init(struct pci_dev *dev);
104static inline void pci_vpd_release(struct pci_dev *dev)
105{
106    if (dev->vpd)
107        dev->vpd->ops->release(dev);
108}
109
110/* PCI /proc functions */
111#ifdef CONFIG_PROC_FS
112extern int pci_proc_attach_device(struct pci_dev *dev);
113extern int pci_proc_detach_device(struct pci_dev *dev);
114extern int pci_proc_detach_bus(struct pci_bus *bus);
115#else
116static inline int pci_proc_attach_device(struct pci_dev *dev) { return 0; }
117static inline int pci_proc_detach_device(struct pci_dev *dev) { return 0; }
118static inline int pci_proc_detach_bus(struct pci_bus *bus) { return 0; }
119#endif
120
121/* Functions for PCI Hotplug drivers to use */
122int pci_hp_add_bridge(struct pci_dev *dev);
123
124#ifdef HAVE_PCI_LEGACY
125extern void pci_create_legacy_files(struct pci_bus *bus);
126extern void pci_remove_legacy_files(struct pci_bus *bus);
127#else
128static inline void pci_create_legacy_files(struct pci_bus *bus) { return; }
129static inline void pci_remove_legacy_files(struct pci_bus *bus) { return; }
130#endif
131
132/* Lock for read/write access to pci device and bus lists */
133extern struct rw_semaphore pci_bus_sem;
134
135extern raw_spinlock_t pci_lock;
136
137extern unsigned int pci_pm_d3_delay;
138
139#ifdef CONFIG_PCI_MSI
140void pci_no_msi(void);
141extern void pci_msi_init_pci_dev(struct pci_dev *dev);
142#else
143static inline void pci_no_msi(void) { }
144static inline void pci_msi_init_pci_dev(struct pci_dev *dev) { }
145#endif
146
147void pci_realloc_get_opt(char *);
148
149static inline int pci_no_d1d2(struct pci_dev *dev)
150{
151    unsigned int parent_dstates = 0;
152
153    if (dev->bus->self)
154        parent_dstates = dev->bus->self->no_d1d2;
155    return (dev->no_d1d2 || parent_dstates);
156
157}
158extern struct device_attribute pci_dev_attrs[];
159extern struct device_attribute pcibus_dev_attrs[];
160#ifdef CONFIG_HOTPLUG
161extern struct bus_attribute pci_bus_attrs[];
162#else
163#define pci_bus_attrs NULL
164#endif
165
166
167/**
168 * pci_match_one_device - Tell if a PCI device structure has a matching
169 * PCI device id structure
170 * @id: single PCI device id structure to match
171 * @dev: the PCI device structure to match against
172 *
173 * Returns the matching pci_device_id structure or %NULL if there is no match.
174 */
175static inline const struct pci_device_id *
176pci_match_one_device(const struct pci_device_id *id, const struct pci_dev *dev)
177{
178    if ((id->vendor == PCI_ANY_ID || id->vendor == dev->vendor) &&
179        (id->device == PCI_ANY_ID || id->device == dev->device) &&
180        (id->subvendor == PCI_ANY_ID || id->subvendor == dev->subsystem_vendor) &&
181        (id->subdevice == PCI_ANY_ID || id->subdevice == dev->subsystem_device) &&
182        !((id->class ^ dev->class) & id->class_mask))
183        return id;
184    return NULL;
185}
186
187/* PCI slot sysfs helper code */
188#define to_pci_slot(s) container_of(s, struct pci_slot, kobj)
189
190extern struct kset *pci_slots_kset;
191
192struct pci_slot_attribute {
193    struct attribute attr;
194    ssize_t (*show)(struct pci_slot *, char *);
195    ssize_t (*store)(struct pci_slot *, const char *, size_t);
196};
197#define to_pci_slot_attr(s) container_of(s, struct pci_slot_attribute, attr)
198
199enum pci_bar_type {
200    pci_bar_unknown, /* Standard PCI BAR probe */
201    pci_bar_io, /* An io port BAR */
202    pci_bar_mem32, /* A 32-bit memory BAR */
203    pci_bar_mem64, /* A 64-bit memory BAR */
204};
205
206bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl,
207                int crs_timeout);
208extern int pci_setup_device(struct pci_dev *dev);
209extern int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
210                struct resource *res, unsigned int reg);
211extern int pci_resource_bar(struct pci_dev *dev, int resno,
212                enum pci_bar_type *type);
213extern int pci_bus_add_child(struct pci_bus *bus);
214extern void pci_enable_ari(struct pci_dev *dev);
215/**
216 * pci_ari_enabled - query ARI forwarding status
217 * @bus: the PCI bus
218 *
219 * Returns 1 if ARI forwarding is enabled, or 0 if not enabled;
220 */
221static inline int pci_ari_enabled(struct pci_bus *bus)
222{
223    return bus->self && bus->self->ari_enabled;
224}
225
226void pci_reassigndev_resource_alignment(struct pci_dev *dev);
227extern void pci_disable_bridge_window(struct pci_dev *dev);
228
229/* Single Root I/O Virtualization */
230struct pci_sriov {
231    int pos; /* capability position */
232    int nres; /* number of resources */
233    u32 cap; /* SR-IOV Capabilities */
234    u16 ctrl; /* SR-IOV Control */
235    u16 total; /* total VFs associated with the PF */
236    u16 initial; /* initial VFs associated with the PF */
237    u16 nr_virtfn; /* number of VFs available */
238    u16 offset; /* first VF Routing ID offset */
239    u16 stride; /* following VF stride */
240    u32 pgsz; /* page size for BAR alignment */
241    u8 link; /* Function Dependency Link */
242    struct pci_dev *dev; /* lowest numbered PF */
243    struct pci_dev *self; /* this PF */
244    struct mutex lock; /* lock for VF bus */
245    struct work_struct mtask; /* VF Migration task */
246    u8 __iomem *mstate; /* VF Migration State Array */
247};
248
249#ifdef CONFIG_PCI_ATS
250extern void pci_restore_ats_state(struct pci_dev *dev);
251#else
252static inline void pci_restore_ats_state(struct pci_dev *dev)
253{
254}
255#endif /* CONFIG_PCI_ATS */
256
257#ifdef CONFIG_PCI_IOV
258extern int pci_iov_init(struct pci_dev *dev);
259extern void pci_iov_release(struct pci_dev *dev);
260extern int pci_iov_resource_bar(struct pci_dev *dev, int resno,
261                enum pci_bar_type *type);
262extern resource_size_t pci_sriov_resource_alignment(struct pci_dev *dev,
263                            int resno);
264extern void pci_restore_iov_state(struct pci_dev *dev);
265extern int pci_iov_bus_range(struct pci_bus *bus);
266
267#else
268static inline int pci_iov_init(struct pci_dev *dev)
269{
270    return -ENODEV;
271}
272static inline void pci_iov_release(struct pci_dev *dev)
273
274{
275}
276static inline int pci_iov_resource_bar(struct pci_dev *dev, int resno,
277                       enum pci_bar_type *type)
278{
279    return 0;
280}
281static inline void pci_restore_iov_state(struct pci_dev *dev)
282{
283}
284static inline int pci_iov_bus_range(struct pci_bus *bus)
285{
286    return 0;
287}
288
289#endif /* CONFIG_PCI_IOV */
290
291extern unsigned long pci_cardbus_resource_alignment(struct resource *);
292
293static inline resource_size_t pci_resource_alignment(struct pci_dev *dev,
294                     struct resource *res)
295{
296#ifdef CONFIG_PCI_IOV
297    int resno = res - dev->resource;
298
299    if (resno >= PCI_IOV_RESOURCES && resno <= PCI_IOV_RESOURCE_END)
300        return pci_sriov_resource_alignment(dev, resno);
301#endif
302    if (dev->class >> 8 == PCI_CLASS_BRIDGE_CARDBUS)
303        return pci_cardbus_resource_alignment(res);
304    return resource_alignment(res);
305}
306
307extern void pci_enable_acs(struct pci_dev *dev);
308
309struct pci_dev_reset_methods {
310    u16 vendor;
311    u16 device;
312    int (*reset)(struct pci_dev *dev, int probe);
313};
314
315#ifdef CONFIG_PCI_QUIRKS
316extern int pci_dev_specific_reset(struct pci_dev *dev, int probe);
317#else
318static inline int pci_dev_specific_reset(struct pci_dev *dev, int probe)
319{
320    return -ENOTTY;
321}
322#endif
323
324#endif /* DRIVERS_PCI_H */
325

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