Root/
1 | /* |
2 | * drivers/pci/setup-bus.c |
3 | * |
4 | * Extruded from code written by |
5 | * Dave Rusling (david.rusling@reo.mts.dec.com) |
6 | * David Mosberger (davidm@cs.arizona.edu) |
7 | * David Miller (davem@redhat.com) |
8 | * |
9 | * Support routines for initializing a PCI subsystem. |
10 | */ |
11 | |
12 | /* |
13 | * Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru> |
14 | * PCI-PCI bridges cleanup, sorted resource allocation. |
15 | * Feb 2002, Ivan Kokshaysky <ink@jurassic.park.msu.ru> |
16 | * Converted to allocation in 3 passes, which gives |
17 | * tighter packing. Prefetchable range support. |
18 | */ |
19 | |
20 | #include <linux/init.h> |
21 | #include <linux/kernel.h> |
22 | #include <linux/module.h> |
23 | #include <linux/pci.h> |
24 | #include <linux/errno.h> |
25 | #include <linux/ioport.h> |
26 | #include <linux/cache.h> |
27 | #include <linux/slab.h> |
28 | #include <asm-generic/pci-bridge.h> |
29 | #include "pci.h" |
30 | |
31 | unsigned int pci_flags; |
32 | |
33 | struct pci_dev_resource { |
34 | struct list_head list; |
35 | struct resource *res; |
36 | struct pci_dev *dev; |
37 | resource_size_t start; |
38 | resource_size_t end; |
39 | resource_size_t add_size; |
40 | resource_size_t min_align; |
41 | unsigned long flags; |
42 | }; |
43 | |
44 | static void free_list(struct list_head *head) |
45 | { |
46 | struct pci_dev_resource *dev_res, *tmp; |
47 | |
48 | list_for_each_entry_safe(dev_res, tmp, head, list) { |
49 | list_del(&dev_res->list); |
50 | kfree(dev_res); |
51 | } |
52 | } |
53 | |
54 | /** |
55 | * add_to_list() - add a new resource tracker to the list |
56 | * @head: Head of the list |
57 | * @dev: device corresponding to which the resource |
58 | * belongs |
59 | * @res: The resource to be tracked |
60 | * @add_size: additional size to be optionally added |
61 | * to the resource |
62 | */ |
63 | static int add_to_list(struct list_head *head, |
64 | struct pci_dev *dev, struct resource *res, |
65 | resource_size_t add_size, resource_size_t min_align) |
66 | { |
67 | struct pci_dev_resource *tmp; |
68 | |
69 | tmp = kzalloc(sizeof(*tmp), GFP_KERNEL); |
70 | if (!tmp) { |
71 | pr_warning("add_to_list: kmalloc() failed!\n"); |
72 | return -ENOMEM; |
73 | } |
74 | |
75 | tmp->res = res; |
76 | tmp->dev = dev; |
77 | tmp->start = res->start; |
78 | tmp->end = res->end; |
79 | tmp->flags = res->flags; |
80 | tmp->add_size = add_size; |
81 | tmp->min_align = min_align; |
82 | |
83 | list_add(&tmp->list, head); |
84 | |
85 | return 0; |
86 | } |
87 | |
88 | static void remove_from_list(struct list_head *head, |
89 | struct resource *res) |
90 | { |
91 | struct pci_dev_resource *dev_res, *tmp; |
92 | |
93 | list_for_each_entry_safe(dev_res, tmp, head, list) { |
94 | if (dev_res->res == res) { |
95 | list_del(&dev_res->list); |
96 | kfree(dev_res); |
97 | break; |
98 | } |
99 | } |
100 | } |
101 | |
102 | static resource_size_t get_res_add_size(struct list_head *head, |
103 | struct resource *res) |
104 | { |
105 | struct pci_dev_resource *dev_res; |
106 | |
107 | list_for_each_entry(dev_res, head, list) { |
108 | if (dev_res->res == res) { |
109 | int idx = res - &dev_res->dev->resource[0]; |
110 | |
111 | dev_printk(KERN_DEBUG, &dev_res->dev->dev, |
112 | "res[%d]=%pR get_res_add_size add_size %llx\n", |
113 | idx, dev_res->res, |
114 | (unsigned long long)dev_res->add_size); |
115 | |
116 | return dev_res->add_size; |
117 | } |
118 | } |
119 | |
120 | return 0; |
121 | } |
122 | |
123 | /* Sort resources by alignment */ |
124 | static void pdev_sort_resources(struct pci_dev *dev, struct list_head *head) |
125 | { |
126 | int i; |
127 | |
128 | for (i = 0; i < PCI_NUM_RESOURCES; i++) { |
129 | struct resource *r; |
130 | struct pci_dev_resource *dev_res, *tmp; |
131 | resource_size_t r_align; |
132 | struct list_head *n; |
133 | |
134 | r = &dev->resource[i]; |
135 | |
136 | if (r->flags & IORESOURCE_PCI_FIXED) |
137 | continue; |
138 | |
139 | if (!(r->flags) || r->parent) |
140 | continue; |
141 | |
142 | r_align = pci_resource_alignment(dev, r); |
143 | if (!r_align) { |
144 | dev_warn(&dev->dev, "BAR %d: %pR has bogus alignment\n", |
145 | i, r); |
146 | continue; |
147 | } |
148 | |
149 | tmp = kzalloc(sizeof(*tmp), GFP_KERNEL); |
150 | if (!tmp) |
151 | panic("pdev_sort_resources(): " |
152 | "kmalloc() failed!\n"); |
153 | tmp->res = r; |
154 | tmp->dev = dev; |
155 | |
156 | /* fallback is smallest one or list is empty*/ |
157 | n = head; |
158 | list_for_each_entry(dev_res, head, list) { |
159 | resource_size_t align; |
160 | |
161 | align = pci_resource_alignment(dev_res->dev, |
162 | dev_res->res); |
163 | |
164 | if (r_align > align) { |
165 | n = &dev_res->list; |
166 | break; |
167 | } |
168 | } |
169 | /* Insert it just before n*/ |
170 | list_add_tail(&tmp->list, n); |
171 | } |
172 | } |
173 | |
174 | static void __dev_sort_resources(struct pci_dev *dev, |
175 | struct list_head *head) |
176 | { |
177 | u16 class = dev->class >> 8; |
178 | |
179 | /* Don't touch classless devices or host bridges or ioapics. */ |
180 | if (class == PCI_CLASS_NOT_DEFINED || class == PCI_CLASS_BRIDGE_HOST) |
181 | return; |
182 | |
183 | /* Don't touch ioapic devices already enabled by firmware */ |
184 | if (class == PCI_CLASS_SYSTEM_PIC) { |
185 | u16 command; |
186 | pci_read_config_word(dev, PCI_COMMAND, &command); |
187 | if (command & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) |
188 | return; |
189 | } |
190 | |
191 | pdev_sort_resources(dev, head); |
192 | } |
193 | |
194 | static inline void reset_resource(struct resource *res) |
195 | { |
196 | res->start = 0; |
197 | res->end = 0; |
198 | res->flags = 0; |
199 | } |
200 | |
201 | /** |
202 | * reassign_resources_sorted() - satisfy any additional resource requests |
203 | * |
204 | * @realloc_head : head of the list tracking requests requiring additional |
205 | * resources |
206 | * @head : head of the list tracking requests with allocated |
207 | * resources |
208 | * |
209 | * Walk through each element of the realloc_head and try to procure |
210 | * additional resources for the element, provided the element |
211 | * is in the head list. |
212 | */ |
213 | static void reassign_resources_sorted(struct list_head *realloc_head, |
214 | struct list_head *head) |
215 | { |
216 | struct resource *res; |
217 | struct pci_dev_resource *add_res, *tmp; |
218 | struct pci_dev_resource *dev_res; |
219 | resource_size_t add_size; |
220 | int idx; |
221 | |
222 | list_for_each_entry_safe(add_res, tmp, realloc_head, list) { |
223 | bool found_match = false; |
224 | |
225 | res = add_res->res; |
226 | /* skip resource that has been reset */ |
227 | if (!res->flags) |
228 | goto out; |
229 | |
230 | /* skip this resource if not found in head list */ |
231 | list_for_each_entry(dev_res, head, list) { |
232 | if (dev_res->res == res) { |
233 | found_match = true; |
234 | break; |
235 | } |
236 | } |
237 | if (!found_match)/* just skip */ |
238 | continue; |
239 | |
240 | idx = res - &add_res->dev->resource[0]; |
241 | add_size = add_res->add_size; |
242 | if (!resource_size(res)) { |
243 | res->start = add_res->start; |
244 | res->end = res->start + add_size - 1; |
245 | if (pci_assign_resource(add_res->dev, idx)) |
246 | reset_resource(res); |
247 | } else { |
248 | resource_size_t align = add_res->min_align; |
249 | res->flags |= add_res->flags & |
250 | (IORESOURCE_STARTALIGN|IORESOURCE_SIZEALIGN); |
251 | if (pci_reassign_resource(add_res->dev, idx, |
252 | add_size, align)) |
253 | dev_printk(KERN_DEBUG, &add_res->dev->dev, |
254 | "failed to add %llx res[%d]=%pR\n", |
255 | (unsigned long long)add_size, |
256 | idx, res); |
257 | } |
258 | out: |
259 | list_del(&add_res->list); |
260 | kfree(add_res); |
261 | } |
262 | } |
263 | |
264 | /** |
265 | * assign_requested_resources_sorted() - satisfy resource requests |
266 | * |
267 | * @head : head of the list tracking requests for resources |
268 | * @fail_head : head of the list tracking requests that could |
269 | * not be allocated |
270 | * |
271 | * Satisfy resource requests of each element in the list. Add |
272 | * requests that could not satisfied to the failed_list. |
273 | */ |
274 | static void assign_requested_resources_sorted(struct list_head *head, |
275 | struct list_head *fail_head) |
276 | { |
277 | struct resource *res; |
278 | struct pci_dev_resource *dev_res; |
279 | int idx; |
280 | |
281 | list_for_each_entry(dev_res, head, list) { |
282 | res = dev_res->res; |
283 | idx = res - &dev_res->dev->resource[0]; |
284 | if (resource_size(res) && |
285 | pci_assign_resource(dev_res->dev, idx)) { |
286 | if (fail_head && !pci_is_root_bus(dev_res->dev->bus)) { |
287 | /* |
288 | * if the failed res is for ROM BAR, and it will |
289 | * be enabled later, don't add it to the list |
290 | */ |
291 | if (!((idx == PCI_ROM_RESOURCE) && |
292 | (!(res->flags & IORESOURCE_ROM_ENABLE)))) |
293 | add_to_list(fail_head, |
294 | dev_res->dev, res, |
295 | 0 /* dont care */, |
296 | 0 /* dont care */); |
297 | } |
298 | reset_resource(res); |
299 | } |
300 | } |
301 | } |
302 | |
303 | static void __assign_resources_sorted(struct list_head *head, |
304 | struct list_head *realloc_head, |
305 | struct list_head *fail_head) |
306 | { |
307 | /* |
308 | * Should not assign requested resources at first. |
309 | * they could be adjacent, so later reassign can not reallocate |
310 | * them one by one in parent resource window. |
311 | * Try to assign requested + add_size at beginning |
312 | * if could do that, could get out early. |
313 | * if could not do that, we still try to assign requested at first, |
314 | * then try to reassign add_size for some resources. |
315 | */ |
316 | LIST_HEAD(save_head); |
317 | LIST_HEAD(local_fail_head); |
318 | struct pci_dev_resource *save_res; |
319 | struct pci_dev_resource *dev_res; |
320 | |
321 | /* Check if optional add_size is there */ |
322 | if (!realloc_head || list_empty(realloc_head)) |
323 | goto requested_and_reassign; |
324 | |
325 | /* Save original start, end, flags etc at first */ |
326 | list_for_each_entry(dev_res, head, list) { |
327 | if (add_to_list(&save_head, dev_res->dev, dev_res->res, 0, 0)) { |
328 | free_list(&save_head); |
329 | goto requested_and_reassign; |
330 | } |
331 | } |
332 | |
333 | /* Update res in head list with add_size in realloc_head list */ |
334 | list_for_each_entry(dev_res, head, list) |
335 | dev_res->res->end += get_res_add_size(realloc_head, |
336 | dev_res->res); |
337 | |
338 | /* Try updated head list with add_size added */ |
339 | assign_requested_resources_sorted(head, &local_fail_head); |
340 | |
341 | /* all assigned with add_size ? */ |
342 | if (list_empty(&local_fail_head)) { |
343 | /* Remove head list from realloc_head list */ |
344 | list_for_each_entry(dev_res, head, list) |
345 | remove_from_list(realloc_head, dev_res->res); |
346 | free_list(&save_head); |
347 | free_list(head); |
348 | return; |
349 | } |
350 | |
351 | free_list(&local_fail_head); |
352 | /* Release assigned resource */ |
353 | list_for_each_entry(dev_res, head, list) |
354 | if (dev_res->res->parent) |
355 | release_resource(dev_res->res); |
356 | /* Restore start/end/flags from saved list */ |
357 | list_for_each_entry(save_res, &save_head, list) { |
358 | struct resource *res = save_res->res; |
359 | |
360 | res->start = save_res->start; |
361 | res->end = save_res->end; |
362 | res->flags = save_res->flags; |
363 | } |
364 | free_list(&save_head); |
365 | |
366 | requested_and_reassign: |
367 | /* Satisfy the must-have resource requests */ |
368 | assign_requested_resources_sorted(head, fail_head); |
369 | |
370 | /* Try to satisfy any additional optional resource |
371 | requests */ |
372 | if (realloc_head) |
373 | reassign_resources_sorted(realloc_head, head); |
374 | free_list(head); |
375 | } |
376 | |
377 | static void pdev_assign_resources_sorted(struct pci_dev *dev, |
378 | struct list_head *add_head, |
379 | struct list_head *fail_head) |
380 | { |
381 | LIST_HEAD(head); |
382 | |
383 | __dev_sort_resources(dev, &head); |
384 | __assign_resources_sorted(&head, add_head, fail_head); |
385 | |
386 | } |
387 | |
388 | static void pbus_assign_resources_sorted(const struct pci_bus *bus, |
389 | struct list_head *realloc_head, |
390 | struct list_head *fail_head) |
391 | { |
392 | struct pci_dev *dev; |
393 | LIST_HEAD(head); |
394 | |
395 | list_for_each_entry(dev, &bus->devices, bus_list) |
396 | __dev_sort_resources(dev, &head); |
397 | |
398 | __assign_resources_sorted(&head, realloc_head, fail_head); |
399 | } |
400 | |
401 | void pci_setup_cardbus(struct pci_bus *bus) |
402 | { |
403 | struct pci_dev *bridge = bus->self; |
404 | struct resource *res; |
405 | struct pci_bus_region region; |
406 | |
407 | dev_info(&bridge->dev, "CardBus bridge to %pR\n", |
408 | &bus->busn_res); |
409 | |
410 | res = bus->resource[0]; |
411 | pcibios_resource_to_bus(bridge, ®ion, res); |
412 | if (res->flags & IORESOURCE_IO) { |
413 | /* |
414 | * The IO resource is allocated a range twice as large as it |
415 | * would normally need. This allows us to set both IO regs. |
416 | */ |
417 | dev_info(&bridge->dev, " bridge window %pR\n", res); |
418 | pci_write_config_dword(bridge, PCI_CB_IO_BASE_0, |
419 | region.start); |
420 | pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_0, |
421 | region.end); |
422 | } |
423 | |
424 | res = bus->resource[1]; |
425 | pcibios_resource_to_bus(bridge, ®ion, res); |
426 | if (res->flags & IORESOURCE_IO) { |
427 | dev_info(&bridge->dev, " bridge window %pR\n", res); |
428 | pci_write_config_dword(bridge, PCI_CB_IO_BASE_1, |
429 | region.start); |
430 | pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_1, |
431 | region.end); |
432 | } |
433 | |
434 | res = bus->resource[2]; |
435 | pcibios_resource_to_bus(bridge, ®ion, res); |
436 | if (res->flags & IORESOURCE_MEM) { |
437 | dev_info(&bridge->dev, " bridge window %pR\n", res); |
438 | pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_0, |
439 | region.start); |
440 | pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_0, |
441 | region.end); |
442 | } |
443 | |
444 | res = bus->resource[3]; |
445 | pcibios_resource_to_bus(bridge, ®ion, res); |
446 | if (res->flags & IORESOURCE_MEM) { |
447 | dev_info(&bridge->dev, " bridge window %pR\n", res); |
448 | pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_1, |
449 | region.start); |
450 | pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_1, |
451 | region.end); |
452 | } |
453 | } |
454 | EXPORT_SYMBOL(pci_setup_cardbus); |
455 | |
456 | /* Initialize bridges with base/limit values we have collected. |
457 | PCI-to-PCI Bridge Architecture Specification rev. 1.1 (1998) |
458 | requires that if there is no I/O ports or memory behind the |
459 | bridge, corresponding range must be turned off by writing base |
460 | value greater than limit to the bridge's base/limit registers. |
461 | |
462 | Note: care must be taken when updating I/O base/limit registers |
463 | of bridges which support 32-bit I/O. This update requires two |
464 | config space writes, so it's quite possible that an I/O window of |
465 | the bridge will have some undesirable address (e.g. 0) after the |
466 | first write. Ditto 64-bit prefetchable MMIO. */ |
467 | static void pci_setup_bridge_io(struct pci_bus *bus) |
468 | { |
469 | struct pci_dev *bridge = bus->self; |
470 | struct resource *res; |
471 | struct pci_bus_region region; |
472 | unsigned long io_mask; |
473 | u8 io_base_lo, io_limit_lo; |
474 | u32 l, io_upper16; |
475 | |
476 | io_mask = PCI_IO_RANGE_MASK; |
477 | if (bridge->io_window_1k) |
478 | io_mask = PCI_IO_1K_RANGE_MASK; |
479 | |
480 | /* Set up the top and bottom of the PCI I/O segment for this bus. */ |
481 | res = bus->resource[0]; |
482 | pcibios_resource_to_bus(bridge, ®ion, res); |
483 | if (res->flags & IORESOURCE_IO) { |
484 | pci_read_config_dword(bridge, PCI_IO_BASE, &l); |
485 | l &= 0xffff0000; |
486 | io_base_lo = (region.start >> 8) & io_mask; |
487 | io_limit_lo = (region.end >> 8) & io_mask; |
488 | l |= ((u32) io_limit_lo << 8) | io_base_lo; |
489 | /* Set up upper 16 bits of I/O base/limit. */ |
490 | io_upper16 = (region.end & 0xffff0000) | (region.start >> 16); |
491 | dev_info(&bridge->dev, " bridge window %pR\n", res); |
492 | } else { |
493 | /* Clear upper 16 bits of I/O base/limit. */ |
494 | io_upper16 = 0; |
495 | l = 0x00f0; |
496 | } |
497 | /* Temporarily disable the I/O range before updating PCI_IO_BASE. */ |
498 | pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, 0x0000ffff); |
499 | /* Update lower 16 bits of I/O base/limit. */ |
500 | pci_write_config_dword(bridge, PCI_IO_BASE, l); |
501 | /* Update upper 16 bits of I/O base/limit. */ |
502 | pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, io_upper16); |
503 | } |
504 | |
505 | static void pci_setup_bridge_mmio(struct pci_bus *bus) |
506 | { |
507 | struct pci_dev *bridge = bus->self; |
508 | struct resource *res; |
509 | struct pci_bus_region region; |
510 | u32 l; |
511 | |
512 | /* Set up the top and bottom of the PCI Memory segment for this bus. */ |
513 | res = bus->resource[1]; |
514 | pcibios_resource_to_bus(bridge, ®ion, res); |
515 | if (res->flags & IORESOURCE_MEM) { |
516 | l = (region.start >> 16) & 0xfff0; |
517 | l |= region.end & 0xfff00000; |
518 | dev_info(&bridge->dev, " bridge window %pR\n", res); |
519 | } else { |
520 | l = 0x0000fff0; |
521 | } |
522 | pci_write_config_dword(bridge, PCI_MEMORY_BASE, l); |
523 | } |
524 | |
525 | static void pci_setup_bridge_mmio_pref(struct pci_bus *bus) |
526 | { |
527 | struct pci_dev *bridge = bus->self; |
528 | struct resource *res; |
529 | struct pci_bus_region region; |
530 | u32 l, bu, lu; |
531 | |
532 | /* Clear out the upper 32 bits of PREF limit. |
533 | If PCI_PREF_BASE_UPPER32 was non-zero, this temporarily |
534 | disables PREF range, which is ok. */ |
535 | pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, 0); |
536 | |
537 | /* Set up PREF base/limit. */ |
538 | bu = lu = 0; |
539 | res = bus->resource[2]; |
540 | pcibios_resource_to_bus(bridge, ®ion, res); |
541 | if (res->flags & IORESOURCE_PREFETCH) { |
542 | l = (region.start >> 16) & 0xfff0; |
543 | l |= region.end & 0xfff00000; |
544 | if (res->flags & IORESOURCE_MEM_64) { |
545 | bu = upper_32_bits(region.start); |
546 | lu = upper_32_bits(region.end); |
547 | } |
548 | dev_info(&bridge->dev, " bridge window %pR\n", res); |
549 | } else { |
550 | l = 0x0000fff0; |
551 | } |
552 | pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, l); |
553 | |
554 | /* Set the upper 32 bits of PREF base & limit. */ |
555 | pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, bu); |
556 | pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, lu); |
557 | } |
558 | |
559 | static void __pci_setup_bridge(struct pci_bus *bus, unsigned long type) |
560 | { |
561 | struct pci_dev *bridge = bus->self; |
562 | |
563 | dev_info(&bridge->dev, "PCI bridge to %pR\n", |
564 | &bus->busn_res); |
565 | |
566 | if (type & IORESOURCE_IO) |
567 | pci_setup_bridge_io(bus); |
568 | |
569 | if (type & IORESOURCE_MEM) |
570 | pci_setup_bridge_mmio(bus); |
571 | |
572 | if (type & IORESOURCE_PREFETCH) |
573 | pci_setup_bridge_mmio_pref(bus); |
574 | |
575 | pci_write_config_word(bridge, PCI_BRIDGE_CONTROL, bus->bridge_ctl); |
576 | } |
577 | |
578 | void pci_setup_bridge(struct pci_bus *bus) |
579 | { |
580 | unsigned long type = IORESOURCE_IO | IORESOURCE_MEM | |
581 | IORESOURCE_PREFETCH; |
582 | |
583 | __pci_setup_bridge(bus, type); |
584 | } |
585 | |
586 | /* Check whether the bridge supports optional I/O and |
587 | prefetchable memory ranges. If not, the respective |
588 | base/limit registers must be read-only and read as 0. */ |
589 | static void pci_bridge_check_ranges(struct pci_bus *bus) |
590 | { |
591 | u16 io; |
592 | u32 pmem; |
593 | struct pci_dev *bridge = bus->self; |
594 | struct resource *b_res; |
595 | |
596 | b_res = &bridge->resource[PCI_BRIDGE_RESOURCES]; |
597 | b_res[1].flags |= IORESOURCE_MEM; |
598 | |
599 | pci_read_config_word(bridge, PCI_IO_BASE, &io); |
600 | if (!io) { |
601 | pci_write_config_word(bridge, PCI_IO_BASE, 0xf0f0); |
602 | pci_read_config_word(bridge, PCI_IO_BASE, &io); |
603 | pci_write_config_word(bridge, PCI_IO_BASE, 0x0); |
604 | } |
605 | if (io) |
606 | b_res[0].flags |= IORESOURCE_IO; |
607 | /* DECchip 21050 pass 2 errata: the bridge may miss an address |
608 | disconnect boundary by one PCI data phase. |
609 | Workaround: do not use prefetching on this device. */ |
610 | if (bridge->vendor == PCI_VENDOR_ID_DEC && bridge->device == 0x0001) |
611 | return; |
612 | pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem); |
613 | if (!pmem) { |
614 | pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, |
615 | 0xfff0fff0); |
616 | pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem); |
617 | pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, 0x0); |
618 | } |
619 | if (pmem) { |
620 | b_res[2].flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH; |
621 | if ((pmem & PCI_PREF_RANGE_TYPE_MASK) == |
622 | PCI_PREF_RANGE_TYPE_64) { |
623 | b_res[2].flags |= IORESOURCE_MEM_64; |
624 | b_res[2].flags |= PCI_PREF_RANGE_TYPE_64; |
625 | } |
626 | } |
627 | |
628 | /* double check if bridge does support 64 bit pref */ |
629 | if (b_res[2].flags & IORESOURCE_MEM_64) { |
630 | u32 mem_base_hi, tmp; |
631 | pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32, |
632 | &mem_base_hi); |
633 | pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, |
634 | 0xffffffff); |
635 | pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32, &tmp); |
636 | if (!tmp) |
637 | b_res[2].flags &= ~IORESOURCE_MEM_64; |
638 | pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, |
639 | mem_base_hi); |
640 | } |
641 | } |
642 | |
643 | /* Helper function for sizing routines: find first available |
644 | bus resource of a given type. Note: we intentionally skip |
645 | the bus resources which have already been assigned (that is, |
646 | have non-NULL parent resource). */ |
647 | static struct resource *find_free_bus_resource(struct pci_bus *bus, unsigned long type) |
648 | { |
649 | int i; |
650 | struct resource *r; |
651 | unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM | |
652 | IORESOURCE_PREFETCH; |
653 | |
654 | pci_bus_for_each_resource(bus, r, i) { |
655 | if (r == &ioport_resource || r == &iomem_resource) |
656 | continue; |
657 | if (r && (r->flags & type_mask) == type && !r->parent) |
658 | return r; |
659 | } |
660 | return NULL; |
661 | } |
662 | |
663 | static resource_size_t calculate_iosize(resource_size_t size, |
664 | resource_size_t min_size, |
665 | resource_size_t size1, |
666 | resource_size_t old_size, |
667 | resource_size_t align) |
668 | { |
669 | if (size < min_size) |
670 | size = min_size; |
671 | if (old_size == 1 ) |
672 | old_size = 0; |
673 | /* To be fixed in 2.5: we should have sort of HAVE_ISA |
674 | flag in the struct pci_bus. */ |
675 | #if defined(CONFIG_ISA) || defined(CONFIG_EISA) |
676 | size = (size & 0xff) + ((size & ~0xffUL) << 2); |
677 | #endif |
678 | size = ALIGN(size + size1, align); |
679 | if (size < old_size) |
680 | size = old_size; |
681 | return size; |
682 | } |
683 | |
684 | static resource_size_t calculate_memsize(resource_size_t size, |
685 | resource_size_t min_size, |
686 | resource_size_t size1, |
687 | resource_size_t old_size, |
688 | resource_size_t align) |
689 | { |
690 | if (size < min_size) |
691 | size = min_size; |
692 | if (old_size == 1 ) |
693 | old_size = 0; |
694 | if (size < old_size) |
695 | size = old_size; |
696 | size = ALIGN(size + size1, align); |
697 | return size; |
698 | } |
699 | |
700 | /** |
701 | * pbus_size_io() - size the io window of a given bus |
702 | * |
703 | * @bus : the bus |
704 | * @min_size : the minimum io window that must to be allocated |
705 | * @add_size : additional optional io window |
706 | * @realloc_head : track the additional io window on this list |
707 | * |
708 | * Sizing the IO windows of the PCI-PCI bridge is trivial, |
709 | * since these windows have 1K or 4K granularity and the IO ranges |
710 | * of non-bridge PCI devices are limited to 256 bytes. |
711 | * We must be careful with the ISA aliasing though. |
712 | */ |
713 | static void pbus_size_io(struct pci_bus *bus, resource_size_t min_size, |
714 | resource_size_t add_size, struct list_head *realloc_head) |
715 | { |
716 | struct pci_dev *dev; |
717 | struct resource *b_res = find_free_bus_resource(bus, IORESOURCE_IO); |
718 | unsigned long size = 0, size0 = 0, size1 = 0; |
719 | resource_size_t children_add_size = 0; |
720 | resource_size_t min_align = 4096, align; |
721 | |
722 | if (!b_res) |
723 | return; |
724 | |
725 | /* |
726 | * Per spec, I/O windows are 4K-aligned, but some bridges have an |
727 | * extension to support 1K alignment. |
728 | */ |
729 | if (bus->self->io_window_1k) |
730 | min_align = 1024; |
731 | list_for_each_entry(dev, &bus->devices, bus_list) { |
732 | int i; |
733 | |
734 | for (i = 0; i < PCI_NUM_RESOURCES; i++) { |
735 | struct resource *r = &dev->resource[i]; |
736 | unsigned long r_size; |
737 | |
738 | if (r->parent || !(r->flags & IORESOURCE_IO)) |
739 | continue; |
740 | r_size = resource_size(r); |
741 | |
742 | if (r_size < 0x400) |
743 | /* Might be re-aligned for ISA */ |
744 | size += r_size; |
745 | else |
746 | size1 += r_size; |
747 | |
748 | align = pci_resource_alignment(dev, r); |
749 | if (align > min_align) |
750 | min_align = align; |
751 | |
752 | if (realloc_head) |
753 | children_add_size += get_res_add_size(realloc_head, r); |
754 | } |
755 | } |
756 | |
757 | if (min_align > 4096) |
758 | min_align = 4096; |
759 | |
760 | size0 = calculate_iosize(size, min_size, size1, |
761 | resource_size(b_res), min_align); |
762 | if (children_add_size > add_size) |
763 | add_size = children_add_size; |
764 | size1 = (!realloc_head || (realloc_head && !add_size)) ? size0 : |
765 | calculate_iosize(size, min_size, add_size + size1, |
766 | resource_size(b_res), min_align); |
767 | if (!size0 && !size1) { |
768 | if (b_res->start || b_res->end) |
769 | dev_info(&bus->self->dev, "disabling bridge window " |
770 | "%pR to %pR (unused)\n", b_res, |
771 | &bus->busn_res); |
772 | b_res->flags = 0; |
773 | return; |
774 | } |
775 | |
776 | b_res->start = min_align; |
777 | b_res->end = b_res->start + size0 - 1; |
778 | b_res->flags |= IORESOURCE_STARTALIGN; |
779 | if (size1 > size0 && realloc_head) { |
780 | add_to_list(realloc_head, bus->self, b_res, size1-size0, |
781 | min_align); |
782 | dev_printk(KERN_DEBUG, &bus->self->dev, "bridge window " |
783 | "%pR to %pR add_size %lx\n", b_res, |
784 | &bus->busn_res, size1-size0); |
785 | } |
786 | } |
787 | |
788 | /** |
789 | * pbus_size_mem() - size the memory window of a given bus |
790 | * |
791 | * @bus : the bus |
792 | * @min_size : the minimum memory window that must to be allocated |
793 | * @add_size : additional optional memory window |
794 | * @realloc_head : track the additional memory window on this list |
795 | * |
796 | * Calculate the size of the bus and minimal alignment which |
797 | * guarantees that all child resources fit in this size. |
798 | */ |
799 | static int pbus_size_mem(struct pci_bus *bus, unsigned long mask, |
800 | unsigned long type, resource_size_t min_size, |
801 | resource_size_t add_size, |
802 | struct list_head *realloc_head) |
803 | { |
804 | struct pci_dev *dev; |
805 | resource_size_t min_align, align, size, size0, size1; |
806 | resource_size_t aligns[12]; /* Alignments from 1Mb to 2Gb */ |
807 | int order, max_order; |
808 | struct resource *b_res = find_free_bus_resource(bus, type); |
809 | unsigned int mem64_mask = 0; |
810 | resource_size_t children_add_size = 0; |
811 | |
812 | if (!b_res) |
813 | return 0; |
814 | |
815 | memset(aligns, 0, sizeof(aligns)); |
816 | max_order = 0; |
817 | size = 0; |
818 | |
819 | mem64_mask = b_res->flags & IORESOURCE_MEM_64; |
820 | b_res->flags &= ~IORESOURCE_MEM_64; |
821 | |
822 | list_for_each_entry(dev, &bus->devices, bus_list) { |
823 | int i; |
824 | |
825 | for (i = 0; i < PCI_NUM_RESOURCES; i++) { |
826 | struct resource *r = &dev->resource[i]; |
827 | resource_size_t r_size; |
828 | |
829 | if (r->parent || (r->flags & mask) != type) |
830 | continue; |
831 | r_size = resource_size(r); |
832 | #ifdef CONFIG_PCI_IOV |
833 | /* put SRIOV requested res to the optional list */ |
834 | if (realloc_head && i >= PCI_IOV_RESOURCES && |
835 | i <= PCI_IOV_RESOURCE_END) { |
836 | r->end = r->start - 1; |
837 | add_to_list(realloc_head, dev, r, r_size, 0/* dont' care */); |
838 | children_add_size += r_size; |
839 | continue; |
840 | } |
841 | #endif |
842 | /* For bridges size != alignment */ |
843 | align = pci_resource_alignment(dev, r); |
844 | order = __ffs(align) - 20; |
845 | if (order > 11) { |
846 | dev_warn(&dev->dev, "disabling BAR %d: %pR " |
847 | "(bad alignment %#llx)\n", i, r, |
848 | (unsigned long long) align); |
849 | r->flags = 0; |
850 | continue; |
851 | } |
852 | size += r_size; |
853 | if (order < 0) |
854 | order = 0; |
855 | /* Exclude ranges with size > align from |
856 | calculation of the alignment. */ |
857 | if (r_size == align) |
858 | aligns[order] += align; |
859 | if (order > max_order) |
860 | max_order = order; |
861 | mem64_mask &= r->flags & IORESOURCE_MEM_64; |
862 | |
863 | if (realloc_head) |
864 | children_add_size += get_res_add_size(realloc_head, r); |
865 | } |
866 | } |
867 | align = 0; |
868 | min_align = 0; |
869 | for (order = 0; order <= max_order; order++) { |
870 | resource_size_t align1 = 1; |
871 | |
872 | align1 <<= (order + 20); |
873 | |
874 | if (!align) |
875 | min_align = align1; |
876 | else if (ALIGN(align + min_align, min_align) < align1) |
877 | min_align = align1 >> 1; |
878 | align += aligns[order]; |
879 | } |
880 | size0 = calculate_memsize(size, min_size, 0, resource_size(b_res), min_align); |
881 | if (children_add_size > add_size) |
882 | add_size = children_add_size; |
883 | size1 = (!realloc_head || (realloc_head && !add_size)) ? size0 : |
884 | calculate_memsize(size, min_size, add_size, |
885 | resource_size(b_res), min_align); |
886 | if (!size0 && !size1) { |
887 | if (b_res->start || b_res->end) |
888 | dev_info(&bus->self->dev, "disabling bridge window " |
889 | "%pR to %pR (unused)\n", b_res, |
890 | &bus->busn_res); |
891 | b_res->flags = 0; |
892 | return 1; |
893 | } |
894 | b_res->start = min_align; |
895 | b_res->end = size0 + min_align - 1; |
896 | b_res->flags |= IORESOURCE_STARTALIGN | mem64_mask; |
897 | if (size1 > size0 && realloc_head) { |
898 | add_to_list(realloc_head, bus->self, b_res, size1-size0, min_align); |
899 | dev_printk(KERN_DEBUG, &bus->self->dev, "bridge window " |
900 | "%pR to %pR add_size %llx\n", b_res, |
901 | &bus->busn_res, (unsigned long long)size1-size0); |
902 | } |
903 | return 1; |
904 | } |
905 | |
906 | unsigned long pci_cardbus_resource_alignment(struct resource *res) |
907 | { |
908 | if (res->flags & IORESOURCE_IO) |
909 | return pci_cardbus_io_size; |
910 | if (res->flags & IORESOURCE_MEM) |
911 | return pci_cardbus_mem_size; |
912 | return 0; |
913 | } |
914 | |
915 | static void pci_bus_size_cardbus(struct pci_bus *bus, |
916 | struct list_head *realloc_head) |
917 | { |
918 | struct pci_dev *bridge = bus->self; |
919 | struct resource *b_res = &bridge->resource[PCI_BRIDGE_RESOURCES]; |
920 | resource_size_t b_res_3_size = pci_cardbus_mem_size * 2; |
921 | u16 ctrl; |
922 | |
923 | if (b_res[0].parent) |
924 | goto handle_b_res_1; |
925 | /* |
926 | * Reserve some resources for CardBus. We reserve |
927 | * a fixed amount of bus space for CardBus bridges. |
928 | */ |
929 | b_res[0].start = pci_cardbus_io_size; |
930 | b_res[0].end = b_res[0].start + pci_cardbus_io_size - 1; |
931 | b_res[0].flags |= IORESOURCE_IO | IORESOURCE_STARTALIGN; |
932 | if (realloc_head) { |
933 | b_res[0].end -= pci_cardbus_io_size; |
934 | add_to_list(realloc_head, bridge, b_res, pci_cardbus_io_size, |
935 | pci_cardbus_io_size); |
936 | } |
937 | |
938 | handle_b_res_1: |
939 | if (b_res[1].parent) |
940 | goto handle_b_res_2; |
941 | b_res[1].start = pci_cardbus_io_size; |
942 | b_res[1].end = b_res[1].start + pci_cardbus_io_size - 1; |
943 | b_res[1].flags |= IORESOURCE_IO | IORESOURCE_STARTALIGN; |
944 | if (realloc_head) { |
945 | b_res[1].end -= pci_cardbus_io_size; |
946 | add_to_list(realloc_head, bridge, b_res+1, pci_cardbus_io_size, |
947 | pci_cardbus_io_size); |
948 | } |
949 | |
950 | handle_b_res_2: |
951 | /* MEM1 must not be pref mmio */ |
952 | pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl); |
953 | if (ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM1) { |
954 | ctrl &= ~PCI_CB_BRIDGE_CTL_PREFETCH_MEM1; |
955 | pci_write_config_word(bridge, PCI_CB_BRIDGE_CONTROL, ctrl); |
956 | pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl); |
957 | } |
958 | |
959 | /* |
960 | * Check whether prefetchable memory is supported |
961 | * by this bridge. |
962 | */ |
963 | pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl); |
964 | if (!(ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0)) { |
965 | ctrl |= PCI_CB_BRIDGE_CTL_PREFETCH_MEM0; |
966 | pci_write_config_word(bridge, PCI_CB_BRIDGE_CONTROL, ctrl); |
967 | pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl); |
968 | } |
969 | |
970 | if (b_res[2].parent) |
971 | goto handle_b_res_3; |
972 | /* |
973 | * If we have prefetchable memory support, allocate |
974 | * two regions. Otherwise, allocate one region of |
975 | * twice the size. |
976 | */ |
977 | if (ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0) { |
978 | b_res[2].start = pci_cardbus_mem_size; |
979 | b_res[2].end = b_res[2].start + pci_cardbus_mem_size - 1; |
980 | b_res[2].flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH | |
981 | IORESOURCE_STARTALIGN; |
982 | if (realloc_head) { |
983 | b_res[2].end -= pci_cardbus_mem_size; |
984 | add_to_list(realloc_head, bridge, b_res+2, |
985 | pci_cardbus_mem_size, pci_cardbus_mem_size); |
986 | } |
987 | |
988 | /* reduce that to half */ |
989 | b_res_3_size = pci_cardbus_mem_size; |
990 | } |
991 | |
992 | handle_b_res_3: |
993 | if (b_res[3].parent) |
994 | goto handle_done; |
995 | b_res[3].start = pci_cardbus_mem_size; |
996 | b_res[3].end = b_res[3].start + b_res_3_size - 1; |
997 | b_res[3].flags |= IORESOURCE_MEM | IORESOURCE_STARTALIGN; |
998 | if (realloc_head) { |
999 | b_res[3].end -= b_res_3_size; |
1000 | add_to_list(realloc_head, bridge, b_res+3, b_res_3_size, |
1001 | pci_cardbus_mem_size); |
1002 | } |
1003 | |
1004 | handle_done: |
1005 | ; |
1006 | } |
1007 | |
1008 | void __ref __pci_bus_size_bridges(struct pci_bus *bus, |
1009 | struct list_head *realloc_head) |
1010 | { |
1011 | struct pci_dev *dev; |
1012 | unsigned long mask, prefmask; |
1013 | resource_size_t additional_mem_size = 0, additional_io_size = 0; |
1014 | |
1015 | list_for_each_entry(dev, &bus->devices, bus_list) { |
1016 | struct pci_bus *b = dev->subordinate; |
1017 | if (!b) |
1018 | continue; |
1019 | |
1020 | switch (dev->class >> 8) { |
1021 | case PCI_CLASS_BRIDGE_CARDBUS: |
1022 | pci_bus_size_cardbus(b, realloc_head); |
1023 | break; |
1024 | |
1025 | case PCI_CLASS_BRIDGE_PCI: |
1026 | default: |
1027 | __pci_bus_size_bridges(b, realloc_head); |
1028 | break; |
1029 | } |
1030 | } |
1031 | |
1032 | /* The root bus? */ |
1033 | if (!bus->self) |
1034 | return; |
1035 | |
1036 | switch (bus->self->class >> 8) { |
1037 | case PCI_CLASS_BRIDGE_CARDBUS: |
1038 | /* don't size cardbuses yet. */ |
1039 | break; |
1040 | |
1041 | case PCI_CLASS_BRIDGE_PCI: |
1042 | pci_bridge_check_ranges(bus); |
1043 | if (bus->self->is_hotplug_bridge) { |
1044 | additional_io_size = pci_hotplug_io_size; |
1045 | additional_mem_size = pci_hotplug_mem_size; |
1046 | } |
1047 | /* |
1048 | * Follow thru |
1049 | */ |
1050 | default: |
1051 | pbus_size_io(bus, realloc_head ? 0 : additional_io_size, |
1052 | additional_io_size, realloc_head); |
1053 | /* If the bridge supports prefetchable range, size it |
1054 | separately. If it doesn't, or its prefetchable window |
1055 | has already been allocated by arch code, try |
1056 | non-prefetchable range for both types of PCI memory |
1057 | resources. */ |
1058 | mask = IORESOURCE_MEM; |
1059 | prefmask = IORESOURCE_MEM | IORESOURCE_PREFETCH; |
1060 | if (pbus_size_mem(bus, prefmask, prefmask, |
1061 | realloc_head ? 0 : additional_mem_size, |
1062 | additional_mem_size, realloc_head)) |
1063 | mask = prefmask; /* Success, size non-prefetch only. */ |
1064 | else |
1065 | additional_mem_size += additional_mem_size; |
1066 | pbus_size_mem(bus, mask, IORESOURCE_MEM, |
1067 | realloc_head ? 0 : additional_mem_size, |
1068 | additional_mem_size, realloc_head); |
1069 | break; |
1070 | } |
1071 | } |
1072 | |
1073 | void __ref pci_bus_size_bridges(struct pci_bus *bus) |
1074 | { |
1075 | __pci_bus_size_bridges(bus, NULL); |
1076 | } |
1077 | EXPORT_SYMBOL(pci_bus_size_bridges); |
1078 | |
1079 | static void __ref __pci_bus_assign_resources(const struct pci_bus *bus, |
1080 | struct list_head *realloc_head, |
1081 | struct list_head *fail_head) |
1082 | { |
1083 | struct pci_bus *b; |
1084 | struct pci_dev *dev; |
1085 | |
1086 | pbus_assign_resources_sorted(bus, realloc_head, fail_head); |
1087 | |
1088 | list_for_each_entry(dev, &bus->devices, bus_list) { |
1089 | b = dev->subordinate; |
1090 | if (!b) |
1091 | continue; |
1092 | |
1093 | __pci_bus_assign_resources(b, realloc_head, fail_head); |
1094 | |
1095 | switch (dev->class >> 8) { |
1096 | case PCI_CLASS_BRIDGE_PCI: |
1097 | if (!pci_is_enabled(dev)) |
1098 | pci_setup_bridge(b); |
1099 | break; |
1100 | |
1101 | case PCI_CLASS_BRIDGE_CARDBUS: |
1102 | pci_setup_cardbus(b); |
1103 | break; |
1104 | |
1105 | default: |
1106 | dev_info(&dev->dev, "not setting up bridge for bus " |
1107 | "%04x:%02x\n", pci_domain_nr(b), b->number); |
1108 | break; |
1109 | } |
1110 | } |
1111 | } |
1112 | |
1113 | void __ref pci_bus_assign_resources(const struct pci_bus *bus) |
1114 | { |
1115 | __pci_bus_assign_resources(bus, NULL, NULL); |
1116 | } |
1117 | EXPORT_SYMBOL(pci_bus_assign_resources); |
1118 | |
1119 | static void __ref __pci_bridge_assign_resources(const struct pci_dev *bridge, |
1120 | struct list_head *add_head, |
1121 | struct list_head *fail_head) |
1122 | { |
1123 | struct pci_bus *b; |
1124 | |
1125 | pdev_assign_resources_sorted((struct pci_dev *)bridge, |
1126 | add_head, fail_head); |
1127 | |
1128 | b = bridge->subordinate; |
1129 | if (!b) |
1130 | return; |
1131 | |
1132 | __pci_bus_assign_resources(b, add_head, fail_head); |
1133 | |
1134 | switch (bridge->class >> 8) { |
1135 | case PCI_CLASS_BRIDGE_PCI: |
1136 | pci_setup_bridge(b); |
1137 | break; |
1138 | |
1139 | case PCI_CLASS_BRIDGE_CARDBUS: |
1140 | pci_setup_cardbus(b); |
1141 | break; |
1142 | |
1143 | default: |
1144 | dev_info(&bridge->dev, "not setting up bridge for bus " |
1145 | "%04x:%02x\n", pci_domain_nr(b), b->number); |
1146 | break; |
1147 | } |
1148 | } |
1149 | static void pci_bridge_release_resources(struct pci_bus *bus, |
1150 | unsigned long type) |
1151 | { |
1152 | int idx; |
1153 | bool changed = false; |
1154 | struct pci_dev *dev; |
1155 | struct resource *r; |
1156 | unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM | |
1157 | IORESOURCE_PREFETCH; |
1158 | |
1159 | dev = bus->self; |
1160 | for (idx = PCI_BRIDGE_RESOURCES; idx <= PCI_BRIDGE_RESOURCE_END; |
1161 | idx++) { |
1162 | r = &dev->resource[idx]; |
1163 | if ((r->flags & type_mask) != type) |
1164 | continue; |
1165 | if (!r->parent) |
1166 | continue; |
1167 | /* |
1168 | * if there are children under that, we should release them |
1169 | * all |
1170 | */ |
1171 | release_child_resources(r); |
1172 | if (!release_resource(r)) { |
1173 | dev_printk(KERN_DEBUG, &dev->dev, |
1174 | "resource %d %pR released\n", idx, r); |
1175 | /* keep the old size */ |
1176 | r->end = resource_size(r) - 1; |
1177 | r->start = 0; |
1178 | r->flags = 0; |
1179 | changed = true; |
1180 | } |
1181 | } |
1182 | |
1183 | if (changed) { |
1184 | /* avoiding touch the one without PREF */ |
1185 | if (type & IORESOURCE_PREFETCH) |
1186 | type = IORESOURCE_PREFETCH; |
1187 | __pci_setup_bridge(bus, type); |
1188 | } |
1189 | } |
1190 | |
1191 | enum release_type { |
1192 | leaf_only, |
1193 | whole_subtree, |
1194 | }; |
1195 | /* |
1196 | * try to release pci bridge resources that is from leaf bridge, |
1197 | * so we can allocate big new one later |
1198 | */ |
1199 | static void __ref pci_bus_release_bridge_resources(struct pci_bus *bus, |
1200 | unsigned long type, |
1201 | enum release_type rel_type) |
1202 | { |
1203 | struct pci_dev *dev; |
1204 | bool is_leaf_bridge = true; |
1205 | |
1206 | list_for_each_entry(dev, &bus->devices, bus_list) { |
1207 | struct pci_bus *b = dev->subordinate; |
1208 | if (!b) |
1209 | continue; |
1210 | |
1211 | is_leaf_bridge = false; |
1212 | |
1213 | if ((dev->class >> 8) != PCI_CLASS_BRIDGE_PCI) |
1214 | continue; |
1215 | |
1216 | if (rel_type == whole_subtree) |
1217 | pci_bus_release_bridge_resources(b, type, |
1218 | whole_subtree); |
1219 | } |
1220 | |
1221 | if (pci_is_root_bus(bus)) |
1222 | return; |
1223 | |
1224 | if ((bus->self->class >> 8) != PCI_CLASS_BRIDGE_PCI) |
1225 | return; |
1226 | |
1227 | if ((rel_type == whole_subtree) || is_leaf_bridge) |
1228 | pci_bridge_release_resources(bus, type); |
1229 | } |
1230 | |
1231 | static void pci_bus_dump_res(struct pci_bus *bus) |
1232 | { |
1233 | struct resource *res; |
1234 | int i; |
1235 | |
1236 | pci_bus_for_each_resource(bus, res, i) { |
1237 | if (!res || !res->end || !res->flags) |
1238 | continue; |
1239 | |
1240 | dev_printk(KERN_DEBUG, &bus->dev, "resource %d %pR\n", i, res); |
1241 | } |
1242 | } |
1243 | |
1244 | static void pci_bus_dump_resources(struct pci_bus *bus) |
1245 | { |
1246 | struct pci_bus *b; |
1247 | struct pci_dev *dev; |
1248 | |
1249 | |
1250 | pci_bus_dump_res(bus); |
1251 | |
1252 | list_for_each_entry(dev, &bus->devices, bus_list) { |
1253 | b = dev->subordinate; |
1254 | if (!b) |
1255 | continue; |
1256 | |
1257 | pci_bus_dump_resources(b); |
1258 | } |
1259 | } |
1260 | |
1261 | static int __init pci_bus_get_depth(struct pci_bus *bus) |
1262 | { |
1263 | int depth = 0; |
1264 | struct pci_dev *dev; |
1265 | |
1266 | list_for_each_entry(dev, &bus->devices, bus_list) { |
1267 | int ret; |
1268 | struct pci_bus *b = dev->subordinate; |
1269 | if (!b) |
1270 | continue; |
1271 | |
1272 | ret = pci_bus_get_depth(b); |
1273 | if (ret + 1 > depth) |
1274 | depth = ret + 1; |
1275 | } |
1276 | |
1277 | return depth; |
1278 | } |
1279 | static int __init pci_get_max_depth(void) |
1280 | { |
1281 | int depth = 0; |
1282 | struct pci_bus *bus; |
1283 | |
1284 | list_for_each_entry(bus, &pci_root_buses, node) { |
1285 | int ret; |
1286 | |
1287 | ret = pci_bus_get_depth(bus); |
1288 | if (ret > depth) |
1289 | depth = ret; |
1290 | } |
1291 | |
1292 | return depth; |
1293 | } |
1294 | |
1295 | /* |
1296 | * -1: undefined, will auto detect later |
1297 | * 0: disabled by user |
1298 | * 1: disabled by auto detect |
1299 | * 2: enabled by user |
1300 | * 3: enabled by auto detect |
1301 | */ |
1302 | enum enable_type { |
1303 | undefined = -1, |
1304 | user_disabled, |
1305 | auto_disabled, |
1306 | user_enabled, |
1307 | auto_enabled, |
1308 | }; |
1309 | |
1310 | static enum enable_type pci_realloc_enable __initdata = undefined; |
1311 | void __init pci_realloc_get_opt(char *str) |
1312 | { |
1313 | if (!strncmp(str, "off", 3)) |
1314 | pci_realloc_enable = user_disabled; |
1315 | else if (!strncmp(str, "on", 2)) |
1316 | pci_realloc_enable = user_enabled; |
1317 | } |
1318 | static bool __init pci_realloc_enabled(void) |
1319 | { |
1320 | return pci_realloc_enable >= user_enabled; |
1321 | } |
1322 | |
1323 | static void __init pci_realloc_detect(void) |
1324 | { |
1325 | #if defined(CONFIG_PCI_IOV) && defined(CONFIG_PCI_REALLOC_ENABLE_AUTO) |
1326 | struct pci_dev *dev = NULL; |
1327 | |
1328 | if (pci_realloc_enable != undefined) |
1329 | return; |
1330 | |
1331 | for_each_pci_dev(dev) { |
1332 | int i; |
1333 | |
1334 | for (i = PCI_IOV_RESOURCES; i <= PCI_IOV_RESOURCE_END; i++) { |
1335 | struct resource *r = &dev->resource[i]; |
1336 | |
1337 | /* Not assigned, or rejected by kernel ? */ |
1338 | if (r->flags && !r->start) { |
1339 | pci_realloc_enable = auto_enabled; |
1340 | |
1341 | return; |
1342 | } |
1343 | } |
1344 | } |
1345 | #endif |
1346 | } |
1347 | |
1348 | /* |
1349 | * first try will not touch pci bridge res |
1350 | * second and later try will clear small leaf bridge res |
1351 | * will stop till to the max deepth if can not find good one |
1352 | */ |
1353 | void __init |
1354 | pci_assign_unassigned_resources(void) |
1355 | { |
1356 | struct pci_bus *bus; |
1357 | LIST_HEAD(realloc_head); /* list of resources that |
1358 | want additional resources */ |
1359 | struct list_head *add_list = NULL; |
1360 | int tried_times = 0; |
1361 | enum release_type rel_type = leaf_only; |
1362 | LIST_HEAD(fail_head); |
1363 | struct pci_dev_resource *fail_res; |
1364 | unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM | |
1365 | IORESOURCE_PREFETCH; |
1366 | int pci_try_num = 1; |
1367 | |
1368 | /* don't realloc if asked to do so */ |
1369 | pci_realloc_detect(); |
1370 | if (pci_realloc_enabled()) { |
1371 | int max_depth = pci_get_max_depth(); |
1372 | |
1373 | pci_try_num = max_depth + 1; |
1374 | printk(KERN_DEBUG "PCI: max bus depth: %d pci_try_num: %d\n", |
1375 | max_depth, pci_try_num); |
1376 | } |
1377 | |
1378 | again: |
1379 | /* |
1380 | * last try will use add_list, otherwise will try good to have as |
1381 | * must have, so can realloc parent bridge resource |
1382 | */ |
1383 | if (tried_times + 1 == pci_try_num) |
1384 | add_list = &realloc_head; |
1385 | /* Depth first, calculate sizes and alignments of all |
1386 | subordinate buses. */ |
1387 | list_for_each_entry(bus, &pci_root_buses, node) |
1388 | __pci_bus_size_bridges(bus, add_list); |
1389 | |
1390 | /* Depth last, allocate resources and update the hardware. */ |
1391 | list_for_each_entry(bus, &pci_root_buses, node) |
1392 | __pci_bus_assign_resources(bus, add_list, &fail_head); |
1393 | if (add_list) |
1394 | BUG_ON(!list_empty(add_list)); |
1395 | tried_times++; |
1396 | |
1397 | /* any device complain? */ |
1398 | if (list_empty(&fail_head)) |
1399 | goto enable_and_dump; |
1400 | |
1401 | if (tried_times >= pci_try_num) { |
1402 | if (pci_realloc_enable == undefined) |
1403 | printk(KERN_INFO "Some PCI device resources are unassigned, try booting with pci=realloc\n"); |
1404 | else if (pci_realloc_enable == auto_enabled) |
1405 | printk(KERN_INFO "Automatically enabled pci realloc, if you have problem, try booting with pci=realloc=off\n"); |
1406 | |
1407 | free_list(&fail_head); |
1408 | goto enable_and_dump; |
1409 | } |
1410 | |
1411 | printk(KERN_DEBUG "PCI: No. %d try to assign unassigned res\n", |
1412 | tried_times + 1); |
1413 | |
1414 | /* third times and later will not check if it is leaf */ |
1415 | if ((tried_times + 1) > 2) |
1416 | rel_type = whole_subtree; |
1417 | |
1418 | /* |
1419 | * Try to release leaf bridge's resources that doesn't fit resource of |
1420 | * child device under that bridge |
1421 | */ |
1422 | list_for_each_entry(fail_res, &fail_head, list) { |
1423 | bus = fail_res->dev->bus; |
1424 | pci_bus_release_bridge_resources(bus, |
1425 | fail_res->flags & type_mask, |
1426 | rel_type); |
1427 | } |
1428 | /* restore size and flags */ |
1429 | list_for_each_entry(fail_res, &fail_head, list) { |
1430 | struct resource *res = fail_res->res; |
1431 | |
1432 | res->start = fail_res->start; |
1433 | res->end = fail_res->end; |
1434 | res->flags = fail_res->flags; |
1435 | if (fail_res->dev->subordinate) |
1436 | res->flags = 0; |
1437 | } |
1438 | free_list(&fail_head); |
1439 | |
1440 | goto again; |
1441 | |
1442 | enable_and_dump: |
1443 | /* Depth last, update the hardware. */ |
1444 | list_for_each_entry(bus, &pci_root_buses, node) |
1445 | pci_enable_bridges(bus); |
1446 | |
1447 | /* dump the resource on buses */ |
1448 | list_for_each_entry(bus, &pci_root_buses, node) |
1449 | pci_bus_dump_resources(bus); |
1450 | } |
1451 | |
1452 | void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge) |
1453 | { |
1454 | struct pci_bus *parent = bridge->subordinate; |
1455 | LIST_HEAD(add_list); /* list of resources that |
1456 | want additional resources */ |
1457 | int tried_times = 0; |
1458 | LIST_HEAD(fail_head); |
1459 | struct pci_dev_resource *fail_res; |
1460 | int retval; |
1461 | unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM | |
1462 | IORESOURCE_PREFETCH; |
1463 | |
1464 | again: |
1465 | __pci_bus_size_bridges(parent, &add_list); |
1466 | __pci_bridge_assign_resources(bridge, &add_list, &fail_head); |
1467 | BUG_ON(!list_empty(&add_list)); |
1468 | tried_times++; |
1469 | |
1470 | if (list_empty(&fail_head)) |
1471 | goto enable_all; |
1472 | |
1473 | if (tried_times >= 2) { |
1474 | /* still fail, don't need to try more */ |
1475 | free_list(&fail_head); |
1476 | goto enable_all; |
1477 | } |
1478 | |
1479 | printk(KERN_DEBUG "PCI: No. %d try to assign unassigned res\n", |
1480 | tried_times + 1); |
1481 | |
1482 | /* |
1483 | * Try to release leaf bridge's resources that doesn't fit resource of |
1484 | * child device under that bridge |
1485 | */ |
1486 | list_for_each_entry(fail_res, &fail_head, list) { |
1487 | struct pci_bus *bus = fail_res->dev->bus; |
1488 | unsigned long flags = fail_res->flags; |
1489 | |
1490 | pci_bus_release_bridge_resources(bus, flags & type_mask, |
1491 | whole_subtree); |
1492 | } |
1493 | /* restore size and flags */ |
1494 | list_for_each_entry(fail_res, &fail_head, list) { |
1495 | struct resource *res = fail_res->res; |
1496 | |
1497 | res->start = fail_res->start; |
1498 | res->end = fail_res->end; |
1499 | res->flags = fail_res->flags; |
1500 | if (fail_res->dev->subordinate) |
1501 | res->flags = 0; |
1502 | } |
1503 | free_list(&fail_head); |
1504 | |
1505 | goto again; |
1506 | |
1507 | enable_all: |
1508 | retval = pci_reenable_device(bridge); |
1509 | pci_set_master(bridge); |
1510 | pci_enable_bridges(parent); |
1511 | } |
1512 | EXPORT_SYMBOL_GPL(pci_assign_unassigned_bridge_resources); |
1513 | |
1514 | #ifdef CONFIG_HOTPLUG |
1515 | /** |
1516 | * pci_rescan_bus - scan a PCI bus for devices. |
1517 | * @bus: PCI bus to scan |
1518 | * |
1519 | * Scan a PCI bus and child buses for new devices, adds them, |
1520 | * and enables them. |
1521 | * |
1522 | * Returns the max number of subordinate bus discovered. |
1523 | */ |
1524 | unsigned int __ref pci_rescan_bus(struct pci_bus *bus) |
1525 | { |
1526 | unsigned int max; |
1527 | struct pci_dev *dev; |
1528 | LIST_HEAD(add_list); /* list of resources that |
1529 | want additional resources */ |
1530 | |
1531 | max = pci_scan_child_bus(bus); |
1532 | |
1533 | down_read(&pci_bus_sem); |
1534 | list_for_each_entry(dev, &bus->devices, bus_list) |
1535 | if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE || |
1536 | dev->hdr_type == PCI_HEADER_TYPE_CARDBUS) |
1537 | if (dev->subordinate) |
1538 | __pci_bus_size_bridges(dev->subordinate, |
1539 | &add_list); |
1540 | up_read(&pci_bus_sem); |
1541 | __pci_bus_assign_resources(bus, &add_list, NULL); |
1542 | BUG_ON(!list_empty(&add_list)); |
1543 | |
1544 | pci_enable_bridges(bus); |
1545 | pci_bus_add_devices(bus); |
1546 | |
1547 | return max; |
1548 | } |
1549 | EXPORT_SYMBOL_GPL(pci_rescan_bus); |
1550 | #endif |
1551 |
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