Root/drivers/pinctrl/pinctrl-sirf.c

1/*
2 * pinmux driver for CSR SiRFprimaII
3 *
4 * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
5 *
6 * Licensed under GPLv2 or later.
7 */
8
9#include <linux/init.h>
10#include <linux/module.h>
11#include <linux/irq.h>
12#include <linux/platform_device.h>
13#include <linux/io.h>
14#include <linux/slab.h>
15#include <linux/err.h>
16#include <linux/irqdomain.h>
17#include <linux/pinctrl/pinctrl.h>
18#include <linux/pinctrl/pinmux.h>
19#include <linux/pinctrl/consumer.h>
20#include <linux/of.h>
21#include <linux/of_address.h>
22#include <linux/of_device.h>
23#include <linux/of_platform.h>
24#include <linux/bitops.h>
25#include <linux/gpio.h>
26#include <linux/of_gpio.h>
27
28#define DRIVER_NAME "pinmux-sirf"
29
30#define SIRFSOC_NUM_PADS 622
31#define SIRFSOC_RSC_PIN_MUX 0x4
32
33#define SIRFSOC_GPIO_PAD_EN(g) ((g)*0x100 + 0x84)
34#define SIRFSOC_GPIO_CTRL(g, i) ((g)*0x100 + (i)*4)
35#define SIRFSOC_GPIO_DSP_EN0 (0x80)
36#define SIRFSOC_GPIO_PAD_EN(g) ((g)*0x100 + 0x84)
37#define SIRFSOC_GPIO_INT_STATUS(g) ((g)*0x100 + 0x8C)
38
39#define SIRFSOC_GPIO_CTL_INTR_LOW_MASK 0x1
40#define SIRFSOC_GPIO_CTL_INTR_HIGH_MASK 0x2
41#define SIRFSOC_GPIO_CTL_INTR_TYPE_MASK 0x4
42#define SIRFSOC_GPIO_CTL_INTR_EN_MASK 0x8
43#define SIRFSOC_GPIO_CTL_INTR_STS_MASK 0x10
44#define SIRFSOC_GPIO_CTL_OUT_EN_MASK 0x20
45#define SIRFSOC_GPIO_CTL_DATAOUT_MASK 0x40
46#define SIRFSOC_GPIO_CTL_DATAIN_MASK 0x80
47#define SIRFSOC_GPIO_CTL_PULL_MASK 0x100
48#define SIRFSOC_GPIO_CTL_PULL_HIGH 0x200
49#define SIRFSOC_GPIO_CTL_DSP_INT 0x400
50
51#define SIRFSOC_GPIO_NO_OF_BANKS 5
52#define SIRFSOC_GPIO_BANK_SIZE 32
53#define SIRFSOC_GPIO_NUM(bank, index) (((bank)*(32)) + (index))
54
55struct sirfsoc_gpio_bank {
56    struct of_mm_gpio_chip chip;
57    struct irq_domain *domain;
58    int id;
59    int parent_irq;
60    spinlock_t lock;
61};
62
63static struct sirfsoc_gpio_bank sgpio_bank[SIRFSOC_GPIO_NO_OF_BANKS];
64static DEFINE_SPINLOCK(sgpio_lock);
65
66/*
67 * pad list for the pinmux subsystem
68 * refer to CS-131858-DC-6A.xls
69 */
70static const struct pinctrl_pin_desc sirfsoc_pads[] = {
71    PINCTRL_PIN(4, "pwm0"),
72    PINCTRL_PIN(5, "pwm1"),
73    PINCTRL_PIN(6, "pwm2"),
74    PINCTRL_PIN(7, "pwm3"),
75    PINCTRL_PIN(8, "warm_rst_b"),
76    PINCTRL_PIN(9, "odo_0"),
77    PINCTRL_PIN(10, "odo_1"),
78    PINCTRL_PIN(11, "dr_dir"),
79    PINCTRL_PIN(13, "scl_1"),
80    PINCTRL_PIN(15, "sda_1"),
81    PINCTRL_PIN(16, "x_ldd[16]"),
82    PINCTRL_PIN(17, "x_ldd[17]"),
83    PINCTRL_PIN(18, "x_ldd[18]"),
84    PINCTRL_PIN(19, "x_ldd[19]"),
85    PINCTRL_PIN(20, "x_ldd[20]"),
86    PINCTRL_PIN(21, "x_ldd[21]"),
87    PINCTRL_PIN(22, "x_ldd[22]"),
88    PINCTRL_PIN(23, "x_ldd[23], lcdrom_frdy"),
89    PINCTRL_PIN(24, "gps_sgn"),
90    PINCTRL_PIN(25, "gps_mag"),
91    PINCTRL_PIN(26, "gps_clk"),
92    PINCTRL_PIN(27, "sd_cd_b_1"),
93    PINCTRL_PIN(28, "sd_vcc_on_1"),
94    PINCTRL_PIN(29, "sd_wp_b_1"),
95    PINCTRL_PIN(30, "sd_clk_3"),
96    PINCTRL_PIN(31, "sd_cmd_3"),
97
98    PINCTRL_PIN(32, "x_sd_dat_3[0]"),
99    PINCTRL_PIN(33, "x_sd_dat_3[1]"),
100    PINCTRL_PIN(34, "x_sd_dat_3[2]"),
101    PINCTRL_PIN(35, "x_sd_dat_3[3]"),
102    PINCTRL_PIN(36, "x_sd_clk_4"),
103    PINCTRL_PIN(37, "x_sd_cmd_4"),
104    PINCTRL_PIN(38, "x_sd_dat_4[0]"),
105    PINCTRL_PIN(39, "x_sd_dat_4[1]"),
106    PINCTRL_PIN(40, "x_sd_dat_4[2]"),
107    PINCTRL_PIN(41, "x_sd_dat_4[3]"),
108    PINCTRL_PIN(42, "x_cko_1"),
109    PINCTRL_PIN(43, "x_ac97_bit_clk"),
110    PINCTRL_PIN(44, "x_ac97_dout"),
111    PINCTRL_PIN(45, "x_ac97_din"),
112    PINCTRL_PIN(46, "x_ac97_sync"),
113    PINCTRL_PIN(47, "x_txd_1"),
114    PINCTRL_PIN(48, "x_txd_2"),
115    PINCTRL_PIN(49, "x_rxd_1"),
116    PINCTRL_PIN(50, "x_rxd_2"),
117    PINCTRL_PIN(51, "x_usclk_0"),
118    PINCTRL_PIN(52, "x_utxd_0"),
119    PINCTRL_PIN(53, "x_urxd_0"),
120    PINCTRL_PIN(54, "x_utfs_0"),
121    PINCTRL_PIN(55, "x_urfs_0"),
122    PINCTRL_PIN(56, "x_usclk_1"),
123    PINCTRL_PIN(57, "x_utxd_1"),
124    PINCTRL_PIN(58, "x_urxd_1"),
125    PINCTRL_PIN(59, "x_utfs_1"),
126    PINCTRL_PIN(60, "x_urfs_1"),
127    PINCTRL_PIN(61, "x_usclk_2"),
128    PINCTRL_PIN(62, "x_utxd_2"),
129    PINCTRL_PIN(63, "x_urxd_2"),
130
131    PINCTRL_PIN(64, "x_utfs_2"),
132    PINCTRL_PIN(65, "x_urfs_2"),
133    PINCTRL_PIN(66, "x_df_we_b"),
134    PINCTRL_PIN(67, "x_df_re_b"),
135    PINCTRL_PIN(68, "x_txd_0"),
136    PINCTRL_PIN(69, "x_rxd_0"),
137    PINCTRL_PIN(78, "x_cko_0"),
138    PINCTRL_PIN(79, "x_vip_pxd[7]"),
139    PINCTRL_PIN(80, "x_vip_pxd[6]"),
140    PINCTRL_PIN(81, "x_vip_pxd[5]"),
141    PINCTRL_PIN(82, "x_vip_pxd[4]"),
142    PINCTRL_PIN(83, "x_vip_pxd[3]"),
143    PINCTRL_PIN(84, "x_vip_pxd[2]"),
144    PINCTRL_PIN(85, "x_vip_pxd[1]"),
145    PINCTRL_PIN(86, "x_vip_pxd[0]"),
146    PINCTRL_PIN(87, "x_vip_vsync"),
147    PINCTRL_PIN(88, "x_vip_hsync"),
148    PINCTRL_PIN(89, "x_vip_pxclk"),
149    PINCTRL_PIN(90, "x_sda_0"),
150    PINCTRL_PIN(91, "x_scl_0"),
151    PINCTRL_PIN(92, "x_df_ry_by"),
152    PINCTRL_PIN(93, "x_df_cs_b[1]"),
153    PINCTRL_PIN(94, "x_df_cs_b[0]"),
154    PINCTRL_PIN(95, "x_l_pclk"),
155
156    PINCTRL_PIN(96, "x_l_lck"),
157    PINCTRL_PIN(97, "x_l_fck"),
158    PINCTRL_PIN(98, "x_l_de"),
159    PINCTRL_PIN(99, "x_ldd[0]"),
160    PINCTRL_PIN(100, "x_ldd[1]"),
161    PINCTRL_PIN(101, "x_ldd[2]"),
162    PINCTRL_PIN(102, "x_ldd[3]"),
163    PINCTRL_PIN(103, "x_ldd[4]"),
164    PINCTRL_PIN(104, "x_ldd[5]"),
165    PINCTRL_PIN(105, "x_ldd[6]"),
166    PINCTRL_PIN(106, "x_ldd[7]"),
167    PINCTRL_PIN(107, "x_ldd[8]"),
168    PINCTRL_PIN(108, "x_ldd[9]"),
169    PINCTRL_PIN(109, "x_ldd[10]"),
170    PINCTRL_PIN(110, "x_ldd[11]"),
171    PINCTRL_PIN(111, "x_ldd[12]"),
172    PINCTRL_PIN(112, "x_ldd[13]"),
173    PINCTRL_PIN(113, "x_ldd[14]"),
174    PINCTRL_PIN(114, "x_ldd[15]"),
175};
176
177/**
178 * @dev: a pointer back to containing device
179 * @virtbase: the offset to the controller in virtual memory
180 */
181struct sirfsoc_pmx {
182    struct device *dev;
183    struct pinctrl_dev *pmx;
184    void __iomem *gpio_virtbase;
185    void __iomem *rsc_virtbase;
186};
187
188/* SIRFSOC_GPIO_PAD_EN set */
189struct sirfsoc_muxmask {
190    unsigned long group;
191    unsigned long mask;
192};
193
194struct sirfsoc_padmux {
195    unsigned long muxmask_counts;
196    const struct sirfsoc_muxmask *muxmask;
197    /* RSC_PIN_MUX set */
198    unsigned long funcmask;
199    unsigned long funcval;
200};
201
202 /**
203 * struct sirfsoc_pin_group - describes a SiRFprimaII pin group
204 * @name: the name of this specific pin group
205 * @pins: an array of discrete physical pins used in this group, taken
206 * from the driver-local pin enumeration space
207 * @num_pins: the number of pins in this group array, i.e. the number of
208 * elements in .pins so we can iterate over that array
209 */
210struct sirfsoc_pin_group {
211    const char *name;
212    const unsigned int *pins;
213    const unsigned num_pins;
214};
215
216static const struct sirfsoc_muxmask lcd_16bits_sirfsoc_muxmask[] = {
217    {
218        .group = 3,
219        .mask = BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(6) | BIT(7) | BIT(8) |
220            BIT(9) | BIT(10) | BIT(11) | BIT(12) | BIT(13) | BIT(14) | BIT(15) | BIT(16) |
221            BIT(17) | BIT(18),
222    }, {
223        .group = 2,
224        .mask = BIT(31),
225    },
226};
227
228static const struct sirfsoc_padmux lcd_16bits_padmux = {
229    .muxmask_counts = ARRAY_SIZE(lcd_16bits_sirfsoc_muxmask),
230    .muxmask = lcd_16bits_sirfsoc_muxmask,
231    .funcmask = BIT(4),
232    .funcval = 0,
233};
234
235static const unsigned lcd_16bits_pins[] = { 95, 96, 97, 98, 99, 100, 101, 102, 103, 104,
236    105, 106, 107, 108, 109, 110, 111, 112, 113, 114 };
237
238static const struct sirfsoc_muxmask lcd_18bits_muxmask[] = {
239    {
240        .group = 3,
241        .mask = BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(6) | BIT(7) | BIT(8) |
242            BIT(9) | BIT(10) | BIT(11) | BIT(12) | BIT(13) | BIT(14) | BIT(15) | BIT(16) |
243            BIT(17) | BIT(18),
244    }, {
245        .group = 2,
246        .mask = BIT(31),
247    }, {
248        .group = 0,
249        .mask = BIT(16) | BIT(17),
250    },
251};
252
253static const struct sirfsoc_padmux lcd_18bits_padmux = {
254    .muxmask_counts = ARRAY_SIZE(lcd_18bits_muxmask),
255    .muxmask = lcd_18bits_muxmask,
256    .funcmask = BIT(4),
257    .funcval = 0,
258};
259
260static const unsigned lcd_18bits_pins[] = { 16, 17, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104,
261    105, 106, 107, 108, 109, 110, 111, 112, 113, 114};
262
263static const struct sirfsoc_muxmask lcd_24bits_muxmask[] = {
264    {
265        .group = 3,
266        .mask = BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(6) | BIT(7) | BIT(8) |
267            BIT(9) | BIT(10) | BIT(11) | BIT(12) | BIT(13) | BIT(14) | BIT(15) | BIT(16) |
268            BIT(17) | BIT(18),
269    }, {
270        .group = 2,
271        .mask = BIT(31),
272    }, {
273        .group = 0,
274        .mask = BIT(16) | BIT(17) | BIT(18) | BIT(19) | BIT(20) | BIT(21) | BIT(22) | BIT(23),
275    },
276};
277
278static const struct sirfsoc_padmux lcd_24bits_padmux = {
279    .muxmask_counts = ARRAY_SIZE(lcd_24bits_muxmask),
280    .muxmask = lcd_24bits_muxmask,
281    .funcmask = BIT(4),
282    .funcval = 0,
283};
284
285static const unsigned lcd_24bits_pins[] = { 16, 17, 18, 19, 20, 21, 22, 23, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104,
286    105, 106, 107, 108, 109, 110, 111, 112, 113, 114 };
287
288static const struct sirfsoc_muxmask lcdrom_muxmask[] = {
289    {
290        .group = 3,
291        .mask = BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(6) | BIT(7) | BIT(8) |
292            BIT(9) | BIT(10) | BIT(11) | BIT(12) | BIT(13) | BIT(14) | BIT(15) | BIT(16) |
293            BIT(17) | BIT(18),
294    }, {
295        .group = 2,
296        .mask = BIT(31),
297    }, {
298        .group = 0,
299        .mask = BIT(23),
300    },
301};
302
303static const struct sirfsoc_padmux lcdrom_padmux = {
304    .muxmask_counts = ARRAY_SIZE(lcdrom_muxmask),
305    .muxmask = lcdrom_muxmask,
306    .funcmask = BIT(4),
307    .funcval = BIT(4),
308};
309
310static const unsigned lcdrom_pins[] = { 23, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104,
311    105, 106, 107, 108, 109, 110, 111, 112, 113, 114 };
312
313static const struct sirfsoc_muxmask uart0_muxmask[] = {
314    {
315        .group = 2,
316        .mask = BIT(4) | BIT(5),
317    }, {
318        .group = 1,
319        .mask = BIT(23) | BIT(28),
320    },
321};
322
323static const struct sirfsoc_padmux uart0_padmux = {
324    .muxmask_counts = ARRAY_SIZE(uart0_muxmask),
325    .muxmask = uart0_muxmask,
326    .funcmask = BIT(9),
327    .funcval = BIT(9),
328};
329
330static const unsigned uart0_pins[] = { 55, 60, 68, 69 };
331
332static const struct sirfsoc_muxmask uart0_nostreamctrl_muxmask[] = {
333    {
334        .group = 2,
335        .mask = BIT(4) | BIT(5),
336    },
337};
338
339static const struct sirfsoc_padmux uart0_nostreamctrl_padmux = {
340    .muxmask_counts = ARRAY_SIZE(uart0_nostreamctrl_muxmask),
341    .muxmask = uart0_nostreamctrl_muxmask,
342};
343
344static const unsigned uart0_nostreamctrl_pins[] = { 68, 39 };
345
346static const struct sirfsoc_muxmask uart1_muxmask[] = {
347    {
348        .group = 1,
349        .mask = BIT(15) | BIT(17),
350    },
351};
352
353static const struct sirfsoc_padmux uart1_padmux = {
354    .muxmask_counts = ARRAY_SIZE(uart1_muxmask),
355    .muxmask = uart1_muxmask,
356};
357
358static const unsigned uart1_pins[] = { 47, 49 };
359
360static const struct sirfsoc_muxmask uart2_muxmask[] = {
361    {
362        .group = 1,
363        .mask = BIT(16) | BIT(18) | BIT(24) | BIT(27),
364    },
365};
366
367static const struct sirfsoc_padmux uart2_padmux = {
368    .muxmask_counts = ARRAY_SIZE(uart2_muxmask),
369    .muxmask = uart2_muxmask,
370    .funcmask = BIT(10),
371    .funcval = BIT(10),
372};
373
374static const unsigned uart2_pins[] = { 48, 50, 56, 59 };
375
376static const struct sirfsoc_muxmask uart2_nostreamctrl_muxmask[] = {
377    {
378        .group = 1,
379        .mask = BIT(16) | BIT(18),
380    },
381};
382
383static const struct sirfsoc_padmux uart2_nostreamctrl_padmux = {
384    .muxmask_counts = ARRAY_SIZE(uart2_nostreamctrl_muxmask),
385    .muxmask = uart2_nostreamctrl_muxmask,
386};
387
388static const unsigned uart2_nostreamctrl_pins[] = { 48, 50 };
389
390static const struct sirfsoc_muxmask sdmmc3_muxmask[] = {
391    {
392        .group = 0,
393        .mask = BIT(30) | BIT(31),
394    }, {
395        .group = 1,
396        .mask = BIT(0) | BIT(1) | BIT(2) | BIT(3),
397    },
398};
399
400static const struct sirfsoc_padmux sdmmc3_padmux = {
401    .muxmask_counts = ARRAY_SIZE(sdmmc3_muxmask),
402    .muxmask = sdmmc3_muxmask,
403    .funcmask = BIT(7),
404    .funcval = 0,
405};
406
407static const unsigned sdmmc3_pins[] = { 30, 31, 32, 33, 34, 35 };
408
409static const struct sirfsoc_muxmask spi0_muxmask[] = {
410    {
411        .group = 1,
412        .mask = BIT(0) | BIT(1) | BIT(2) | BIT(3),
413    },
414};
415
416static const struct sirfsoc_padmux spi0_padmux = {
417    .muxmask_counts = ARRAY_SIZE(spi0_muxmask),
418    .muxmask = spi0_muxmask,
419    .funcmask = BIT(7),
420    .funcval = BIT(7),
421};
422
423static const unsigned spi0_pins[] = { 32, 33, 34, 35 };
424
425static const struct sirfsoc_muxmask sdmmc4_muxmask[] = {
426    {
427        .group = 1,
428        .mask = BIT(4) | BIT(5) | BIT(6) | BIT(7) | BIT(8) | BIT(9),
429    },
430};
431
432static const struct sirfsoc_padmux sdmmc4_padmux = {
433    .muxmask_counts = ARRAY_SIZE(sdmmc4_muxmask),
434    .muxmask = sdmmc4_muxmask,
435};
436
437static const unsigned sdmmc4_pins[] = { 36, 37, 38, 39, 40, 41 };
438
439static const struct sirfsoc_muxmask cko1_muxmask[] = {
440    {
441        .group = 1,
442        .mask = BIT(10),
443    },
444};
445
446static const struct sirfsoc_padmux cko1_padmux = {
447    .muxmask_counts = ARRAY_SIZE(cko1_muxmask),
448    .muxmask = cko1_muxmask,
449    .funcmask = BIT(3),
450    .funcval = 0,
451};
452
453static const unsigned cko1_pins[] = { 42 };
454
455static const struct sirfsoc_muxmask i2s_muxmask[] = {
456    {
457        .group = 1,
458        .mask =
459            BIT(10) | BIT(11) | BIT(12) | BIT(13) | BIT(14) | BIT(19)
460                | BIT(23) | BIT(28),
461    },
462};
463
464static const struct sirfsoc_padmux i2s_padmux = {
465    .muxmask_counts = ARRAY_SIZE(i2s_muxmask),
466    .muxmask = i2s_muxmask,
467    .funcmask = BIT(3) | BIT(9),
468    .funcval = BIT(3),
469};
470
471static const unsigned i2s_pins[] = { 42, 43, 44, 45, 46, 51, 55, 60 };
472
473static const struct sirfsoc_muxmask ac97_muxmask[] = {
474    {
475        .group = 1,
476        .mask = BIT(11) | BIT(12) | BIT(13) | BIT(14),
477    },
478};
479
480static const struct sirfsoc_padmux ac97_padmux = {
481    .muxmask_counts = ARRAY_SIZE(ac97_muxmask),
482    .muxmask = ac97_muxmask,
483    .funcmask = BIT(8),
484    .funcval = 0,
485};
486
487static const unsigned ac97_pins[] = { 33, 34, 35, 36 };
488
489static const struct sirfsoc_muxmask spi1_muxmask[] = {
490    {
491        .group = 1,
492        .mask = BIT(11) | BIT(12) | BIT(13) | BIT(14),
493    },
494};
495
496static const struct sirfsoc_padmux spi1_padmux = {
497    .muxmask_counts = ARRAY_SIZE(spi1_muxmask),
498    .muxmask = spi1_muxmask,
499    .funcmask = BIT(8),
500    .funcval = BIT(8),
501};
502
503static const unsigned spi1_pins[] = { 43, 44, 45, 46 };
504
505static const struct sirfsoc_muxmask sdmmc1_muxmask[] = {
506    {
507        .group = 0,
508        .mask = BIT(27) | BIT(28) | BIT(29),
509    },
510};
511
512static const struct sirfsoc_padmux sdmmc1_padmux = {
513    .muxmask_counts = ARRAY_SIZE(sdmmc1_muxmask),
514    .muxmask = sdmmc1_muxmask,
515};
516
517static const unsigned sdmmc1_pins[] = { 27, 28, 29 };
518
519static const struct sirfsoc_muxmask gps_muxmask[] = {
520    {
521        .group = 0,
522        .mask = BIT(24) | BIT(25) | BIT(26),
523    },
524};
525
526static const struct sirfsoc_padmux gps_padmux = {
527    .muxmask_counts = ARRAY_SIZE(gps_muxmask),
528    .muxmask = gps_muxmask,
529    .funcmask = BIT(12) | BIT(13) | BIT(14),
530    .funcval = BIT(12),
531};
532
533static const unsigned gps_pins[] = { 24, 25, 26 };
534
535static const struct sirfsoc_muxmask sdmmc5_muxmask[] = {
536    {
537        .group = 0,
538        .mask = BIT(24) | BIT(25) | BIT(26),
539    }, {
540        .group = 1,
541        .mask = BIT(29),
542    }, {
543        .group = 2,
544        .mask = BIT(0) | BIT(1),
545    },
546};
547
548static const struct sirfsoc_padmux sdmmc5_padmux = {
549    .muxmask_counts = ARRAY_SIZE(sdmmc5_muxmask),
550    .muxmask = sdmmc5_muxmask,
551    .funcmask = BIT(13) | BIT(14),
552    .funcval = BIT(13) | BIT(14),
553};
554
555static const unsigned sdmmc5_pins[] = { 24, 25, 26, 61, 64, 65 };
556
557static const struct sirfsoc_muxmask usp0_muxmask[] = {
558    {
559        .group = 1,
560        .mask = BIT(19) | BIT(20) | BIT(21) | BIT(22) | BIT(23),
561    },
562};
563
564static const struct sirfsoc_padmux usp0_padmux = {
565    .muxmask_counts = ARRAY_SIZE(usp0_muxmask),
566    .muxmask = usp0_muxmask,
567    .funcmask = BIT(1) | BIT(2) | BIT(6) | BIT(9),
568    .funcval = 0,
569};
570
571static const unsigned usp0_pins[] = { 51, 52, 53, 54, 55 };
572
573static const struct sirfsoc_muxmask usp1_muxmask[] = {
574    {
575        .group = 1,
576        .mask = BIT(24) | BIT(25) | BIT(26) | BIT(27) | BIT(28),
577    },
578};
579
580static const struct sirfsoc_padmux usp1_padmux = {
581    .muxmask_counts = ARRAY_SIZE(usp1_muxmask),
582    .muxmask = usp1_muxmask,
583    .funcmask = BIT(1) | BIT(9) | BIT(10) | BIT(11),
584    .funcval = 0,
585};
586
587static const unsigned usp1_pins[] = { 56, 57, 58, 59, 60 };
588
589static const struct sirfsoc_muxmask usp2_muxmask[] = {
590    {
591        .group = 1,
592        .mask = BIT(29) | BIT(30) | BIT(31),
593    }, {
594        .group = 2,
595        .mask = BIT(0) | BIT(1),
596    },
597};
598
599static const struct sirfsoc_padmux usp2_padmux = {
600    .muxmask_counts = ARRAY_SIZE(usp2_muxmask),
601    .muxmask = usp2_muxmask,
602    .funcmask = BIT(13) | BIT(14),
603    .funcval = 0,
604};
605
606static const unsigned usp2_pins[] = { 61, 62, 63, 64, 65 };
607
608static const struct sirfsoc_muxmask nand_muxmask[] = {
609    {
610        .group = 2,
611        .mask = BIT(2) | BIT(3) | BIT(28) | BIT(29) | BIT(30),
612    },
613};
614
615static const struct sirfsoc_padmux nand_padmux = {
616    .muxmask_counts = ARRAY_SIZE(nand_muxmask),
617    .muxmask = nand_muxmask,
618    .funcmask = BIT(5),
619    .funcval = 0,
620};
621
622static const unsigned nand_pins[] = { 64, 65, 92, 93, 94 };
623
624static const struct sirfsoc_padmux sdmmc0_padmux = {
625    .muxmask_counts = 0,
626    .funcmask = BIT(5),
627    .funcval = 0,
628};
629
630static const unsigned sdmmc0_pins[] = { };
631
632static const struct sirfsoc_muxmask sdmmc2_muxmask[] = {
633    {
634        .group = 2,
635        .mask = BIT(2) | BIT(3),
636    },
637};
638
639static const struct sirfsoc_padmux sdmmc2_padmux = {
640    .muxmask_counts = ARRAY_SIZE(sdmmc2_muxmask),
641    .muxmask = sdmmc2_muxmask,
642    .funcmask = BIT(5),
643    .funcval = BIT(5),
644};
645
646static const unsigned sdmmc2_pins[] = { 66, 67 };
647
648static const struct sirfsoc_muxmask cko0_muxmask[] = {
649    {
650        .group = 2,
651        .mask = BIT(14),
652    },
653};
654
655static const struct sirfsoc_padmux cko0_padmux = {
656    .muxmask_counts = ARRAY_SIZE(cko0_muxmask),
657    .muxmask = cko0_muxmask,
658};
659
660static const unsigned cko0_pins[] = { 78 };
661
662static const struct sirfsoc_muxmask vip_muxmask[] = {
663    {
664        .group = 2,
665        .mask = BIT(15) | BIT(16) | BIT(17) | BIT(18) | BIT(19)
666            | BIT(20) | BIT(21) | BIT(22) | BIT(23) | BIT(24) |
667            BIT(25),
668    },
669};
670
671static const struct sirfsoc_padmux vip_padmux = {
672    .muxmask_counts = ARRAY_SIZE(vip_muxmask),
673    .muxmask = vip_muxmask,
674    .funcmask = BIT(0),
675    .funcval = 0,
676};
677
678static const unsigned vip_pins[] = { 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89 };
679
680static const struct sirfsoc_muxmask i2c0_muxmask[] = {
681    {
682        .group = 2,
683        .mask = BIT(26) | BIT(27),
684    },
685};
686
687static const struct sirfsoc_padmux i2c0_padmux = {
688    .muxmask_counts = ARRAY_SIZE(i2c0_muxmask),
689    .muxmask = i2c0_muxmask,
690};
691
692static const unsigned i2c0_pins[] = { 90, 91 };
693
694static const struct sirfsoc_muxmask i2c1_muxmask[] = {
695    {
696        .group = 0,
697        .mask = BIT(13) | BIT(15),
698    },
699};
700
701static const struct sirfsoc_padmux i2c1_padmux = {
702    .muxmask_counts = ARRAY_SIZE(i2c1_muxmask),
703    .muxmask = i2c1_muxmask,
704};
705
706static const unsigned i2c1_pins[] = { 13, 15 };
707
708static const struct sirfsoc_muxmask viprom_muxmask[] = {
709    {
710        .group = 2,
711        .mask = BIT(15) | BIT(16) | BIT(17) | BIT(18) | BIT(19)
712            | BIT(20) | BIT(21) | BIT(22) | BIT(23) | BIT(24) |
713            BIT(25),
714    }, {
715        .group = 0,
716        .mask = BIT(12),
717    },
718};
719
720static const struct sirfsoc_padmux viprom_padmux = {
721    .muxmask_counts = ARRAY_SIZE(viprom_muxmask),
722    .muxmask = viprom_muxmask,
723    .funcmask = BIT(0),
724    .funcval = BIT(0),
725};
726
727static const unsigned viprom_pins[] = { 12, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89 };
728
729static const struct sirfsoc_muxmask pwm0_muxmask[] = {
730    {
731        .group = 0,
732        .mask = BIT(4),
733    },
734};
735
736static const struct sirfsoc_padmux pwm0_padmux = {
737    .muxmask_counts = ARRAY_SIZE(pwm0_muxmask),
738    .muxmask = pwm0_muxmask,
739    .funcmask = BIT(12),
740    .funcval = 0,
741};
742
743static const unsigned pwm0_pins[] = { 4 };
744
745static const struct sirfsoc_muxmask pwm1_muxmask[] = {
746    {
747        .group = 0,
748        .mask = BIT(5),
749    },
750};
751
752static const struct sirfsoc_padmux pwm1_padmux = {
753    .muxmask_counts = ARRAY_SIZE(pwm1_muxmask),
754    .muxmask = pwm1_muxmask,
755};
756
757static const unsigned pwm1_pins[] = { 5 };
758
759static const struct sirfsoc_muxmask pwm2_muxmask[] = {
760    {
761        .group = 0,
762        .mask = BIT(6),
763    },
764};
765
766static const struct sirfsoc_padmux pwm2_padmux = {
767    .muxmask_counts = ARRAY_SIZE(pwm2_muxmask),
768    .muxmask = pwm2_muxmask,
769};
770
771static const unsigned pwm2_pins[] = { 6 };
772
773static const struct sirfsoc_muxmask pwm3_muxmask[] = {
774    {
775        .group = 0,
776        .mask = BIT(7),
777    },
778};
779
780static const struct sirfsoc_padmux pwm3_padmux = {
781    .muxmask_counts = ARRAY_SIZE(pwm3_muxmask),
782    .muxmask = pwm3_muxmask,
783};
784
785static const unsigned pwm3_pins[] = { 7 };
786
787static const struct sirfsoc_muxmask warm_rst_muxmask[] = {
788    {
789        .group = 0,
790        .mask = BIT(8),
791    },
792};
793
794static const struct sirfsoc_padmux warm_rst_padmux = {
795    .muxmask_counts = ARRAY_SIZE(warm_rst_muxmask),
796    .muxmask = warm_rst_muxmask,
797};
798
799static const unsigned warm_rst_pins[] = { 8 };
800
801static const struct sirfsoc_muxmask usb0_utmi_drvbus_muxmask[] = {
802    {
803        .group = 1,
804        .mask = BIT(22),
805    },
806};
807static const struct sirfsoc_padmux usb0_utmi_drvbus_padmux = {
808    .muxmask_counts = ARRAY_SIZE(usb0_utmi_drvbus_muxmask),
809    .muxmask = usb0_utmi_drvbus_muxmask,
810    .funcmask = BIT(6),
811    .funcval = BIT(6), /* refer to PAD_UTMI_DRVVBUS0_ENABLE */
812};
813
814static const unsigned usb0_utmi_drvbus_pins[] = { 54 };
815
816static const struct sirfsoc_muxmask usb1_utmi_drvbus_muxmask[] = {
817    {
818        .group = 1,
819        .mask = BIT(27),
820    },
821};
822
823static const struct sirfsoc_padmux usb1_utmi_drvbus_padmux = {
824    .muxmask_counts = ARRAY_SIZE(usb1_utmi_drvbus_muxmask),
825    .muxmask = usb1_utmi_drvbus_muxmask,
826    .funcmask = BIT(11),
827    .funcval = BIT(11), /* refer to PAD_UTMI_DRVVBUS1_ENABLE */
828};
829
830static const unsigned usb1_utmi_drvbus_pins[] = { 59 };
831
832static const struct sirfsoc_muxmask pulse_count_muxmask[] = {
833    {
834        .group = 0,
835        .mask = BIT(9) | BIT(10) | BIT(11),
836    },
837};
838
839static const struct sirfsoc_padmux pulse_count_padmux = {
840    .muxmask_counts = ARRAY_SIZE(pulse_count_muxmask),
841    .muxmask = pulse_count_muxmask,
842};
843
844static const unsigned pulse_count_pins[] = { 9, 10, 11 };
845
846#define SIRFSOC_PIN_GROUP(n, p) \
847    { \
848        .name = n, \
849        .pins = p, \
850        .num_pins = ARRAY_SIZE(p), \
851    }
852
853static const struct sirfsoc_pin_group sirfsoc_pin_groups[] = {
854    SIRFSOC_PIN_GROUP("lcd_16bitsgrp", lcd_16bits_pins),
855    SIRFSOC_PIN_GROUP("lcd_18bitsgrp", lcd_18bits_pins),
856    SIRFSOC_PIN_GROUP("lcd_24bitsgrp", lcd_24bits_pins),
857    SIRFSOC_PIN_GROUP("lcdrom_grp", lcdrom_pins),
858    SIRFSOC_PIN_GROUP("uart0grp", uart0_pins),
859    SIRFSOC_PIN_GROUP("uart1grp", uart1_pins),
860    SIRFSOC_PIN_GROUP("uart2grp", uart2_pins),
861    SIRFSOC_PIN_GROUP("uart2_nostreamctrlgrp", uart2_nostreamctrl_pins),
862    SIRFSOC_PIN_GROUP("usp0grp", usp0_pins),
863    SIRFSOC_PIN_GROUP("usp1grp", usp1_pins),
864    SIRFSOC_PIN_GROUP("usp2grp", usp2_pins),
865    SIRFSOC_PIN_GROUP("i2c0grp", i2c0_pins),
866    SIRFSOC_PIN_GROUP("i2c1grp", i2c1_pins),
867    SIRFSOC_PIN_GROUP("pwm0grp", pwm0_pins),
868    SIRFSOC_PIN_GROUP("pwm1grp", pwm1_pins),
869    SIRFSOC_PIN_GROUP("pwm2grp", pwm2_pins),
870    SIRFSOC_PIN_GROUP("pwm3grp", pwm3_pins),
871    SIRFSOC_PIN_GROUP("vipgrp", vip_pins),
872    SIRFSOC_PIN_GROUP("vipromgrp", viprom_pins),
873    SIRFSOC_PIN_GROUP("warm_rstgrp", warm_rst_pins),
874    SIRFSOC_PIN_GROUP("cko0_rstgrp", cko0_pins),
875    SIRFSOC_PIN_GROUP("cko1_rstgrp", cko1_pins),
876    SIRFSOC_PIN_GROUP("sdmmc0grp", sdmmc0_pins),
877    SIRFSOC_PIN_GROUP("sdmmc1grp", sdmmc1_pins),
878    SIRFSOC_PIN_GROUP("sdmmc2grp", sdmmc2_pins),
879    SIRFSOC_PIN_GROUP("sdmmc3grp", sdmmc3_pins),
880    SIRFSOC_PIN_GROUP("sdmmc4grp", sdmmc4_pins),
881    SIRFSOC_PIN_GROUP("sdmmc5grp", sdmmc5_pins),
882    SIRFSOC_PIN_GROUP("usb0_utmi_drvbusgrp", usb0_utmi_drvbus_pins),
883    SIRFSOC_PIN_GROUP("usb1_utmi_drvbusgrp", usb1_utmi_drvbus_pins),
884    SIRFSOC_PIN_GROUP("pulse_countgrp", pulse_count_pins),
885    SIRFSOC_PIN_GROUP("i2sgrp", i2s_pins),
886    SIRFSOC_PIN_GROUP("ac97grp", ac97_pins),
887    SIRFSOC_PIN_GROUP("nandgrp", nand_pins),
888    SIRFSOC_PIN_GROUP("spi0grp", spi0_pins),
889    SIRFSOC_PIN_GROUP("spi1grp", spi1_pins),
890    SIRFSOC_PIN_GROUP("gpsgrp", gps_pins),
891};
892
893static int sirfsoc_get_groups_count(struct pinctrl_dev *pctldev)
894{
895    return ARRAY_SIZE(sirfsoc_pin_groups);
896}
897
898static const char *sirfsoc_get_group_name(struct pinctrl_dev *pctldev,
899                       unsigned selector)
900{
901    return sirfsoc_pin_groups[selector].name;
902}
903
904static int sirfsoc_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
905                   const unsigned **pins,
906                   unsigned *num_pins)
907{
908    *pins = sirfsoc_pin_groups[selector].pins;
909    *num_pins = sirfsoc_pin_groups[selector].num_pins;
910    return 0;
911}
912
913static void sirfsoc_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
914           unsigned offset)
915{
916    seq_printf(s, " " DRIVER_NAME);
917}
918
919static struct pinctrl_ops sirfsoc_pctrl_ops = {
920    .get_groups_count = sirfsoc_get_groups_count,
921    .get_group_name = sirfsoc_get_group_name,
922    .get_group_pins = sirfsoc_get_group_pins,
923    .pin_dbg_show = sirfsoc_pin_dbg_show,
924};
925
926struct sirfsoc_pmx_func {
927    const char *name;
928    const char * const *groups;
929    const unsigned num_groups;
930    const struct sirfsoc_padmux *padmux;
931};
932
933static const char * const lcd_16bitsgrp[] = { "lcd_16bitsgrp" };
934static const char * const lcd_18bitsgrp[] = { "lcd_18bitsgrp" };
935static const char * const lcd_24bitsgrp[] = { "lcd_24bitsgrp" };
936static const char * const lcdromgrp[] = { "lcdromgrp" };
937static const char * const uart0grp[] = { "uart0grp" };
938static const char * const uart1grp[] = { "uart1grp" };
939static const char * const uart2grp[] = { "uart2grp" };
940static const char * const uart2_nostreamctrlgrp[] = { "uart2_nostreamctrlgrp" };
941static const char * const usp0grp[] = { "usp0grp" };
942static const char * const usp1grp[] = { "usp1grp" };
943static const char * const usp2grp[] = { "usp2grp" };
944static const char * const i2c0grp[] = { "i2c0grp" };
945static const char * const i2c1grp[] = { "i2c1grp" };
946static const char * const pwm0grp[] = { "pwm0grp" };
947static const char * const pwm1grp[] = { "pwm1grp" };
948static const char * const pwm2grp[] = { "pwm2grp" };
949static const char * const pwm3grp[] = { "pwm3grp" };
950static const char * const vipgrp[] = { "vipgrp" };
951static const char * const vipromgrp[] = { "vipromgrp" };
952static const char * const warm_rstgrp[] = { "warm_rstgrp" };
953static const char * const cko0grp[] = { "cko0grp" };
954static const char * const cko1grp[] = { "cko1grp" };
955static const char * const sdmmc0grp[] = { "sdmmc0grp" };
956static const char * const sdmmc1grp[] = { "sdmmc1grp" };
957static const char * const sdmmc2grp[] = { "sdmmc2grp" };
958static const char * const sdmmc3grp[] = { "sdmmc3grp" };
959static const char * const sdmmc4grp[] = { "sdmmc4grp" };
960static const char * const sdmmc5grp[] = { "sdmmc5grp" };
961static const char * const usb0_utmi_drvbusgrp[] = { "usb0_utmi_drvbusgrp" };
962static const char * const usb1_utmi_drvbusgrp[] = { "usb1_utmi_drvbusgrp" };
963static const char * const pulse_countgrp[] = { "pulse_countgrp" };
964static const char * const i2sgrp[] = { "i2sgrp" };
965static const char * const ac97grp[] = { "ac97grp" };
966static const char * const nandgrp[] = { "nandgrp" };
967static const char * const spi0grp[] = { "spi0grp" };
968static const char * const spi1grp[] = { "spi1grp" };
969static const char * const gpsgrp[] = { "gpsgrp" };
970
971#define SIRFSOC_PMX_FUNCTION(n, g, m) \
972    { \
973        .name = n, \
974        .groups = g, \
975        .num_groups = ARRAY_SIZE(g), \
976        .padmux = &m, \
977    }
978
979static const struct sirfsoc_pmx_func sirfsoc_pmx_functions[] = {
980    SIRFSOC_PMX_FUNCTION("lcd_16bits", lcd_16bitsgrp, lcd_16bits_padmux),
981    SIRFSOC_PMX_FUNCTION("lcd_18bits", lcd_18bitsgrp, lcd_18bits_padmux),
982    SIRFSOC_PMX_FUNCTION("lcd_24bits", lcd_24bitsgrp, lcd_24bits_padmux),
983    SIRFSOC_PMX_FUNCTION("lcdrom", lcdromgrp, lcdrom_padmux),
984    SIRFSOC_PMX_FUNCTION("uart0", uart0grp, uart0_padmux),
985    SIRFSOC_PMX_FUNCTION("uart1", uart1grp, uart1_padmux),
986    SIRFSOC_PMX_FUNCTION("uart2", uart2grp, uart2_padmux),
987    SIRFSOC_PMX_FUNCTION("uart2_nostreamctrl", uart2_nostreamctrlgrp, uart2_nostreamctrl_padmux),
988    SIRFSOC_PMX_FUNCTION("usp0", usp0grp, usp0_padmux),
989    SIRFSOC_PMX_FUNCTION("usp1", usp1grp, usp1_padmux),
990    SIRFSOC_PMX_FUNCTION("usp2", usp2grp, usp2_padmux),
991    SIRFSOC_PMX_FUNCTION("i2c0", i2c0grp, i2c0_padmux),
992    SIRFSOC_PMX_FUNCTION("i2c1", i2c1grp, i2c1_padmux),
993    SIRFSOC_PMX_FUNCTION("pwm0", pwm0grp, pwm0_padmux),
994    SIRFSOC_PMX_FUNCTION("pwm1", pwm1grp, pwm1_padmux),
995    SIRFSOC_PMX_FUNCTION("pwm2", pwm2grp, pwm2_padmux),
996    SIRFSOC_PMX_FUNCTION("pwm3", pwm3grp, pwm3_padmux),
997    SIRFSOC_PMX_FUNCTION("vip", vipgrp, vip_padmux),
998    SIRFSOC_PMX_FUNCTION("viprom", vipromgrp, viprom_padmux),
999    SIRFSOC_PMX_FUNCTION("warm_rst", warm_rstgrp, warm_rst_padmux),
1000    SIRFSOC_PMX_FUNCTION("cko0", cko0grp, cko0_padmux),
1001    SIRFSOC_PMX_FUNCTION("cko1", cko1grp, cko1_padmux),
1002    SIRFSOC_PMX_FUNCTION("sdmmc0", sdmmc0grp, sdmmc0_padmux),
1003    SIRFSOC_PMX_FUNCTION("sdmmc1", sdmmc1grp, sdmmc1_padmux),
1004    SIRFSOC_PMX_FUNCTION("sdmmc2", sdmmc2grp, sdmmc2_padmux),
1005    SIRFSOC_PMX_FUNCTION("sdmmc3", sdmmc3grp, sdmmc3_padmux),
1006    SIRFSOC_PMX_FUNCTION("sdmmc4", sdmmc4grp, sdmmc4_padmux),
1007    SIRFSOC_PMX_FUNCTION("sdmmc5", sdmmc5grp, sdmmc5_padmux),
1008    SIRFSOC_PMX_FUNCTION("usb0_utmi_drvbus", usb0_utmi_drvbusgrp, usb0_utmi_drvbus_padmux),
1009    SIRFSOC_PMX_FUNCTION("usb1_utmi_drvbus", usb1_utmi_drvbusgrp, usb1_utmi_drvbus_padmux),
1010    SIRFSOC_PMX_FUNCTION("pulse_count", pulse_countgrp, pulse_count_padmux),
1011    SIRFSOC_PMX_FUNCTION("i2s", i2sgrp, i2s_padmux),
1012    SIRFSOC_PMX_FUNCTION("ac97", ac97grp, ac97_padmux),
1013    SIRFSOC_PMX_FUNCTION("nand", nandgrp, nand_padmux),
1014    SIRFSOC_PMX_FUNCTION("spi0", spi0grp, spi0_padmux),
1015    SIRFSOC_PMX_FUNCTION("spi1", spi1grp, spi1_padmux),
1016    SIRFSOC_PMX_FUNCTION("gps", gpsgrp, gps_padmux),
1017};
1018
1019static void sirfsoc_pinmux_endisable(struct sirfsoc_pmx *spmx, unsigned selector,
1020    bool enable)
1021{
1022    int i;
1023    const struct sirfsoc_padmux *mux = sirfsoc_pmx_functions[selector].padmux;
1024    const struct sirfsoc_muxmask *mask = mux->muxmask;
1025
1026    for (i = 0; i < mux->muxmask_counts; i++) {
1027        u32 muxval;
1028        muxval = readl(spmx->gpio_virtbase + SIRFSOC_GPIO_PAD_EN(mask[i].group));
1029        if (enable)
1030            muxval = muxval & ~mask[i].mask;
1031        else
1032            muxval = muxval | mask[i].mask;
1033        writel(muxval, spmx->gpio_virtbase + SIRFSOC_GPIO_PAD_EN(mask[i].group));
1034    }
1035
1036    if (mux->funcmask && enable) {
1037        u32 func_en_val;
1038        func_en_val =
1039            readl(spmx->rsc_virtbase + SIRFSOC_RSC_PIN_MUX);
1040        func_en_val =
1041            (func_en_val & ~mux->funcmask) | (mux->
1042                funcval);
1043        writel(func_en_val, spmx->rsc_virtbase + SIRFSOC_RSC_PIN_MUX);
1044    }
1045}
1046
1047static int sirfsoc_pinmux_enable(struct pinctrl_dev *pmxdev, unsigned selector,
1048    unsigned group)
1049{
1050    struct sirfsoc_pmx *spmx;
1051
1052    spmx = pinctrl_dev_get_drvdata(pmxdev);
1053    sirfsoc_pinmux_endisable(spmx, selector, true);
1054
1055    return 0;
1056}
1057
1058static void sirfsoc_pinmux_disable(struct pinctrl_dev *pmxdev, unsigned selector,
1059    unsigned group)
1060{
1061    struct sirfsoc_pmx *spmx;
1062
1063    spmx = pinctrl_dev_get_drvdata(pmxdev);
1064    sirfsoc_pinmux_endisable(spmx, selector, false);
1065}
1066
1067static int sirfsoc_pinmux_get_funcs_count(struct pinctrl_dev *pmxdev)
1068{
1069    return ARRAY_SIZE(sirfsoc_pmx_functions);
1070}
1071
1072static const char *sirfsoc_pinmux_get_func_name(struct pinctrl_dev *pctldev,
1073                      unsigned selector)
1074{
1075    return sirfsoc_pmx_functions[selector].name;
1076}
1077
1078static int sirfsoc_pinmux_get_groups(struct pinctrl_dev *pctldev, unsigned selector,
1079                   const char * const **groups,
1080                   unsigned * const num_groups)
1081{
1082    *groups = sirfsoc_pmx_functions[selector].groups;
1083    *num_groups = sirfsoc_pmx_functions[selector].num_groups;
1084    return 0;
1085}
1086
1087static int sirfsoc_pinmux_request_gpio(struct pinctrl_dev *pmxdev,
1088    struct pinctrl_gpio_range *range, unsigned offset)
1089{
1090    struct sirfsoc_pmx *spmx;
1091
1092    int group = range->id;
1093
1094    u32 muxval;
1095
1096    spmx = pinctrl_dev_get_drvdata(pmxdev);
1097
1098    muxval = readl(spmx->gpio_virtbase + SIRFSOC_GPIO_PAD_EN(group));
1099    muxval = muxval | (1 << (offset - range->pin_base));
1100    writel(muxval, spmx->gpio_virtbase + SIRFSOC_GPIO_PAD_EN(group));
1101
1102    return 0;
1103}
1104
1105static struct pinmux_ops sirfsoc_pinmux_ops = {
1106    .enable = sirfsoc_pinmux_enable,
1107    .disable = sirfsoc_pinmux_disable,
1108    .get_functions_count = sirfsoc_pinmux_get_funcs_count,
1109    .get_function_name = sirfsoc_pinmux_get_func_name,
1110    .get_function_groups = sirfsoc_pinmux_get_groups,
1111    .gpio_request_enable = sirfsoc_pinmux_request_gpio,
1112};
1113
1114static struct pinctrl_desc sirfsoc_pinmux_desc = {
1115    .name = DRIVER_NAME,
1116    .pins = sirfsoc_pads,
1117    .npins = ARRAY_SIZE(sirfsoc_pads),
1118    .pctlops = &sirfsoc_pctrl_ops,
1119    .pmxops = &sirfsoc_pinmux_ops,
1120    .owner = THIS_MODULE,
1121};
1122
1123/*
1124 * Todo: bind irq_chip to every pinctrl_gpio_range
1125 */
1126static struct pinctrl_gpio_range sirfsoc_gpio_ranges[] = {
1127    {
1128        .name = "sirfsoc-gpio*",
1129        .id = 0,
1130        .base = 0,
1131        .pin_base = 0,
1132        .npins = 32,
1133    }, {
1134        .name = "sirfsoc-gpio*",
1135        .id = 1,
1136        .base = 32,
1137        .pin_base = 32,
1138        .npins = 32,
1139    }, {
1140        .name = "sirfsoc-gpio*",
1141        .id = 2,
1142        .base = 64,
1143        .pin_base = 64,
1144        .npins = 32,
1145    }, {
1146        .name = "sirfsoc-gpio*",
1147        .id = 3,
1148        .base = 96,
1149        .pin_base = 96,
1150        .npins = 19,
1151    },
1152};
1153
1154static void __iomem *sirfsoc_rsc_of_iomap(void)
1155{
1156    const struct of_device_id rsc_ids[] = {
1157        { .compatible = "sirf,prima2-rsc" },
1158        {}
1159    };
1160    struct device_node *np;
1161
1162    np = of_find_matching_node(NULL, rsc_ids);
1163    if (!np)
1164        panic("unable to find compatible rsc node in dtb\n");
1165
1166    return of_iomap(np, 0);
1167}
1168
1169static int __devinit sirfsoc_pinmux_probe(struct platform_device *pdev)
1170{
1171    int ret;
1172    struct sirfsoc_pmx *spmx;
1173    struct device_node *np = pdev->dev.of_node;
1174    int i;
1175
1176    /* Create state holders etc for this driver */
1177    spmx = devm_kzalloc(&pdev->dev, sizeof(*spmx), GFP_KERNEL);
1178    if (!spmx)
1179        return -ENOMEM;
1180
1181    spmx->dev = &pdev->dev;
1182
1183    platform_set_drvdata(pdev, spmx);
1184
1185    spmx->gpio_virtbase = of_iomap(np, 0);
1186    if (!spmx->gpio_virtbase) {
1187        ret = -ENOMEM;
1188        dev_err(&pdev->dev, "can't map gpio registers\n");
1189        goto out_no_gpio_remap;
1190    }
1191
1192    spmx->rsc_virtbase = sirfsoc_rsc_of_iomap();
1193    if (!spmx->rsc_virtbase) {
1194        ret = -ENOMEM;
1195        dev_err(&pdev->dev, "can't map rsc registers\n");
1196        goto out_no_rsc_remap;
1197    }
1198
1199    /* Now register the pin controller and all pins it handles */
1200    spmx->pmx = pinctrl_register(&sirfsoc_pinmux_desc, &pdev->dev, spmx);
1201    if (!spmx->pmx) {
1202        dev_err(&pdev->dev, "could not register SIRFSOC pinmux driver\n");
1203        ret = -EINVAL;
1204        goto out_no_pmx;
1205    }
1206
1207    for (i = 0; i < ARRAY_SIZE(sirfsoc_gpio_ranges); i++)
1208        pinctrl_add_gpio_range(spmx->pmx, &sirfsoc_gpio_ranges[i]);
1209
1210    dev_info(&pdev->dev, "initialized SIRFSOC pinmux driver\n");
1211
1212    return 0;
1213
1214out_no_pmx:
1215    iounmap(spmx->rsc_virtbase);
1216out_no_rsc_remap:
1217    iounmap(spmx->gpio_virtbase);
1218out_no_gpio_remap:
1219    platform_set_drvdata(pdev, NULL);
1220    return ret;
1221}
1222
1223static const struct of_device_id pinmux_ids[] __devinitconst = {
1224    { .compatible = "sirf,prima2-gpio-pinmux" },
1225    {}
1226};
1227
1228static struct platform_driver sirfsoc_pinmux_driver = {
1229    .driver = {
1230        .name = DRIVER_NAME,
1231        .owner = THIS_MODULE,
1232        .of_match_table = pinmux_ids,
1233    },
1234    .probe = sirfsoc_pinmux_probe,
1235};
1236
1237static int __init sirfsoc_pinmux_init(void)
1238{
1239    return platform_driver_register(&sirfsoc_pinmux_driver);
1240}
1241arch_initcall(sirfsoc_pinmux_init);
1242
1243static inline int sirfsoc_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
1244{
1245    struct sirfsoc_gpio_bank *bank = container_of(to_of_mm_gpio_chip(chip),
1246        struct sirfsoc_gpio_bank, chip);
1247
1248    return irq_find_mapping(bank->domain, offset);
1249}
1250
1251static inline int sirfsoc_gpio_to_offset(unsigned int gpio)
1252{
1253    return gpio % SIRFSOC_GPIO_BANK_SIZE;
1254}
1255
1256static inline struct sirfsoc_gpio_bank *sirfsoc_gpio_to_bank(unsigned int gpio)
1257{
1258    return &sgpio_bank[gpio / SIRFSOC_GPIO_BANK_SIZE];
1259}
1260
1261void sirfsoc_gpio_set_pull(unsigned gpio, unsigned mode)
1262{
1263    struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(gpio);
1264    int idx = sirfsoc_gpio_to_offset(gpio);
1265    u32 val, offset;
1266    unsigned long flags;
1267
1268    offset = SIRFSOC_GPIO_CTRL(bank->id, idx);
1269
1270    spin_lock_irqsave(&sgpio_lock, flags);
1271
1272    val = readl(bank->chip.regs + offset);
1273
1274    switch (mode) {
1275    case SIRFSOC_GPIO_PULL_NONE:
1276        val &= ~SIRFSOC_GPIO_CTL_PULL_MASK;
1277        break;
1278    case SIRFSOC_GPIO_PULL_UP:
1279        val |= SIRFSOC_GPIO_CTL_PULL_MASK;
1280        val |= SIRFSOC_GPIO_CTL_PULL_HIGH;
1281        break;
1282    case SIRFSOC_GPIO_PULL_DOWN:
1283        val |= SIRFSOC_GPIO_CTL_PULL_MASK;
1284        val &= ~SIRFSOC_GPIO_CTL_PULL_HIGH;
1285        break;
1286    default:
1287        break;
1288    }
1289
1290    writel(val, bank->chip.regs + offset);
1291
1292    spin_unlock_irqrestore(&sgpio_lock, flags);
1293}
1294EXPORT_SYMBOL(sirfsoc_gpio_set_pull);
1295
1296static inline struct sirfsoc_gpio_bank *sirfsoc_irqchip_to_bank(struct gpio_chip *chip)
1297{
1298    return container_of(to_of_mm_gpio_chip(chip), struct sirfsoc_gpio_bank, chip);
1299}
1300
1301static void sirfsoc_gpio_irq_ack(struct irq_data *d)
1302{
1303    struct sirfsoc_gpio_bank *bank = irq_data_get_irq_chip_data(d);
1304    int idx = d->hwirq % SIRFSOC_GPIO_BANK_SIZE;
1305    u32 val, offset;
1306    unsigned long flags;
1307
1308    offset = SIRFSOC_GPIO_CTRL(bank->id, idx);
1309
1310    spin_lock_irqsave(&sgpio_lock, flags);
1311
1312    val = readl(bank->chip.regs + offset);
1313
1314    writel(val, bank->chip.regs + offset);
1315
1316    spin_unlock_irqrestore(&sgpio_lock, flags);
1317}
1318
1319static void __sirfsoc_gpio_irq_mask(struct sirfsoc_gpio_bank *bank, int idx)
1320{
1321    u32 val, offset;
1322    unsigned long flags;
1323
1324    offset = SIRFSOC_GPIO_CTRL(bank->id, idx);
1325
1326    spin_lock_irqsave(&sgpio_lock, flags);
1327
1328    val = readl(bank->chip.regs + offset);
1329    val &= ~SIRFSOC_GPIO_CTL_INTR_EN_MASK;
1330    val &= ~SIRFSOC_GPIO_CTL_INTR_STS_MASK;
1331    writel(val, bank->chip.regs + offset);
1332
1333    spin_unlock_irqrestore(&sgpio_lock, flags);
1334}
1335
1336static void sirfsoc_gpio_irq_mask(struct irq_data *d)
1337{
1338    struct sirfsoc_gpio_bank *bank = irq_data_get_irq_chip_data(d);
1339
1340    __sirfsoc_gpio_irq_mask(bank, d->hwirq % SIRFSOC_GPIO_BANK_SIZE);
1341}
1342
1343static void sirfsoc_gpio_irq_unmask(struct irq_data *d)
1344{
1345    struct sirfsoc_gpio_bank *bank = irq_data_get_irq_chip_data(d);
1346    int idx = d->hwirq % SIRFSOC_GPIO_BANK_SIZE;
1347    u32 val, offset;
1348    unsigned long flags;
1349
1350    offset = SIRFSOC_GPIO_CTRL(bank->id, idx);
1351
1352    spin_lock_irqsave(&sgpio_lock, flags);
1353
1354    val = readl(bank->chip.regs + offset);
1355    val &= ~SIRFSOC_GPIO_CTL_INTR_STS_MASK;
1356    val |= SIRFSOC_GPIO_CTL_INTR_EN_MASK;
1357    writel(val, bank->chip.regs + offset);
1358
1359    spin_unlock_irqrestore(&sgpio_lock, flags);
1360}
1361
1362static int sirfsoc_gpio_irq_type(struct irq_data *d, unsigned type)
1363{
1364    struct sirfsoc_gpio_bank *bank = irq_data_get_irq_chip_data(d);
1365    int idx = d->hwirq % SIRFSOC_GPIO_BANK_SIZE;
1366    u32 val, offset;
1367    unsigned long flags;
1368
1369    offset = SIRFSOC_GPIO_CTRL(bank->id, idx);
1370
1371    spin_lock_irqsave(&sgpio_lock, flags);
1372
1373    val = readl(bank->chip.regs + offset);
1374    val &= ~SIRFSOC_GPIO_CTL_INTR_STS_MASK;
1375
1376    switch (type) {
1377    case IRQ_TYPE_NONE:
1378        break;
1379    case IRQ_TYPE_EDGE_RISING:
1380        val |= SIRFSOC_GPIO_CTL_INTR_HIGH_MASK | SIRFSOC_GPIO_CTL_INTR_TYPE_MASK;
1381        val &= ~SIRFSOC_GPIO_CTL_INTR_LOW_MASK;
1382        break;
1383    case IRQ_TYPE_EDGE_FALLING:
1384        val &= ~SIRFSOC_GPIO_CTL_INTR_HIGH_MASK;
1385        val |= SIRFSOC_GPIO_CTL_INTR_LOW_MASK | SIRFSOC_GPIO_CTL_INTR_TYPE_MASK;
1386        break;
1387    case IRQ_TYPE_EDGE_BOTH:
1388        val |= SIRFSOC_GPIO_CTL_INTR_HIGH_MASK | SIRFSOC_GPIO_CTL_INTR_LOW_MASK |
1389             SIRFSOC_GPIO_CTL_INTR_TYPE_MASK;
1390        break;
1391    case IRQ_TYPE_LEVEL_LOW:
1392        val &= ~(SIRFSOC_GPIO_CTL_INTR_HIGH_MASK | SIRFSOC_GPIO_CTL_INTR_TYPE_MASK);
1393        val |= SIRFSOC_GPIO_CTL_INTR_LOW_MASK;
1394        break;
1395    case IRQ_TYPE_LEVEL_HIGH:
1396        val |= SIRFSOC_GPIO_CTL_INTR_HIGH_MASK;
1397        val &= ~(SIRFSOC_GPIO_CTL_INTR_LOW_MASK | SIRFSOC_GPIO_CTL_INTR_TYPE_MASK);
1398        break;
1399    }
1400
1401    writel(val, bank->chip.regs + offset);
1402
1403    spin_unlock_irqrestore(&sgpio_lock, flags);
1404
1405    return 0;
1406}
1407
1408static struct irq_chip sirfsoc_irq_chip = {
1409    .name = "sirf-gpio-irq",
1410    .irq_ack = sirfsoc_gpio_irq_ack,
1411    .irq_mask = sirfsoc_gpio_irq_mask,
1412    .irq_unmask = sirfsoc_gpio_irq_unmask,
1413    .irq_set_type = sirfsoc_gpio_irq_type,
1414};
1415
1416static void sirfsoc_gpio_handle_irq(unsigned int irq, struct irq_desc *desc)
1417{
1418    struct sirfsoc_gpio_bank *bank = irq_get_handler_data(irq);
1419    u32 status, ctrl;
1420    int idx = 0;
1421    unsigned int first_irq;
1422
1423    status = readl(bank->chip.regs + SIRFSOC_GPIO_INT_STATUS(bank->id));
1424    if (!status) {
1425        printk(KERN_WARNING
1426            "%s: gpio id %d status %#x no interrupt is flaged\n",
1427            __func__, bank->id, status);
1428        handle_bad_irq(irq, desc);
1429        return;
1430    }
1431
1432    first_irq = bank->domain->revmap_data.legacy.first_irq;
1433
1434    while (status) {
1435        ctrl = readl(bank->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, idx));
1436
1437        /*
1438         * Here we must check whether the corresponding GPIO's interrupt
1439         * has been enabled, otherwise just skip it
1440         */
1441        if ((status & 0x1) && (ctrl & SIRFSOC_GPIO_CTL_INTR_EN_MASK)) {
1442            pr_debug("%s: gpio id %d idx %d happens\n",
1443                __func__, bank->id, idx);
1444            generic_handle_irq(first_irq + idx);
1445        }
1446
1447        idx++;
1448        status = status >> 1;
1449    }
1450}
1451
1452static inline void sirfsoc_gpio_set_input(struct sirfsoc_gpio_bank *bank, unsigned ctrl_offset)
1453{
1454    u32 val;
1455    unsigned long flags;
1456
1457    spin_lock_irqsave(&bank->lock, flags);
1458
1459    val = readl(bank->chip.regs + ctrl_offset);
1460    val &= ~SIRFSOC_GPIO_CTL_OUT_EN_MASK;
1461    writel(val, bank->chip.regs + ctrl_offset);
1462
1463    spin_unlock_irqrestore(&bank->lock, flags);
1464}
1465
1466static int sirfsoc_gpio_request(struct gpio_chip *chip, unsigned offset)
1467{
1468    struct sirfsoc_gpio_bank *bank = sirfsoc_irqchip_to_bank(chip);
1469    unsigned long flags;
1470
1471    if (pinctrl_request_gpio(chip->base + offset))
1472        return -ENODEV;
1473
1474    spin_lock_irqsave(&bank->lock, flags);
1475
1476    /*
1477     * default status:
1478     * set direction as input and mask irq
1479     */
1480    sirfsoc_gpio_set_input(bank, SIRFSOC_GPIO_CTRL(bank->id, offset));
1481    __sirfsoc_gpio_irq_mask(bank, offset);
1482
1483    spin_unlock_irqrestore(&bank->lock, flags);
1484
1485    return 0;
1486}
1487
1488static void sirfsoc_gpio_free(struct gpio_chip *chip, unsigned offset)
1489{
1490    struct sirfsoc_gpio_bank *bank = sirfsoc_irqchip_to_bank(chip);
1491    unsigned long flags;
1492
1493    spin_lock_irqsave(&bank->lock, flags);
1494
1495    __sirfsoc_gpio_irq_mask(bank, offset);
1496    sirfsoc_gpio_set_input(bank, SIRFSOC_GPIO_CTRL(bank->id, offset));
1497
1498    spin_unlock_irqrestore(&bank->lock, flags);
1499
1500    pinctrl_free_gpio(chip->base + offset);
1501}
1502
1503static int sirfsoc_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
1504{
1505    struct sirfsoc_gpio_bank *bank = sirfsoc_irqchip_to_bank(chip);
1506    int idx = sirfsoc_gpio_to_offset(gpio);
1507    unsigned long flags;
1508    unsigned offset;
1509
1510    offset = SIRFSOC_GPIO_CTRL(bank->id, idx);
1511
1512    spin_lock_irqsave(&bank->lock, flags);
1513
1514    sirfsoc_gpio_set_input(bank, offset);
1515
1516    spin_unlock_irqrestore(&bank->lock, flags);
1517
1518    return 0;
1519}
1520
1521static inline void sirfsoc_gpio_set_output(struct sirfsoc_gpio_bank *bank, unsigned offset,
1522    int value)
1523{
1524    u32 out_ctrl;
1525    unsigned long flags;
1526
1527    spin_lock_irqsave(&bank->lock, flags);
1528
1529    out_ctrl = readl(bank->chip.regs + offset);
1530    if (value)
1531        out_ctrl |= SIRFSOC_GPIO_CTL_DATAOUT_MASK;
1532    else
1533        out_ctrl &= ~SIRFSOC_GPIO_CTL_DATAOUT_MASK;
1534
1535    out_ctrl &= ~SIRFSOC_GPIO_CTL_INTR_EN_MASK;
1536    out_ctrl |= SIRFSOC_GPIO_CTL_OUT_EN_MASK;
1537    writel(out_ctrl, bank->chip.regs + offset);
1538
1539    spin_unlock_irqrestore(&bank->lock, flags);
1540}
1541
1542static int sirfsoc_gpio_direction_output(struct gpio_chip *chip, unsigned gpio, int value)
1543{
1544    struct sirfsoc_gpio_bank *bank = sirfsoc_irqchip_to_bank(chip);
1545    int idx = sirfsoc_gpio_to_offset(gpio);
1546    u32 offset;
1547    unsigned long flags;
1548
1549    offset = SIRFSOC_GPIO_CTRL(bank->id, idx);
1550
1551    spin_lock_irqsave(&sgpio_lock, flags);
1552
1553    sirfsoc_gpio_set_output(bank, offset, value);
1554
1555    spin_unlock_irqrestore(&sgpio_lock, flags);
1556
1557    return 0;
1558}
1559
1560static int sirfsoc_gpio_get_value(struct gpio_chip *chip, unsigned offset)
1561{
1562    struct sirfsoc_gpio_bank *bank = sirfsoc_irqchip_to_bank(chip);
1563    u32 val;
1564    unsigned long flags;
1565
1566    spin_lock_irqsave(&bank->lock, flags);
1567
1568    val = readl(bank->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, offset));
1569
1570    spin_unlock_irqrestore(&bank->lock, flags);
1571
1572    return !!(val & SIRFSOC_GPIO_CTL_DATAIN_MASK);
1573}
1574
1575static void sirfsoc_gpio_set_value(struct gpio_chip *chip, unsigned offset,
1576    int value)
1577{
1578    struct sirfsoc_gpio_bank *bank = sirfsoc_irqchip_to_bank(chip);
1579    u32 ctrl;
1580    unsigned long flags;
1581
1582    spin_lock_irqsave(&bank->lock, flags);
1583
1584    ctrl = readl(bank->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, offset));
1585    if (value)
1586        ctrl |= SIRFSOC_GPIO_CTL_DATAOUT_MASK;
1587    else
1588        ctrl &= ~SIRFSOC_GPIO_CTL_DATAOUT_MASK;
1589    writel(ctrl, bank->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, offset));
1590
1591    spin_unlock_irqrestore(&bank->lock, flags);
1592}
1593
1594int sirfsoc_gpio_irq_map(struct irq_domain *d, unsigned int irq,
1595    irq_hw_number_t hwirq)
1596{
1597    struct sirfsoc_gpio_bank *bank = d->host_data;
1598
1599    if (!bank)
1600        return -EINVAL;
1601
1602    irq_set_chip(irq, &sirfsoc_irq_chip);
1603    irq_set_handler(irq, handle_level_irq);
1604    irq_set_chip_data(irq, bank);
1605    set_irq_flags(irq, IRQF_VALID);
1606
1607    return 0;
1608}
1609
1610const struct irq_domain_ops sirfsoc_gpio_irq_simple_ops = {
1611    .map = sirfsoc_gpio_irq_map,
1612    .xlate = irq_domain_xlate_twocell,
1613};
1614
1615static int __devinit sirfsoc_gpio_probe(struct device_node *np)
1616{
1617    int i, err = 0;
1618    struct sirfsoc_gpio_bank *bank;
1619    void *regs;
1620    struct platform_device *pdev;
1621
1622    pdev = of_find_device_by_node(np);
1623    if (!pdev)
1624        return -ENODEV;
1625
1626    regs = of_iomap(np, 0);
1627    if (!regs)
1628        return -ENOMEM;
1629
1630    for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) {
1631        bank = &sgpio_bank[i];
1632        spin_lock_init(&bank->lock);
1633        bank->chip.gc.request = sirfsoc_gpio_request;
1634        bank->chip.gc.free = sirfsoc_gpio_free;
1635        bank->chip.gc.direction_input = sirfsoc_gpio_direction_input;
1636        bank->chip.gc.get = sirfsoc_gpio_get_value;
1637        bank->chip.gc.direction_output = sirfsoc_gpio_direction_output;
1638        bank->chip.gc.set = sirfsoc_gpio_set_value;
1639        bank->chip.gc.to_irq = sirfsoc_gpio_to_irq;
1640        bank->chip.gc.base = i * SIRFSOC_GPIO_BANK_SIZE;
1641        bank->chip.gc.ngpio = SIRFSOC_GPIO_BANK_SIZE;
1642        bank->chip.gc.label = kstrdup(np->full_name, GFP_KERNEL);
1643        bank->chip.gc.of_node = np;
1644        bank->chip.regs = regs;
1645        bank->id = i;
1646        bank->parent_irq = platform_get_irq(pdev, i);
1647        if (bank->parent_irq < 0) {
1648            err = bank->parent_irq;
1649            goto out;
1650        }
1651
1652        err = gpiochip_add(&bank->chip.gc);
1653        if (err) {
1654            pr_err("%s: error in probe function with status %d\n",
1655                np->full_name, err);
1656            goto out;
1657        }
1658
1659        bank->domain = irq_domain_add_legacy(np, SIRFSOC_GPIO_BANK_SIZE,
1660            SIRFSOC_GPIO_IRQ_START + i * SIRFSOC_GPIO_BANK_SIZE, 0,
1661            &sirfsoc_gpio_irq_simple_ops, bank);
1662
1663        if (!bank->domain) {
1664            pr_err("%s: Failed to create irqdomain\n", np->full_name);
1665            err = -ENOSYS;
1666            goto out;
1667        }
1668
1669        irq_set_chained_handler(bank->parent_irq, sirfsoc_gpio_handle_irq);
1670        irq_set_handler_data(bank->parent_irq, bank);
1671    }
1672
1673out:
1674    iounmap(regs);
1675    return err;
1676}
1677
1678static int __init sirfsoc_gpio_init(void)
1679{
1680
1681    struct device_node *np;
1682
1683    np = of_find_matching_node(NULL, pinmux_ids);
1684
1685    if (!np)
1686        return -ENODEV;
1687
1688    return sirfsoc_gpio_probe(np);
1689}
1690subsys_initcall(sirfsoc_gpio_init);
1691
1692MODULE_AUTHOR("Rongjun Ying <rongjun.ying@csr.com>, "
1693    "Yuping Luo <yuping.luo@csr.com>, "
1694    "Barry Song <baohua.song@csr.com>");
1695MODULE_DESCRIPTION("SIRFSOC pin control driver");
1696MODULE_LICENSE("GPL");
1697

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