Root/drivers/spi/spi-ppc4xx.c

1/*
2 * SPI_PPC4XX SPI controller driver.
3 *
4 * Copyright (C) 2007 Gary Jennejohn <garyj@denx.de>
5 * Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering
6 * Copyright 2009 Harris Corporation, Steven A. Falco <sfalco@harris.com>
7 *
8 * Based in part on drivers/spi/spi_s3c24xx.c
9 *
10 * Copyright (c) 2006 Ben Dooks
11 * Copyright (c) 2006 Simtec Electronics
12 * Ben Dooks <ben@simtec.co.uk>
13 *
14 * This program is free software; you can redistribute it and/or modify it
15 * under the terms of the GNU General Public License version 2 as published
16 * by the Free Software Foundation.
17 */
18
19/*
20 * The PPC4xx SPI controller has no FIFO so each sent/received byte will
21 * generate an interrupt to the CPU. This can cause high CPU utilization.
22 * This driver allows platforms to reduce the interrupt load on the CPU
23 * during SPI transfers by setting max_speed_hz via the device tree.
24 */
25
26#include <linux/module.h>
27#include <linux/init.h>
28#include <linux/sched.h>
29#include <linux/slab.h>
30#include <linux/errno.h>
31#include <linux/wait.h>
32#include <linux/of_platform.h>
33#include <linux/of_gpio.h>
34#include <linux/interrupt.h>
35#include <linux/delay.h>
36
37#include <linux/gpio.h>
38#include <linux/spi/spi.h>
39#include <linux/spi/spi_bitbang.h>
40
41#include <asm/io.h>
42#include <asm/dcr.h>
43#include <asm/dcr-regs.h>
44
45/* bits in mode register - bit 0 is MSb */
46
47/*
48 * SPI_PPC4XX_MODE_SCP = 0 means "data latched on trailing edge of clock"
49 * SPI_PPC4XX_MODE_SCP = 1 means "data latched on leading edge of clock"
50 * Note: This is the inverse of CPHA.
51 */
52#define SPI_PPC4XX_MODE_SCP (0x80 >> 3)
53
54/* SPI_PPC4XX_MODE_SPE = 1 means "port enabled" */
55#define SPI_PPC4XX_MODE_SPE (0x80 >> 4)
56
57/*
58 * SPI_PPC4XX_MODE_RD = 0 means "MSB first" - this is the normal mode
59 * SPI_PPC4XX_MODE_RD = 1 means "LSB first" - this is bit-reversed mode
60 * Note: This is identical to SPI_LSB_FIRST.
61 */
62#define SPI_PPC4XX_MODE_RD (0x80 >> 5)
63
64/*
65 * SPI_PPC4XX_MODE_CI = 0 means "clock idles low"
66 * SPI_PPC4XX_MODE_CI = 1 means "clock idles high"
67 * Note: This is identical to CPOL.
68 */
69#define SPI_PPC4XX_MODE_CI (0x80 >> 6)
70
71/*
72 * SPI_PPC4XX_MODE_IL = 0 means "loopback disable"
73 * SPI_PPC4XX_MODE_IL = 1 means "loopback enable"
74 */
75#define SPI_PPC4XX_MODE_IL (0x80 >> 7)
76
77/* bits in control register */
78/* starts a transfer when set */
79#define SPI_PPC4XX_CR_STR (0x80 >> 7)
80
81/* bits in status register */
82/* port is busy with a transfer */
83#define SPI_PPC4XX_SR_BSY (0x80 >> 6)
84/* RxD ready */
85#define SPI_PPC4XX_SR_RBR (0x80 >> 7)
86
87/* clock settings (SCP and CI) for various SPI modes */
88#define SPI_CLK_MODE0 (SPI_PPC4XX_MODE_SCP | 0)
89#define SPI_CLK_MODE1 (0 | 0)
90#define SPI_CLK_MODE2 (SPI_PPC4XX_MODE_SCP | SPI_PPC4XX_MODE_CI)
91#define SPI_CLK_MODE3 (0 | SPI_PPC4XX_MODE_CI)
92
93#define DRIVER_NAME "spi_ppc4xx_of"
94
95struct spi_ppc4xx_regs {
96    u8 mode;
97    u8 rxd;
98    u8 txd;
99    u8 cr;
100    u8 sr;
101    u8 dummy;
102    /*
103     * Clock divisor modulus register
104     * This uses the follwing formula:
105     * SCPClkOut = OPBCLK/(4(CDM + 1))
106     * or
107     * CDM = (OPBCLK/4*SCPClkOut) - 1
108     * bit 0 is the MSb!
109     */
110    u8 cdm;
111};
112
113/* SPI Controller driver's private data. */
114struct ppc4xx_spi {
115    /* bitbang has to be first */
116    struct spi_bitbang bitbang;
117    struct completion done;
118
119    u64 mapbase;
120    u64 mapsize;
121    int irqnum;
122    /* need this to set the SPI clock */
123    unsigned int opb_freq;
124
125    /* for transfers */
126    int len;
127    int count;
128    /* data buffers */
129    const unsigned char *tx;
130    unsigned char *rx;
131
132    int *gpios;
133
134    struct spi_ppc4xx_regs __iomem *regs; /* pointer to the registers */
135    struct spi_master *master;
136    struct device *dev;
137};
138
139/* need this so we can set the clock in the chipselect routine */
140struct spi_ppc4xx_cs {
141    u8 mode;
142};
143
144static int spi_ppc4xx_txrx(struct spi_device *spi, struct spi_transfer *t)
145{
146    struct ppc4xx_spi *hw;
147    u8 data;
148
149    dev_dbg(&spi->dev, "txrx: tx %p, rx %p, len %d\n",
150        t->tx_buf, t->rx_buf, t->len);
151
152    hw = spi_master_get_devdata(spi->master);
153
154    hw->tx = t->tx_buf;
155    hw->rx = t->rx_buf;
156    hw->len = t->len;
157    hw->count = 0;
158
159    /* send the first byte */
160    data = hw->tx ? hw->tx[0] : 0;
161    out_8(&hw->regs->txd, data);
162    out_8(&hw->regs->cr, SPI_PPC4XX_CR_STR);
163    wait_for_completion(&hw->done);
164
165    return hw->count;
166}
167
168static int spi_ppc4xx_setupxfer(struct spi_device *spi, struct spi_transfer *t)
169{
170    struct ppc4xx_spi *hw = spi_master_get_devdata(spi->master);
171    struct spi_ppc4xx_cs *cs = spi->controller_state;
172    int scr;
173    u8 cdm = 0;
174    u32 speed;
175    u8 bits_per_word;
176
177    /* Start with the generic configuration for this device. */
178    bits_per_word = spi->bits_per_word;
179    speed = spi->max_speed_hz;
180
181    /*
182     * Modify the configuration if the transfer overrides it. Do not allow
183     * the transfer to overwrite the generic configuration with zeros.
184     */
185    if (t) {
186        if (t->bits_per_word)
187            bits_per_word = t->bits_per_word;
188
189        if (t->speed_hz)
190            speed = min(t->speed_hz, spi->max_speed_hz);
191    }
192
193    if (bits_per_word != 8) {
194        dev_err(&spi->dev, "invalid bits-per-word (%d)\n",
195                bits_per_word);
196        return -EINVAL;
197    }
198
199    if (!speed || (speed > spi->max_speed_hz)) {
200        dev_err(&spi->dev, "invalid speed_hz (%d)\n", speed);
201        return -EINVAL;
202    }
203
204    /* Write new configration */
205    out_8(&hw->regs->mode, cs->mode);
206
207    /* Set the clock */
208    /* opb_freq was already divided by 4 */
209    scr = (hw->opb_freq / speed) - 1;
210    if (scr > 0)
211        cdm = min(scr, 0xff);
212
213    dev_dbg(&spi->dev, "setting pre-scaler to %d (hz %d)\n", cdm, speed);
214
215    if (in_8(&hw->regs->cdm) != cdm)
216        out_8(&hw->regs->cdm, cdm);
217
218    spin_lock(&hw->bitbang.lock);
219    if (!hw->bitbang.busy) {
220        hw->bitbang.chipselect(spi, BITBANG_CS_INACTIVE);
221        /* Need to ndelay here? */
222    }
223    spin_unlock(&hw->bitbang.lock);
224
225    return 0;
226}
227
228static int spi_ppc4xx_setup(struct spi_device *spi)
229{
230    struct spi_ppc4xx_cs *cs = spi->controller_state;
231
232    if (spi->bits_per_word != 8) {
233        dev_err(&spi->dev, "invalid bits-per-word (%d)\n",
234            spi->bits_per_word);
235        return -EINVAL;
236    }
237
238    if (!spi->max_speed_hz) {
239        dev_err(&spi->dev, "invalid max_speed_hz (must be non-zero)\n");
240        return -EINVAL;
241    }
242
243    if (cs == NULL) {
244        cs = kzalloc(sizeof *cs, GFP_KERNEL);
245        if (!cs)
246            return -ENOMEM;
247        spi->controller_state = cs;
248    }
249
250    /*
251     * We set all bits of the SPI0_MODE register, so,
252     * no need to read-modify-write
253     */
254    cs->mode = SPI_PPC4XX_MODE_SPE;
255
256    switch (spi->mode & (SPI_CPHA | SPI_CPOL)) {
257    case SPI_MODE_0:
258        cs->mode |= SPI_CLK_MODE0;
259        break;
260    case SPI_MODE_1:
261        cs->mode |= SPI_CLK_MODE1;
262        break;
263    case SPI_MODE_2:
264        cs->mode |= SPI_CLK_MODE2;
265        break;
266    case SPI_MODE_3:
267        cs->mode |= SPI_CLK_MODE3;
268        break;
269    }
270
271    if (spi->mode & SPI_LSB_FIRST)
272        cs->mode |= SPI_PPC4XX_MODE_RD;
273
274    return 0;
275}
276
277static void spi_ppc4xx_chipsel(struct spi_device *spi, int value)
278{
279    struct ppc4xx_spi *hw = spi_master_get_devdata(spi->master);
280    unsigned int cs = spi->chip_select;
281    unsigned int cspol;
282
283    /*
284     * If there are no chip selects at all, or if this is the special
285     * case of a non-existent (dummy) chip select, do nothing.
286     */
287
288    if (!hw->master->num_chipselect || hw->gpios[cs] == -EEXIST)
289        return;
290
291    cspol = spi->mode & SPI_CS_HIGH ? 1 : 0;
292    if (value == BITBANG_CS_INACTIVE)
293        cspol = !cspol;
294
295    gpio_set_value(hw->gpios[cs], cspol);
296}
297
298static irqreturn_t spi_ppc4xx_int(int irq, void *dev_id)
299{
300    struct ppc4xx_spi *hw;
301    u8 status;
302    u8 data;
303    unsigned int count;
304
305    hw = (struct ppc4xx_spi *)dev_id;
306
307    status = in_8(&hw->regs->sr);
308    if (!status)
309        return IRQ_NONE;
310
311    /*
312     * BSY de-asserts one cycle after the transfer is complete. The
313     * interrupt is asserted after the transfer is complete. The exact
314     * relationship is not documented, hence this code.
315     */
316
317    if (unlikely(status & SPI_PPC4XX_SR_BSY)) {
318        u8 lstatus;
319        int cnt = 0;
320
321        dev_dbg(hw->dev, "got interrupt but spi still busy?\n");
322        do {
323            ndelay(10);
324            lstatus = in_8(&hw->regs->sr);
325        } while (++cnt < 100 && lstatus & SPI_PPC4XX_SR_BSY);
326
327        if (cnt >= 100) {
328            dev_err(hw->dev, "busywait: too many loops!\n");
329            complete(&hw->done);
330            return IRQ_HANDLED;
331        } else {
332            /* status is always 1 (RBR) here */
333            status = in_8(&hw->regs->sr);
334            dev_dbg(hw->dev, "loops %d status %x\n", cnt, status);
335        }
336    }
337
338    count = hw->count;
339    hw->count++;
340
341    /* RBR triggered this interrupt. Therefore, data must be ready. */
342    data = in_8(&hw->regs->rxd);
343    if (hw->rx)
344        hw->rx[count] = data;
345
346    count++;
347
348    if (count < hw->len) {
349        data = hw->tx ? hw->tx[count] : 0;
350        out_8(&hw->regs->txd, data);
351        out_8(&hw->regs->cr, SPI_PPC4XX_CR_STR);
352    } else {
353        complete(&hw->done);
354    }
355
356    return IRQ_HANDLED;
357}
358
359static void spi_ppc4xx_cleanup(struct spi_device *spi)
360{
361    kfree(spi->controller_state);
362}
363
364static void spi_ppc4xx_enable(struct ppc4xx_spi *hw)
365{
366    /*
367     * On all 4xx PPC's the SPI bus is shared/multiplexed with
368     * the 2nd I2C bus. We need to enable the the SPI bus before
369     * using it.
370     */
371
372    /* need to clear bit 14 to enable SPC */
373    dcri_clrset(SDR0, SDR0_PFC1, 0x80000000 >> 14, 0);
374}
375
376static void free_gpios(struct ppc4xx_spi *hw)
377{
378    if (hw->master->num_chipselect) {
379        int i;
380        for (i = 0; i < hw->master->num_chipselect; i++)
381            if (gpio_is_valid(hw->gpios[i]))
382                gpio_free(hw->gpios[i]);
383
384        kfree(hw->gpios);
385        hw->gpios = NULL;
386    }
387}
388
389/*
390 * platform_device layer stuff...
391 */
392static int __init spi_ppc4xx_of_probe(struct platform_device *op)
393{
394    struct ppc4xx_spi *hw;
395    struct spi_master *master;
396    struct spi_bitbang *bbp;
397    struct resource resource;
398    struct device_node *np = op->dev.of_node;
399    struct device *dev = &op->dev;
400    struct device_node *opbnp;
401    int ret;
402    int num_gpios;
403    const unsigned int *clk;
404
405    master = spi_alloc_master(dev, sizeof *hw);
406    if (master == NULL)
407        return -ENOMEM;
408    master->dev.of_node = np;
409    dev_set_drvdata(dev, master);
410    hw = spi_master_get_devdata(master);
411    hw->master = spi_master_get(master);
412    hw->dev = dev;
413
414    init_completion(&hw->done);
415
416    /*
417     * A count of zero implies a single SPI device without any chip-select.
418     * Note that of_gpio_count counts all gpios assigned to this spi master.
419     * This includes both "null" gpio's and real ones.
420     */
421    num_gpios = of_gpio_count(np);
422    if (num_gpios) {
423        int i;
424
425        hw->gpios = kzalloc(sizeof(int) * num_gpios, GFP_KERNEL);
426        if (!hw->gpios) {
427            ret = -ENOMEM;
428            goto free_master;
429        }
430
431        for (i = 0; i < num_gpios; i++) {
432            int gpio;
433            enum of_gpio_flags flags;
434
435            gpio = of_get_gpio_flags(np, i, &flags);
436            hw->gpios[i] = gpio;
437
438            if (gpio_is_valid(gpio)) {
439                /* Real CS - set the initial state. */
440                ret = gpio_request(gpio, np->name);
441                if (ret < 0) {
442                    dev_err(dev, "can't request gpio "
443                            "#%d: %d\n", i, ret);
444                    goto free_gpios;
445                }
446
447                gpio_direction_output(gpio,
448                        !!(flags & OF_GPIO_ACTIVE_LOW));
449            } else if (gpio == -EEXIST) {
450                ; /* No CS, but that's OK. */
451            } else {
452                dev_err(dev, "invalid gpio #%d: %d\n", i, gpio);
453                ret = -EINVAL;
454                goto free_gpios;
455            }
456        }
457    }
458
459    /* Setup the state for the bitbang driver */
460    bbp = &hw->bitbang;
461    bbp->master = hw->master;
462    bbp->setup_transfer = spi_ppc4xx_setupxfer;
463    bbp->chipselect = spi_ppc4xx_chipsel;
464    bbp->txrx_bufs = spi_ppc4xx_txrx;
465    bbp->use_dma = 0;
466    bbp->master->setup = spi_ppc4xx_setup;
467    bbp->master->cleanup = spi_ppc4xx_cleanup;
468
469    /* the spi->mode bits understood by this driver: */
470    bbp->master->mode_bits =
471        SPI_CPHA | SPI_CPOL | SPI_CS_HIGH | SPI_LSB_FIRST;
472
473    /* this many pins in all GPIO controllers */
474    bbp->master->num_chipselect = num_gpios;
475
476    /* Get the clock for the OPB */
477    opbnp = of_find_compatible_node(NULL, NULL, "ibm,opb");
478    if (opbnp == NULL) {
479        dev_err(dev, "OPB: cannot find node\n");
480        ret = -ENODEV;
481        goto free_gpios;
482    }
483    /* Get the clock (Hz) for the OPB */
484    clk = of_get_property(opbnp, "clock-frequency", NULL);
485    if (clk == NULL) {
486        dev_err(dev, "OPB: no clock-frequency property set\n");
487        of_node_put(opbnp);
488        ret = -ENODEV;
489        goto free_gpios;
490    }
491    hw->opb_freq = *clk;
492    hw->opb_freq >>= 2;
493    of_node_put(opbnp);
494
495    ret = of_address_to_resource(np, 0, &resource);
496    if (ret) {
497        dev_err(dev, "error while parsing device node resource\n");
498        goto free_gpios;
499    }
500    hw->mapbase = resource.start;
501    hw->mapsize = resource_size(&resource);
502
503    /* Sanity check */
504    if (hw->mapsize < sizeof(struct spi_ppc4xx_regs)) {
505        dev_err(dev, "too small to map registers\n");
506        ret = -EINVAL;
507        goto free_gpios;
508    }
509
510    /* Request IRQ */
511    hw->irqnum = irq_of_parse_and_map(np, 0);
512    ret = request_irq(hw->irqnum, spi_ppc4xx_int,
513              0, "spi_ppc4xx_of", (void *)hw);
514    if (ret) {
515        dev_err(dev, "unable to allocate interrupt\n");
516        goto free_gpios;
517    }
518
519    if (!request_mem_region(hw->mapbase, hw->mapsize, DRIVER_NAME)) {
520        dev_err(dev, "resource unavailable\n");
521        ret = -EBUSY;
522        goto request_mem_error;
523    }
524
525    hw->regs = ioremap(hw->mapbase, sizeof(struct spi_ppc4xx_regs));
526
527    if (!hw->regs) {
528        dev_err(dev, "unable to memory map registers\n");
529        ret = -ENXIO;
530        goto map_io_error;
531    }
532
533    spi_ppc4xx_enable(hw);
534
535    /* Finally register our spi controller */
536    dev->dma_mask = 0;
537    ret = spi_bitbang_start(bbp);
538    if (ret) {
539        dev_err(dev, "failed to register SPI master\n");
540        goto unmap_regs;
541    }
542
543    dev_info(dev, "driver initialized\n");
544
545    return 0;
546
547unmap_regs:
548    iounmap(hw->regs);
549map_io_error:
550    release_mem_region(hw->mapbase, hw->mapsize);
551request_mem_error:
552    free_irq(hw->irqnum, hw);
553free_gpios:
554    free_gpios(hw);
555free_master:
556    dev_set_drvdata(dev, NULL);
557    spi_master_put(master);
558
559    dev_err(dev, "initialization failed\n");
560    return ret;
561}
562
563static int __exit spi_ppc4xx_of_remove(struct platform_device *op)
564{
565    struct spi_master *master = dev_get_drvdata(&op->dev);
566    struct ppc4xx_spi *hw = spi_master_get_devdata(master);
567
568    spi_bitbang_stop(&hw->bitbang);
569    dev_set_drvdata(&op->dev, NULL);
570    release_mem_region(hw->mapbase, hw->mapsize);
571    free_irq(hw->irqnum, hw);
572    iounmap(hw->regs);
573    free_gpios(hw);
574    return 0;
575}
576
577static const struct of_device_id spi_ppc4xx_of_match[] = {
578    { .compatible = "ibm,ppc4xx-spi", },
579    {},
580};
581
582MODULE_DEVICE_TABLE(of, spi_ppc4xx_of_match);
583
584static struct platform_driver spi_ppc4xx_of_driver = {
585    .probe = spi_ppc4xx_of_probe,
586    .remove = __exit_p(spi_ppc4xx_of_remove),
587    .driver = {
588        .name = DRIVER_NAME,
589        .owner = THIS_MODULE,
590        .of_match_table = spi_ppc4xx_of_match,
591    },
592};
593module_platform_driver(spi_ppc4xx_of_driver);
594
595MODULE_AUTHOR("Gary Jennejohn & Stefan Roese");
596MODULE_DESCRIPTION("Simple PPC4xx SPI Driver");
597MODULE_LICENSE("GPL");
598

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