Root/drivers/ssb/driver_gige.c

1/*
2 * Sonics Silicon Backplane
3 * Broadcom Gigabit Ethernet core driver
4 *
5 * Copyright 2008, Broadcom Corporation
6 * Copyright 2008, Michael Buesch <m@bues.ch>
7 *
8 * Licensed under the GNU/GPL. See COPYING for details.
9 */
10
11#include <linux/ssb/ssb.h>
12#include <linux/ssb/ssb_driver_gige.h>
13#include <linux/export.h>
14#include <linux/pci.h>
15#include <linux/pci_regs.h>
16#include <linux/slab.h>
17
18
19/*
20MODULE_DESCRIPTION("SSB Broadcom Gigabit Ethernet driver");
21MODULE_AUTHOR("Michael Buesch");
22MODULE_LICENSE("GPL");
23*/
24
25static const struct ssb_device_id ssb_gige_tbl[] = {
26    SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_ETHERNET_GBIT, SSB_ANY_REV),
27    SSB_DEVTABLE_END
28};
29/* MODULE_DEVICE_TABLE(ssb, ssb_gige_tbl); */
30
31
32static inline u8 gige_read8(struct ssb_gige *dev, u16 offset)
33{
34    return ssb_read8(dev->dev, offset);
35}
36
37static inline u16 gige_read16(struct ssb_gige *dev, u16 offset)
38{
39    return ssb_read16(dev->dev, offset);
40}
41
42static inline u32 gige_read32(struct ssb_gige *dev, u16 offset)
43{
44    return ssb_read32(dev->dev, offset);
45}
46
47static inline void gige_write8(struct ssb_gige *dev,
48                   u16 offset, u8 value)
49{
50    ssb_write8(dev->dev, offset, value);
51}
52
53static inline void gige_write16(struct ssb_gige *dev,
54                u16 offset, u16 value)
55{
56    ssb_write16(dev->dev, offset, value);
57}
58
59static inline void gige_write32(struct ssb_gige *dev,
60                u16 offset, u32 value)
61{
62    ssb_write32(dev->dev, offset, value);
63}
64
65static inline
66u8 gige_pcicfg_read8(struct ssb_gige *dev, unsigned int offset)
67{
68    BUG_ON(offset >= 256);
69    return gige_read8(dev, SSB_GIGE_PCICFG + offset);
70}
71
72static inline
73u16 gige_pcicfg_read16(struct ssb_gige *dev, unsigned int offset)
74{
75    BUG_ON(offset >= 256);
76    return gige_read16(dev, SSB_GIGE_PCICFG + offset);
77}
78
79static inline
80u32 gige_pcicfg_read32(struct ssb_gige *dev, unsigned int offset)
81{
82    BUG_ON(offset >= 256);
83    return gige_read32(dev, SSB_GIGE_PCICFG + offset);
84}
85
86static inline
87void gige_pcicfg_write8(struct ssb_gige *dev,
88            unsigned int offset, u8 value)
89{
90    BUG_ON(offset >= 256);
91    gige_write8(dev, SSB_GIGE_PCICFG + offset, value);
92}
93
94static inline
95void gige_pcicfg_write16(struct ssb_gige *dev,
96             unsigned int offset, u16 value)
97{
98    BUG_ON(offset >= 256);
99    gige_write16(dev, SSB_GIGE_PCICFG + offset, value);
100}
101
102static inline
103void gige_pcicfg_write32(struct ssb_gige *dev,
104             unsigned int offset, u32 value)
105{
106    BUG_ON(offset >= 256);
107    gige_write32(dev, SSB_GIGE_PCICFG + offset, value);
108}
109
110static int __devinit ssb_gige_pci_read_config(struct pci_bus *bus,
111                          unsigned int devfn, int reg,
112                          int size, u32 *val)
113{
114    struct ssb_gige *dev = container_of(bus->ops, struct ssb_gige, pci_ops);
115    unsigned long flags;
116
117    if ((PCI_SLOT(devfn) > 0) || (PCI_FUNC(devfn) > 0))
118        return PCIBIOS_DEVICE_NOT_FOUND;
119    if (reg >= 256)
120        return PCIBIOS_DEVICE_NOT_FOUND;
121
122    spin_lock_irqsave(&dev->lock, flags);
123    switch (size) {
124    case 1:
125        *val = gige_pcicfg_read8(dev, reg);
126        break;
127    case 2:
128        *val = gige_pcicfg_read16(dev, reg);
129        break;
130    case 4:
131        *val = gige_pcicfg_read32(dev, reg);
132        break;
133    default:
134        WARN_ON(1);
135    }
136    spin_unlock_irqrestore(&dev->lock, flags);
137
138    return PCIBIOS_SUCCESSFUL;
139}
140
141static int __devinit ssb_gige_pci_write_config(struct pci_bus *bus,
142                           unsigned int devfn, int reg,
143                           int size, u32 val)
144{
145    struct ssb_gige *dev = container_of(bus->ops, struct ssb_gige, pci_ops);
146    unsigned long flags;
147
148    if ((PCI_SLOT(devfn) > 0) || (PCI_FUNC(devfn) > 0))
149        return PCIBIOS_DEVICE_NOT_FOUND;
150    if (reg >= 256)
151        return PCIBIOS_DEVICE_NOT_FOUND;
152
153    spin_lock_irqsave(&dev->lock, flags);
154    switch (size) {
155    case 1:
156        gige_pcicfg_write8(dev, reg, val);
157        break;
158    case 2:
159        gige_pcicfg_write16(dev, reg, val);
160        break;
161    case 4:
162        gige_pcicfg_write32(dev, reg, val);
163        break;
164    default:
165        WARN_ON(1);
166    }
167    spin_unlock_irqrestore(&dev->lock, flags);
168
169    return PCIBIOS_SUCCESSFUL;
170}
171
172static int __devinit ssb_gige_probe(struct ssb_device *sdev,
173                    const struct ssb_device_id *id)
174{
175    struct ssb_gige *dev;
176    u32 base, tmslow, tmshigh;
177
178    dev = kzalloc(sizeof(*dev), GFP_KERNEL);
179    if (!dev)
180        return -ENOMEM;
181    dev->dev = sdev;
182
183    spin_lock_init(&dev->lock);
184    dev->pci_controller.pci_ops = &dev->pci_ops;
185    dev->pci_controller.io_resource = &dev->io_resource;
186    dev->pci_controller.mem_resource = &dev->mem_resource;
187    dev->pci_controller.io_map_base = 0x800;
188    dev->pci_ops.read = ssb_gige_pci_read_config;
189    dev->pci_ops.write = ssb_gige_pci_write_config;
190
191    dev->io_resource.name = SSB_GIGE_IO_RES_NAME;
192    dev->io_resource.start = 0x800;
193    dev->io_resource.end = 0x8FF;
194    dev->io_resource.flags = IORESOURCE_IO | IORESOURCE_PCI_FIXED;
195
196    if (!ssb_device_is_enabled(sdev))
197        ssb_device_enable(sdev, 0);
198
199    /* Setup BAR0. This is a 64k MMIO region. */
200    base = ssb_admatch_base(ssb_read32(sdev, SSB_ADMATCH1));
201    gige_pcicfg_write32(dev, PCI_BASE_ADDRESS_0, base);
202    gige_pcicfg_write32(dev, PCI_BASE_ADDRESS_1, 0);
203
204    dev->mem_resource.name = SSB_GIGE_MEM_RES_NAME;
205    dev->mem_resource.start = base;
206    dev->mem_resource.end = base + 0x10000 - 1;
207    dev->mem_resource.flags = IORESOURCE_MEM | IORESOURCE_PCI_FIXED;
208
209    /* Enable the memory region. */
210    gige_pcicfg_write16(dev, PCI_COMMAND,
211                gige_pcicfg_read16(dev, PCI_COMMAND)
212                | PCI_COMMAND_MEMORY);
213
214    /* Write flushing is controlled by the Flush Status Control register.
215     * We want to flush every register write with a timeout and we want
216     * to disable the IRQ mask while flushing to avoid concurrency.
217     * Note that automatic write flushing does _not_ work from
218     * an IRQ handler. The driver must flush manually by reading a register.
219     */
220    gige_write32(dev, SSB_GIGE_SHIM_FLUSHSTAT, 0x00000068);
221
222    /* Check if we have an RGMII or GMII PHY-bus.
223     * On RGMII do not bypass the DLLs */
224    tmslow = ssb_read32(sdev, SSB_TMSLOW);
225    tmshigh = ssb_read32(sdev, SSB_TMSHIGH);
226    if (tmshigh & SSB_GIGE_TMSHIGH_RGMII) {
227        tmslow &= ~SSB_GIGE_TMSLOW_TXBYPASS;
228        tmslow &= ~SSB_GIGE_TMSLOW_RXBYPASS;
229        dev->has_rgmii = 1;
230    } else {
231        tmslow |= SSB_GIGE_TMSLOW_TXBYPASS;
232        tmslow |= SSB_GIGE_TMSLOW_RXBYPASS;
233        dev->has_rgmii = 0;
234    }
235    tmslow |= SSB_GIGE_TMSLOW_DLLEN;
236    ssb_write32(sdev, SSB_TMSLOW, tmslow);
237
238    ssb_set_drvdata(sdev, dev);
239    register_pci_controller(&dev->pci_controller);
240
241    return 0;
242}
243
244bool pdev_is_ssb_gige_core(struct pci_dev *pdev)
245{
246    if (!pdev->resource[0].name)
247        return 0;
248    return (strcmp(pdev->resource[0].name, SSB_GIGE_MEM_RES_NAME) == 0);
249}
250EXPORT_SYMBOL(pdev_is_ssb_gige_core);
251
252int ssb_gige_pcibios_plat_dev_init(struct ssb_device *sdev,
253                   struct pci_dev *pdev)
254{
255    struct ssb_gige *dev = ssb_get_drvdata(sdev);
256    struct resource *res;
257
258    if (pdev->bus->ops != &dev->pci_ops) {
259        /* The PCI device is not on this SSB GigE bridge device. */
260        return -ENODEV;
261    }
262
263    /* Fixup the PCI resources. */
264    res = &(pdev->resource[0]);
265    res->flags = IORESOURCE_MEM | IORESOURCE_PCI_FIXED;
266    res->name = dev->mem_resource.name;
267    res->start = dev->mem_resource.start;
268    res->end = dev->mem_resource.end;
269
270    /* Fixup interrupt lines. */
271    pdev->irq = ssb_mips_irq(sdev) + 2;
272    pci_write_config_byte(pdev, PCI_INTERRUPT_LINE, pdev->irq);
273
274    return 0;
275}
276
277int ssb_gige_map_irq(struct ssb_device *sdev,
278             const struct pci_dev *pdev)
279{
280    struct ssb_gige *dev = ssb_get_drvdata(sdev);
281
282    if (pdev->bus->ops != &dev->pci_ops) {
283        /* The PCI device is not on this SSB GigE bridge device. */
284        return -ENODEV;
285    }
286
287    return ssb_mips_irq(sdev) + 2;
288}
289
290static struct ssb_driver ssb_gige_driver = {
291    .name = "BCM-GigE",
292    .id_table = ssb_gige_tbl,
293    .probe = ssb_gige_probe,
294};
295
296int ssb_gige_init(void)
297{
298    return ssb_driver_register(&ssb_gige_driver);
299}
300

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