Root/drivers/staging/csr/csr_wifi_hip_chiphelper_private.h

1/*****************************************************************************
2
3            (c) Cambridge Silicon Radio Limited 2011
4            All rights reserved and confidential information of CSR
5
6            Refer to LICENSE.txt included with this source for details
7            on the license terms.
8
9*****************************************************************************/
10
11#ifndef CSR_WIFI_HIP_CHIPHELPER_PRIVATE_H__
12#define CSR_WIFI_HIP_CHIPHELPER_PRIVATE_H__
13
14
15#include "csr_wifi_hip_chiphelper.h"
16
17#ifdef __cplusplus
18extern "C" {
19#endif /* __cplusplus */
20
21/* This GP stuff should be somewhere else? */
22
23/* Memory spaces encoded in top byte of Generic Pointer type */
24#define UNIFI_SH_DMEM 0x01 /* Shared Data Memory */
25#define UNIFI_EXT_FLASH 0x02 /* External FLASH */
26#define UNIFI_EXT_SRAM 0x03 /* External SRAM */
27#define UNIFI_REGISTERS 0x04 /* Registers */
28#define UNIFI_PHY_DMEM 0x10 /* PHY Data Memory */
29#define UNIFI_PHY_PMEM 0x11 /* PHY Program Memory */
30#define UNIFI_PHY_ROM 0x12 /* PHY ROM */
31#define UNIFI_MAC_DMEM 0x20 /* MAC Data Memory */
32#define UNIFI_MAC_PMEM 0x21 /* MAC Program Memory */
33#define UNIFI_MAC_ROM 0x22 /* MAC ROM */
34#define UNIFI_BT_DMEM 0x30 /* BT Data Memory */
35#define UNIFI_BT_PMEM 0x31 /* BT Program Memory */
36#define UNIFI_BT_ROM 0x32 /* BT ROM */
37
38#define MAKE_GP(R, O) (((UNIFI_ ## R) << 24) | (O))
39#define GP_OFFSET(GP) ((GP) & 0xFFFFFF)
40#define GP_SPACE(GP) (((GP) >> 24) & 0xFF)
41
42
43/* Address value pairs */
44struct val_array_t
45{
46    u32 len;
47    const struct chip_helper_init_values *vals;
48};
49
50/* Just a (counted) u16 array */
51struct data_array_t
52{
53    u32 len;
54    const u16 *vals;
55};
56
57struct reset_prog_t
58{
59    u32 len;
60    const struct chip_helper_reset_values *vals;
61};
62
63/* The addresses of registers that are equivalent but on
64   different host transports. */
65struct chip_map_address_t
66{
67    u16 spi, host;
68};
69
70struct map_array_t
71{
72    u32 len;
73    const struct chip_map_address_t *vals;
74};
75
76struct chip_device_regs_per_transport_t
77{
78    u16 dbg_proc_select;
79    u16 dbg_stop_status;
80    u16 window1_page; /* PROG_PMEM1 or GW1 */
81    u16 window2_page; /* PROG_PMEM2 or GW2 */
82    u16 window3_page; /* SHARED or GW3 */
83    u16 io_log_addr;
84};
85
86struct chip_device_regs_t
87{
88    u16 gbl_chip_version;
89    u16 gbl_misc_enables;
90    u16 dbg_emu_cmd;
91    struct chip_device_regs_per_transport_t host;
92    struct chip_device_regs_per_transport_t spi;
93    u16 dbg_reset;
94    u16 dbg_reset_value;
95    u16 dbg_reset_warn;
96    u16 dbg_reset_warn_value;
97    u16 dbg_reset_result;
98    u16 xap_pch;
99    u16 xap_pcl;
100    u16 proc_pc_snoop;
101    u16 watchdog_disable;
102    u16 mailbox0;
103    u16 mailbox1;
104    u16 mailbox2;
105    u16 mailbox3;
106    u16 sdio_host_int;
107    u16 shared_io_interrupt;
108    u16 sdio_hip_handshake;
109    u16 coex_status; /* Allows WAPI detection */
110};
111
112/* If allowed is false then this window does not provide this
113   type of access.
114   This describes how addresses should be shifted to make the
115   "page" address. The address is shifted left by 'page_shift'
116   and then has 'page_offset' added. This value should then be
117   written to the page register. */
118struct window_shift_info_t
119{
120    s32 allowed;
121    u32 page_shift;
122    u16 page_offset;
123};
124
125/* Each window has an address and size. These are obvious. It then
126   has a description for each type of memory that might be accessed
127   through it. There might also be a start to the offset of the window.
128   This means that that number of addresses at the start of the window
129   are unusable. */
130struct window_info_t
131{
132    u16 address;
133    u16 size;
134    u16 blocked;
135    const struct window_shift_info_t *mode;
136};
137
138/* If GBL_CHIP_VERSION and'ed with 'mask' and is equal to 'result'
139   then this is the correct set of info. If pre_bc7 is true then the
140   address of GBL_CHIP_VERSION is FF9A, else its FE81. */
141struct chip_version_t
142{
143    s32 pre_bc7;
144    u16 mask;
145    u16 result;
146    u8 sdio;
147};
148
149struct chip_device_desc_t
150{
151    struct chip_version_t chip_version;
152
153    /* This is a text string that a human might find useful (BC02, UF105x) */
154    const char *friendly_name;
155    /* This is what we show to customers */
156    const char *marketing_name;
157
158    /* Initialisation values to write following a reset */
159    struct val_array_t init;
160
161    /* Binary sequence for hard reset */
162    struct reset_prog_t reset_prog;
163
164    /* The register map */
165    const struct chip_device_regs_t *regs;
166
167    /* Some misc. info on the chip */
168    struct
169    {
170        u32 has_flash : 1;
171        u32 has_ext_sram : 1;
172        u32 has_rom : 1;
173        u32 has_bt : 1;
174        u32 has_wlan : 1;
175    } bools;
176
177    /* This table is used to remap register addresses depending on what
178       host interface is used. On the BC7 and later chips there are
179       multiple sets of memory window registers, on for each host
180       interafce (SDIO / SPI). The correct one is needed. */
181    struct map_array_t map;
182
183    /* The offsets into the program address space of the different types of memory.
184       The RAM offset is probably the most useful. */
185    struct
186    {
187        u32 ram;
188        u32 rom;
189        u32 flash;
190        u32 ext_sram;
191    } prog_offset;
192
193    /* The offsets into the data address space of interesting things. */
194    struct
195    {
196        u16 ram;
197        /* maybe add shared / page tables? */
198    } data_offset;
199
200    /* Information on the different windows */
201    const struct window_info_t *windows[CHIP_HELPER_WINDOW_COUNT];
202};
203
204#ifdef __cplusplus
205}
206#endif /* __cplusplus */
207
208#endif /* CSR_WIFI_HIP_CHIPHELPER_PRIVATE_H__ */
209

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