Root/drivers/staging/rtl8192e/rtl819x_HT.h

1/******************************************************************************
2 * Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved.
3 *
4 * This program is distributed in the hope that it will be useful, but WITHOUT
5 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
6 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
7 * more details.
8 *
9 * You should have received a copy of the GNU General Public License along with
10 * this program; if not, write to the Free Software Foundation, Inc.,
11 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
12 *
13 * The full GNU General Public License is included in this distribution in the
14 * file called LICENSE.
15 *
16 * Contact Information:
17 * wlanfae <wlanfae@realtek.com>
18******************************************************************************/
19#ifndef _RTL819XU_HTTYPE_H_
20#define _RTL819XU_HTTYPE_H_
21
22
23#define HT_OPMODE_NO_PROTECT 0
24#define HT_OPMODE_OPTIONAL 1
25#define HT_OPMODE_40MHZ_PROTECT 2
26#define HT_OPMODE_MIXED 3
27
28#define MIMO_PS_STATIC 0
29#define MIMO_PS_DYNAMIC 1
30#define MIMO_PS_NOLIMIT 3
31
32
33
34#define sHTCLng 4
35
36
37#define HT_SUPPORTED_MCS_1SS_BITMAP 0x000000ff
38#define HT_SUPPORTED_MCS_2SS_BITMAP 0x0000ff00
39#define HT_SUPPORTED_MCS_1SS_2SS_BITMAP \
40    (HT_MCS_1SS_BITMAP | HT_MCS_1SS_2SS_BITMAP)
41
42enum ht_mcs_rate {
43    HT_MCS0 = 0x00000001,
44    HT_MCS1 = 0x00000002,
45    HT_MCS2 = 0x00000004,
46    HT_MCS3 = 0x00000008,
47    HT_MCS4 = 0x00000010,
48    HT_MCS5 = 0x00000020,
49    HT_MCS6 = 0x00000040,
50    HT_MCS7 = 0x00000080,
51    HT_MCS8 = 0x00000100,
52    HT_MCS9 = 0x00000200,
53    HT_MCS10 = 0x00000400,
54    HT_MCS11 = 0x00000800,
55    HT_MCS12 = 0x00001000,
56    HT_MCS13 = 0x00002000,
57    HT_MCS14 = 0x00004000,
58    HT_MCS15 = 0x00008000,
59};
60
61enum ht_channel_width {
62    HT_CHANNEL_WIDTH_20 = 0,
63    HT_CHANNEL_WIDTH_20_40 = 1,
64};
65
66enum ht_extchnl_offset {
67    HT_EXTCHNL_OFFSET_NO_EXT = 0,
68    HT_EXTCHNL_OFFSET_UPPER = 1,
69    HT_EXTCHNL_OFFSET_NO_DEF = 2,
70    HT_EXTCHNL_OFFSET_LOWER = 3,
71};
72
73enum chnl_op {
74    CHNLOP_NONE = 0,
75    CHNLOP_SCAN = 1,
76    CHNLOP_SWBW = 2,
77    CHNLOP_SWCHNL = 3,
78};
79
80#define CHHLOP_IN_PROGRESS(_pHTInfo) \
81        ((_pHTInfo)->ChnlOp > CHNLOP_NONE) ? true : false
82
83/*
84union ht_capability {
85    u16 ShortData;
86    u8 CharData[2];
87    struct
88    {
89        u16 AdvCoding:1;
90        u16 ChlWidth:1;
91        u16 MimoPwrSave:2;
92        u16 GreenField:1;
93        u16 ShortGI20Mhz:1;
94        u16 ShortGI40Mhz:1;
95        u16 STBC:1;
96        u16 BeamForm:1;
97        u16 DelayBA:1;
98        u16 MaxAMSDUSize:1;
99        u16 DssCCk:1;
100        u16 PSMP:1;
101        u16 Rsvd:3;
102    }Field;
103};
104
105union ht_capability_macpara {
106    u8 ShortData;
107    u8 CharData[1];
108    struct
109    {
110        u8 MaxRxAMPDU:2;
111        u8 MPDUDensity:2;
112        u8 Rsvd:4;
113    }Field;
114};
115*/
116
117enum ht_action {
118    ACT_RECOMMAND_WIDTH = 0,
119    ACT_MIMO_PWR_SAVE = 1,
120    ACT_PSMP = 2,
121    ACT_SET_PCO_PHASE = 3,
122    ACT_MIMO_CHL_MEASURE = 4,
123    ACT_RECIPROCITY_CORRECT = 5,
124    ACT_MIMO_CSI_MATRICS = 6,
125    ACT_MIMO_NOCOMPR_STEER = 7,
126    ACT_MIMO_COMPR_STEER = 8,
127    ACT_ANTENNA_SELECT = 9,
128};
129
130
131enum ht_bw40_sc {
132    SC_MODE_DUPLICATE = 0,
133    SC_MODE_LOWER = 1,
134    SC_MODE_UPPER = 2,
135    SC_MODE_FULL40MHZ = 3,
136};
137
138struct ht_capab_ele {
139
140    u8 AdvCoding:1;
141    u8 ChlWidth:1;
142    u8 MimoPwrSave:2;
143    u8 GreenField:1;
144    u8 ShortGI20Mhz:1;
145    u8 ShortGI40Mhz:1;
146    u8 TxSTBC:1;
147    u8 RxSTBC:2;
148    u8 DelayBA:1;
149    u8 MaxAMSDUSize:1;
150    u8 DssCCk:1;
151    u8 PSMP:1;
152    u8 Rsvd1:1;
153    u8 LSigTxopProtect:1;
154
155    u8 MaxRxAMPDUFactor:2;
156    u8 MPDUDensity:3;
157    u8 Rsvd2:3;
158
159    u8 MCS[16];
160
161
162    u16 ExtHTCapInfo;
163
164    u8 TxBFCap[4];
165
166    u8 ASCap;
167
168} __packed;
169
170
171struct ht_info_ele {
172    u8 ControlChl;
173
174    u8 ExtChlOffset:2;
175    u8 RecommemdedTxWidth:1;
176    u8 RIFS:1;
177    u8 PSMPAccessOnly:1;
178    u8 SrvIntGranularity:3;
179
180    u8 OptMode:2;
181    u8 NonGFDevPresent:1;
182    u8 Revd1:5;
183    u8 Revd2:8;
184
185    u8 Rsvd3:6;
186    u8 DualBeacon:1;
187    u8 DualCTSProtect:1;
188
189    u8 SecondaryBeacon:1;
190    u8 LSigTxopProtectFull:1;
191    u8 PcoActive:1;
192    u8 PcoPhase:1;
193    u8 Rsvd4:4;
194
195    u8 BasicMSC[16];
196} __packed;
197
198struct mimops_ctrl {
199    u8 MimoPsEnable:1;
200    u8 MimoPsMode:1;
201    u8 Reserved:6;
202};
203
204enum ht_spec_ver {
205    HT_SPEC_VER_IEEE = 0,
206    HT_SPEC_VER_EWC = 1,
207};
208
209enum ht_aggre_mode {
210    HT_AGG_AUTO = 0,
211    HT_AGG_FORCE_ENABLE = 1,
212    HT_AGG_FORCE_DISABLE = 2,
213};
214
215
216struct rt_hi_throughput {
217    u8 bEnableHT;
218    u8 bCurrentHTSupport;
219
220    u8 bRegBW40MHz;
221    u8 bCurBW40MHz;
222
223    u8 bRegShortGI40MHz;
224    u8 bCurShortGI40MHz;
225
226    u8 bRegShortGI20MHz;
227    u8 bCurShortGI20MHz;
228
229    u8 bRegSuppCCK;
230    u8 bCurSuppCCK;
231
232    enum ht_spec_ver ePeerHTSpecVer;
233
234
235    struct ht_capab_ele SelfHTCap;
236    struct ht_info_ele SelfHTInfo;
237
238    u8 PeerHTCapBuf[32];
239    u8 PeerHTInfoBuf[32];
240
241
242    u8 bAMSDU_Support;
243    u16 nAMSDU_MaxSize;
244    u8 bCurrent_AMSDU_Support;
245    u16 nCurrent_AMSDU_MaxSize;
246
247    u8 bAMPDUEnable;
248    u8 bCurrentAMPDUEnable;
249    u8 AMPDU_Factor;
250    u8 CurrentAMPDUFactor;
251    u8 MPDU_Density;
252    u8 CurrentMPDUDensity;
253
254    enum ht_aggre_mode ForcedAMPDUMode;
255    u8 ForcedAMPDUFactor;
256    u8 ForcedMPDUDensity;
257
258    enum ht_aggre_mode ForcedAMSDUMode;
259    u16 ForcedAMSDUMaxSize;
260
261    u8 bForcedShortGI;
262
263    u8 CurrentOpMode;
264
265    u8 SelfMimoPs;
266    u8 PeerMimoPs;
267
268    enum ht_extchnl_offset CurSTAExtChnlOffset;
269    u8 bCurTxBW40MHz;
270    u8 PeerBandwidth;
271
272    u8 bSwBwInProgress;
273    enum chnl_op ChnlOp;
274    u8 SwBwStep;
275
276    u8 bRegRT2RTAggregation;
277    u8 RT2RT_HT_Mode;
278    u8 bCurrentRT2RTAggregation;
279    u8 bCurrentRT2RTLongSlotTime;
280    u8 szRT2RTAggBuffer[10];
281
282    u8 bRegRxReorderEnable;
283    u8 bCurRxReorderEnable;
284    u8 RxReorderWinSize;
285    u8 RxReorderPendingTime;
286    u16 RxReorderDropCounter;
287
288    u8 bIsPeerBcm;
289
290    u8 IOTPeer;
291    u32 IOTAction;
292    u8 IOTRaFunc;
293
294    u8 bWAIotBroadcom;
295    u8 WAIotTH;
296
297    u8 bAcceptAddbaReq;
298} __packed;
299
300
301
302struct rt_htinfo_sta_entry {
303    u8 bEnableHT;
304
305    u8 bSupportCck;
306
307    u16 AMSDU_MaxSize;
308
309    u8 AMPDU_Factor;
310    u8 MPDU_Density;
311
312    u8 HTHighestOperaRate;
313
314    u8 bBw40MHz;
315
316    u8 bCurTxBW40MHz;
317
318    u8 bCurShortGI20MHz;
319
320    u8 bCurShortGI40MHz;
321
322    u8 MimoPs;
323
324    u8 McsRateSet[16];
325
326    u8 bCurRxReorderEnable;
327
328    u16 nAMSDU_MaxSize;
329
330};
331
332
333
334
335
336
337struct bss_ht {
338
339    u8 bdSupportHT;
340
341    u8 bdHTCapBuf[32];
342    u16 bdHTCapLen;
343    u8 bdHTInfoBuf[32];
344    u16 bdHTInfoLen;
345
346    enum ht_spec_ver bdHTSpecVer;
347    enum ht_channel_width bdBandWidth;
348
349    u8 bdRT2RTAggregation;
350    u8 bdRT2RTLongSlotTime;
351    u8 RT2RT_HT_Mode;
352    u8 bdHT1R;
353};
354
355struct mimo_rssi {
356    u32 EnableAntenna;
357    u32 AntennaA;
358    u32 AntennaB;
359    u32 AntennaC;
360    u32 AntennaD;
361    u32 Average;
362};
363
364struct mimo_evm {
365    u32 EVM1;
366    u32 EVM2;
367};
368
369struct false_alarm_stats {
370    u32 Cnt_Parity_Fail;
371    u32 Cnt_Rate_Illegal;
372    u32 Cnt_Crc8_fail;
373    u32 Cnt_Mcs_fail;
374    u32 Cnt_Ofdm_fail;
375    u32 Cnt_Cck_fail;
376    u32 Cnt_all;
377};
378
379
380extern u8 MCS_FILTER_ALL[16];
381extern u8 MCS_FILTER_1SS[16];
382
383#define PICK_RATE(_nLegacyRate, _nMcsRate) \
384        ((_nMcsRate == 0) ? (_nLegacyRate&0x7f) : (_nMcsRate))
385#define LEGACY_WIRELESS_MODE IEEE_MODE_MASK
386
387#define CURRENT_RATE(WirelessMode, LegacyRate, HTRate) \
388            ((WirelessMode & (LEGACY_WIRELESS_MODE)) != 0) ? \
389            (LegacyRate) : (PICK_RATE(LegacyRate, HTRate))
390
391
392
393#define RATE_ADPT_1SS_MASK 0xFF
394#define RATE_ADPT_2SS_MASK 0xF0
395#define RATE_ADPT_MCS32_MASK 0x01
396
397#define IS_11N_MCS_RATE(rate) (rate&0x80)
398
399enum ht_aggre_size {
400    HT_AGG_SIZE_8K = 0,
401    HT_AGG_SIZE_16K = 1,
402    HT_AGG_SIZE_32K = 2,
403    HT_AGG_SIZE_64K = 3,
404};
405
406enum ht_iot_peer {
407    HT_IOT_PEER_UNKNOWN = 0,
408    HT_IOT_PEER_REALTEK = 1,
409    HT_IOT_PEER_REALTEK_92SE = 2,
410    HT_IOT_PEER_BROADCOM = 3,
411    HT_IOT_PEER_RALINK = 4,
412    HT_IOT_PEER_ATHEROS = 5,
413    HT_IOT_PEER_CISCO = 6,
414    HT_IOT_PEER_MARVELL = 7,
415    HT_IOT_PEER_92U_SOFTAP = 8,
416    HT_IOT_PEER_SELF_SOFTAP = 9,
417    HT_IOT_PEER_AIRGO = 10,
418    HT_IOT_PEER_MAX = 11,
419};
420
421enum ht_iot_peer_subtype {
422    HT_IOT_PEER_ATHEROS_DIR635 = 0,
423};
424
425enum ht_iot_action {
426    HT_IOT_ACT_TX_USE_AMSDU_4K = 0x00000001,
427    HT_IOT_ACT_TX_USE_AMSDU_8K = 0x00000002,
428    HT_IOT_ACT_DISABLE_MCS14 = 0x00000004,
429    HT_IOT_ACT_DISABLE_MCS15 = 0x00000008,
430    HT_IOT_ACT_DISABLE_ALL_2SS = 0x00000010,
431    HT_IOT_ACT_DISABLE_EDCA_TURBO = 0x00000020,
432    HT_IOT_ACT_MGNT_USE_CCK_6M = 0x00000040,
433    HT_IOT_ACT_CDD_FSYNC = 0x00000080,
434    HT_IOT_ACT_PURE_N_MODE = 0x00000100,
435    HT_IOT_ACT_FORCED_CTS2SELF = 0x00000200,
436    HT_IOT_ACT_FORCED_RTS = 0x00000400,
437    HT_IOT_ACT_AMSDU_ENABLE = 0x00000800,
438    HT_IOT_ACT_REJECT_ADDBA_REQ = 0x00001000,
439    HT_IOT_ACT_ALLOW_PEER_AGG_ONE_PKT = 0x00002000,
440    HT_IOT_ACT_EDCA_BIAS_ON_RX = 0x00004000,
441
442    HT_IOT_ACT_HYBRID_AGGREGATION = 0x00010000,
443    HT_IOT_ACT_DISABLE_SHORT_GI = 0x00020000,
444    HT_IOT_ACT_DISABLE_HIGH_POWER = 0x00040000,
445    HT_IOT_ACT_DISABLE_TX_40_MHZ = 0x00080000,
446    HT_IOT_ACT_TX_NO_AGGREGATION = 0x00100000,
447    HT_IOT_ACT_DISABLE_TX_2SS = 0x00200000,
448
449    HT_IOT_ACT_MID_HIGHPOWER = 0x00400000,
450    HT_IOT_ACT_NULL_DATA_POWER_SAVING = 0x00800000,
451
452    HT_IOT_ACT_DISABLE_CCK_RATE = 0x01000000,
453    HT_IOT_ACT_FORCED_ENABLE_BE_TXOP = 0x02000000,
454    HT_IOT_ACT_WA_IOT_Broadcom = 0x04000000,
455
456    HT_IOT_ACT_DISABLE_RX_40MHZ_SHORT_GI = 0x08000000,
457
458};
459
460enum ht_iot_rafunc {
461    HT_IOT_RAFUNC_DISABLE_ALL = 0x00,
462    HT_IOT_RAFUNC_PEER_1R = 0x01,
463    HT_IOT_RAFUNC_TX_AMSDU = 0x02,
464};
465
466enum rt_ht_capability {
467    RT_HT_CAP_USE_TURBO_AGGR = 0x01,
468    RT_HT_CAP_USE_LONG_PREAMBLE = 0x02,
469    RT_HT_CAP_USE_AMPDU = 0x04,
470    RT_HT_CAP_USE_WOW = 0x8,
471    RT_HT_CAP_USE_SOFTAP = 0x10,
472    RT_HT_CAP_USE_92SE = 0x20,
473};
474
475#endif
476

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