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1 | /* |
2 | * nv_tco 0.01: TCO timer driver for NV chipsets |
3 | * |
4 | * (c) Copyright 2005 Google Inc., All Rights Reserved. |
5 | * |
6 | * Based off i8xx_tco.c: |
7 | * (c) Copyright 2000 kernel concepts <nils@kernelconcepts.de>, All Rights |
8 | * Reserved. |
9 | * http://www.kernelconcepts.de |
10 | * |
11 | * This program is free software; you can redistribute it and/or |
12 | * modify it under the terms of the GNU General Public License |
13 | * as published by the Free Software Foundation; either version |
14 | * 2 of the License, or (at your option) any later version. |
15 | * |
16 | * TCO timer driver for NV chipsets |
17 | * based on softdog.c by Alan Cox <alan@redhat.com> |
18 | */ |
19 | |
20 | /* |
21 | * Includes, defines, variables, module parameters, ... |
22 | */ |
23 | |
24 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
25 | |
26 | #include <linux/module.h> |
27 | #include <linux/moduleparam.h> |
28 | #include <linux/types.h> |
29 | #include <linux/miscdevice.h> |
30 | #include <linux/watchdog.h> |
31 | #include <linux/init.h> |
32 | #include <linux/fs.h> |
33 | #include <linux/pci.h> |
34 | #include <linux/ioport.h> |
35 | #include <linux/jiffies.h> |
36 | #include <linux/platform_device.h> |
37 | #include <linux/uaccess.h> |
38 | #include <linux/io.h> |
39 | |
40 | #include "nv_tco.h" |
41 | |
42 | /* Module and version information */ |
43 | #define TCO_VERSION "0.01" |
44 | #define TCO_MODULE_NAME "NV_TCO" |
45 | #define TCO_DRIVER_NAME TCO_MODULE_NAME ", v" TCO_VERSION |
46 | |
47 | /* internal variables */ |
48 | static unsigned int tcobase; |
49 | static DEFINE_SPINLOCK(tco_lock); /* Guards the hardware */ |
50 | static unsigned long timer_alive; |
51 | static char tco_expect_close; |
52 | static struct pci_dev *tco_pci; |
53 | |
54 | /* the watchdog platform device */ |
55 | static struct platform_device *nv_tco_platform_device; |
56 | |
57 | /* module parameters */ |
58 | #define WATCHDOG_HEARTBEAT 30 /* 30 sec default heartbeat (2<heartbeat<39) */ |
59 | static int heartbeat = WATCHDOG_HEARTBEAT; /* in seconds */ |
60 | module_param(heartbeat, int, 0); |
61 | MODULE_PARM_DESC(heartbeat, "Watchdog heartbeat in seconds. (2<heartbeat<39, " |
62 | "default=" __MODULE_STRING(WATCHDOG_HEARTBEAT) ")"); |
63 | |
64 | static bool nowayout = WATCHDOG_NOWAYOUT; |
65 | module_param(nowayout, bool, 0); |
66 | MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started" |
67 | " (default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); |
68 | |
69 | /* |
70 | * Some TCO specific functions |
71 | */ |
72 | static inline unsigned char seconds_to_ticks(int seconds) |
73 | { |
74 | /* the internal timer is stored as ticks which decrement |
75 | * every 0.6 seconds */ |
76 | return (seconds * 10) / 6; |
77 | } |
78 | |
79 | static void tco_timer_start(void) |
80 | { |
81 | u32 val; |
82 | unsigned long flags; |
83 | |
84 | spin_lock_irqsave(&tco_lock, flags); |
85 | val = inl(TCO_CNT(tcobase)); |
86 | val &= ~TCO_CNT_TCOHALT; |
87 | outl(val, TCO_CNT(tcobase)); |
88 | spin_unlock_irqrestore(&tco_lock, flags); |
89 | } |
90 | |
91 | static void tco_timer_stop(void) |
92 | { |
93 | u32 val; |
94 | unsigned long flags; |
95 | |
96 | spin_lock_irqsave(&tco_lock, flags); |
97 | val = inl(TCO_CNT(tcobase)); |
98 | val |= TCO_CNT_TCOHALT; |
99 | outl(val, TCO_CNT(tcobase)); |
100 | spin_unlock_irqrestore(&tco_lock, flags); |
101 | } |
102 | |
103 | static void tco_timer_keepalive(void) |
104 | { |
105 | unsigned long flags; |
106 | |
107 | spin_lock_irqsave(&tco_lock, flags); |
108 | outb(0x01, TCO_RLD(tcobase)); |
109 | spin_unlock_irqrestore(&tco_lock, flags); |
110 | } |
111 | |
112 | static int tco_timer_set_heartbeat(int t) |
113 | { |
114 | int ret = 0; |
115 | unsigned char tmrval; |
116 | unsigned long flags; |
117 | u8 val; |
118 | |
119 | /* |
120 | * note seconds_to_ticks(t) > t, so if t > 0x3f, so is |
121 | * tmrval=seconds_to_ticks(t). Check that the count in seconds isn't |
122 | * out of range on it's own (to avoid overflow in tmrval). |
123 | */ |
124 | if (t < 0 || t > 0x3f) |
125 | return -EINVAL; |
126 | tmrval = seconds_to_ticks(t); |
127 | |
128 | /* "Values of 0h-3h are ignored and should not be attempted" */ |
129 | if (tmrval > 0x3f || tmrval < 0x04) |
130 | return -EINVAL; |
131 | |
132 | /* Write new heartbeat to watchdog */ |
133 | spin_lock_irqsave(&tco_lock, flags); |
134 | val = inb(TCO_TMR(tcobase)); |
135 | val &= 0xc0; |
136 | val |= tmrval; |
137 | outb(val, TCO_TMR(tcobase)); |
138 | val = inb(TCO_TMR(tcobase)); |
139 | |
140 | if ((val & 0x3f) != tmrval) |
141 | ret = -EINVAL; |
142 | spin_unlock_irqrestore(&tco_lock, flags); |
143 | |
144 | if (ret) |
145 | return ret; |
146 | |
147 | heartbeat = t; |
148 | return 0; |
149 | } |
150 | |
151 | /* |
152 | * /dev/watchdog handling |
153 | */ |
154 | |
155 | static int nv_tco_open(struct inode *inode, struct file *file) |
156 | { |
157 | /* /dev/watchdog can only be opened once */ |
158 | if (test_and_set_bit(0, &timer_alive)) |
159 | return -EBUSY; |
160 | |
161 | /* Reload and activate timer */ |
162 | tco_timer_keepalive(); |
163 | tco_timer_start(); |
164 | return nonseekable_open(inode, file); |
165 | } |
166 | |
167 | static int nv_tco_release(struct inode *inode, struct file *file) |
168 | { |
169 | /* Shut off the timer */ |
170 | if (tco_expect_close == 42) { |
171 | tco_timer_stop(); |
172 | } else { |
173 | pr_crit("Unexpected close, not stopping watchdog!\n"); |
174 | tco_timer_keepalive(); |
175 | } |
176 | clear_bit(0, &timer_alive); |
177 | tco_expect_close = 0; |
178 | return 0; |
179 | } |
180 | |
181 | static ssize_t nv_tco_write(struct file *file, const char __user *data, |
182 | size_t len, loff_t *ppos) |
183 | { |
184 | /* See if we got the magic character 'V' and reload the timer */ |
185 | if (len) { |
186 | if (!nowayout) { |
187 | size_t i; |
188 | |
189 | /* |
190 | * note: just in case someone wrote the magic character |
191 | * five months ago... |
192 | */ |
193 | tco_expect_close = 0; |
194 | |
195 | /* |
196 | * scan to see whether or not we got the magic |
197 | * character |
198 | */ |
199 | for (i = 0; i != len; i++) { |
200 | char c; |
201 | if (get_user(c, data + i)) |
202 | return -EFAULT; |
203 | if (c == 'V') |
204 | tco_expect_close = 42; |
205 | } |
206 | } |
207 | |
208 | /* someone wrote to us, we should reload the timer */ |
209 | tco_timer_keepalive(); |
210 | } |
211 | return len; |
212 | } |
213 | |
214 | static long nv_tco_ioctl(struct file *file, unsigned int cmd, |
215 | unsigned long arg) |
216 | { |
217 | int new_options, retval = -EINVAL; |
218 | int new_heartbeat; |
219 | void __user *argp = (void __user *)arg; |
220 | int __user *p = argp; |
221 | static const struct watchdog_info ident = { |
222 | .options = WDIOF_SETTIMEOUT | |
223 | WDIOF_KEEPALIVEPING | |
224 | WDIOF_MAGICCLOSE, |
225 | .firmware_version = 0, |
226 | .identity = TCO_MODULE_NAME, |
227 | }; |
228 | |
229 | switch (cmd) { |
230 | case WDIOC_GETSUPPORT: |
231 | return copy_to_user(argp, &ident, sizeof(ident)) ? -EFAULT : 0; |
232 | case WDIOC_GETSTATUS: |
233 | case WDIOC_GETBOOTSTATUS: |
234 | return put_user(0, p); |
235 | case WDIOC_SETOPTIONS: |
236 | if (get_user(new_options, p)) |
237 | return -EFAULT; |
238 | if (new_options & WDIOS_DISABLECARD) { |
239 | tco_timer_stop(); |
240 | retval = 0; |
241 | } |
242 | if (new_options & WDIOS_ENABLECARD) { |
243 | tco_timer_keepalive(); |
244 | tco_timer_start(); |
245 | retval = 0; |
246 | } |
247 | return retval; |
248 | case WDIOC_KEEPALIVE: |
249 | tco_timer_keepalive(); |
250 | return 0; |
251 | case WDIOC_SETTIMEOUT: |
252 | if (get_user(new_heartbeat, p)) |
253 | return -EFAULT; |
254 | if (tco_timer_set_heartbeat(new_heartbeat)) |
255 | return -EINVAL; |
256 | tco_timer_keepalive(); |
257 | /* Fall through */ |
258 | case WDIOC_GETTIMEOUT: |
259 | return put_user(heartbeat, p); |
260 | default: |
261 | return -ENOTTY; |
262 | } |
263 | } |
264 | |
265 | /* |
266 | * Kernel Interfaces |
267 | */ |
268 | |
269 | static const struct file_operations nv_tco_fops = { |
270 | .owner = THIS_MODULE, |
271 | .llseek = no_llseek, |
272 | .write = nv_tco_write, |
273 | .unlocked_ioctl = nv_tco_ioctl, |
274 | .open = nv_tco_open, |
275 | .release = nv_tco_release, |
276 | }; |
277 | |
278 | static struct miscdevice nv_tco_miscdev = { |
279 | .minor = WATCHDOG_MINOR, |
280 | .name = "watchdog", |
281 | .fops = &nv_tco_fops, |
282 | }; |
283 | |
284 | /* |
285 | * Data for PCI driver interface |
286 | * |
287 | * This data only exists for exporting the supported |
288 | * PCI ids via MODULE_DEVICE_TABLE. We do not actually |
289 | * register a pci_driver, because someone else might one day |
290 | * want to register another driver on the same PCI id. |
291 | */ |
292 | static DEFINE_PCI_DEVICE_TABLE(tco_pci_tbl) = { |
293 | { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_SMBUS, |
294 | PCI_ANY_ID, PCI_ANY_ID, }, |
295 | { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_SMBUS, |
296 | PCI_ANY_ID, PCI_ANY_ID, }, |
297 | { 0, }, /* End of list */ |
298 | }; |
299 | MODULE_DEVICE_TABLE(pci, tco_pci_tbl); |
300 | |
301 | /* |
302 | * Init & exit routines |
303 | */ |
304 | |
305 | static unsigned char __devinit nv_tco_getdevice(void) |
306 | { |
307 | struct pci_dev *dev = NULL; |
308 | u32 val; |
309 | |
310 | /* Find the PCI device */ |
311 | for_each_pci_dev(dev) { |
312 | if (pci_match_id(tco_pci_tbl, dev) != NULL) { |
313 | tco_pci = dev; |
314 | break; |
315 | } |
316 | } |
317 | |
318 | if (!tco_pci) |
319 | return 0; |
320 | |
321 | /* Find the base io port */ |
322 | pci_read_config_dword(tco_pci, 0x64, &val); |
323 | val &= 0xffff; |
324 | if (val == 0x0001 || val == 0x0000) { |
325 | /* Something is wrong here, bar isn't setup */ |
326 | pr_err("failed to get tcobase address\n"); |
327 | return 0; |
328 | } |
329 | val &= 0xff00; |
330 | tcobase = val + 0x40; |
331 | |
332 | if (!request_region(tcobase, 0x10, "NV TCO")) { |
333 | pr_err("I/O address 0x%04x already in use\n", tcobase); |
334 | return 0; |
335 | } |
336 | |
337 | /* Set a reasonable heartbeat before we stop the timer */ |
338 | tco_timer_set_heartbeat(30); |
339 | |
340 | /* |
341 | * Stop the TCO before we change anything so we don't race with |
342 | * a zeroed timer. |
343 | */ |
344 | tco_timer_keepalive(); |
345 | tco_timer_stop(); |
346 | |
347 | /* Disable SMI caused by TCO */ |
348 | if (!request_region(MCP51_SMI_EN(tcobase), 4, "NV TCO")) { |
349 | pr_err("I/O address 0x%04x already in use\n", |
350 | MCP51_SMI_EN(tcobase)); |
351 | goto out; |
352 | } |
353 | val = inl(MCP51_SMI_EN(tcobase)); |
354 | val &= ~MCP51_SMI_EN_TCO; |
355 | outl(val, MCP51_SMI_EN(tcobase)); |
356 | val = inl(MCP51_SMI_EN(tcobase)); |
357 | release_region(MCP51_SMI_EN(tcobase), 4); |
358 | if (val & MCP51_SMI_EN_TCO) { |
359 | pr_err("Could not disable SMI caused by TCO\n"); |
360 | goto out; |
361 | } |
362 | |
363 | /* Check chipset's NO_REBOOT bit */ |
364 | pci_read_config_dword(tco_pci, MCP51_SMBUS_SETUP_B, &val); |
365 | val |= MCP51_SMBUS_SETUP_B_TCO_REBOOT; |
366 | pci_write_config_dword(tco_pci, MCP51_SMBUS_SETUP_B, val); |
367 | pci_read_config_dword(tco_pci, MCP51_SMBUS_SETUP_B, &val); |
368 | if (!(val & MCP51_SMBUS_SETUP_B_TCO_REBOOT)) { |
369 | pr_err("failed to reset NO_REBOOT flag, reboot disabled by hardware\n"); |
370 | goto out; |
371 | } |
372 | |
373 | return 1; |
374 | out: |
375 | release_region(tcobase, 0x10); |
376 | return 0; |
377 | } |
378 | |
379 | static int __devinit nv_tco_init(struct platform_device *dev) |
380 | { |
381 | int ret; |
382 | |
383 | /* Check whether or not the hardware watchdog is there */ |
384 | if (!nv_tco_getdevice()) |
385 | return -ENODEV; |
386 | |
387 | /* Check to see if last reboot was due to watchdog timeout */ |
388 | pr_info("Watchdog reboot %sdetected\n", |
389 | inl(TCO_STS(tcobase)) & TCO_STS_TCO2TO_STS ? "" : "not "); |
390 | |
391 | /* Clear out the old status */ |
392 | outl(TCO_STS_RESET, TCO_STS(tcobase)); |
393 | |
394 | /* |
395 | * Check that the heartbeat value is within it's range. |
396 | * If not, reset to the default. |
397 | */ |
398 | if (tco_timer_set_heartbeat(heartbeat)) { |
399 | heartbeat = WATCHDOG_HEARTBEAT; |
400 | tco_timer_set_heartbeat(heartbeat); |
401 | pr_info("heartbeat value must be 2<heartbeat<39, using %d\n", |
402 | heartbeat); |
403 | } |
404 | |
405 | ret = misc_register(&nv_tco_miscdev); |
406 | if (ret != 0) { |
407 | pr_err("cannot register miscdev on minor=%d (err=%d)\n", |
408 | WATCHDOG_MINOR, ret); |
409 | goto unreg_region; |
410 | } |
411 | |
412 | clear_bit(0, &timer_alive); |
413 | |
414 | tco_timer_stop(); |
415 | |
416 | pr_info("initialized (0x%04x). heartbeat=%d sec (nowayout=%d)\n", |
417 | tcobase, heartbeat, nowayout); |
418 | |
419 | return 0; |
420 | |
421 | unreg_region: |
422 | release_region(tcobase, 0x10); |
423 | return ret; |
424 | } |
425 | |
426 | static void __devexit nv_tco_cleanup(void) |
427 | { |
428 | u32 val; |
429 | |
430 | /* Stop the timer before we leave */ |
431 | if (!nowayout) |
432 | tco_timer_stop(); |
433 | |
434 | /* Set the NO_REBOOT bit to prevent later reboots, just for sure */ |
435 | pci_read_config_dword(tco_pci, MCP51_SMBUS_SETUP_B, &val); |
436 | val &= ~MCP51_SMBUS_SETUP_B_TCO_REBOOT; |
437 | pci_write_config_dword(tco_pci, MCP51_SMBUS_SETUP_B, val); |
438 | pci_read_config_dword(tco_pci, MCP51_SMBUS_SETUP_B, &val); |
439 | if (val & MCP51_SMBUS_SETUP_B_TCO_REBOOT) { |
440 | pr_crit("Couldn't unset REBOOT bit. Machine may soon reset\n"); |
441 | } |
442 | |
443 | /* Deregister */ |
444 | misc_deregister(&nv_tco_miscdev); |
445 | release_region(tcobase, 0x10); |
446 | } |
447 | |
448 | static int __devexit nv_tco_remove(struct platform_device *dev) |
449 | { |
450 | if (tcobase) |
451 | nv_tco_cleanup(); |
452 | |
453 | return 0; |
454 | } |
455 | |
456 | static void nv_tco_shutdown(struct platform_device *dev) |
457 | { |
458 | u32 val; |
459 | |
460 | tco_timer_stop(); |
461 | |
462 | /* Some BIOSes fail the POST (once) if the NO_REBOOT flag is not |
463 | * unset during shutdown. */ |
464 | pci_read_config_dword(tco_pci, MCP51_SMBUS_SETUP_B, &val); |
465 | val &= ~MCP51_SMBUS_SETUP_B_TCO_REBOOT; |
466 | pci_write_config_dword(tco_pci, MCP51_SMBUS_SETUP_B, val); |
467 | } |
468 | |
469 | static struct platform_driver nv_tco_driver = { |
470 | .probe = nv_tco_init, |
471 | .remove = __devexit_p(nv_tco_remove), |
472 | .shutdown = nv_tco_shutdown, |
473 | .driver = { |
474 | .owner = THIS_MODULE, |
475 | .name = TCO_MODULE_NAME, |
476 | }, |
477 | }; |
478 | |
479 | static int __init nv_tco_init_module(void) |
480 | { |
481 | int err; |
482 | |
483 | pr_info("NV TCO WatchDog Timer Driver v%s\n", TCO_VERSION); |
484 | |
485 | err = platform_driver_register(&nv_tco_driver); |
486 | if (err) |
487 | return err; |
488 | |
489 | nv_tco_platform_device = platform_device_register_simple( |
490 | TCO_MODULE_NAME, -1, NULL, 0); |
491 | if (IS_ERR(nv_tco_platform_device)) { |
492 | err = PTR_ERR(nv_tco_platform_device); |
493 | goto unreg_platform_driver; |
494 | } |
495 | |
496 | return 0; |
497 | |
498 | unreg_platform_driver: |
499 | platform_driver_unregister(&nv_tco_driver); |
500 | return err; |
501 | } |
502 | |
503 | static void __exit nv_tco_cleanup_module(void) |
504 | { |
505 | platform_device_unregister(nv_tco_platform_device); |
506 | platform_driver_unregister(&nv_tco_driver); |
507 | pr_info("NV TCO Watchdog Module Unloaded\n"); |
508 | } |
509 | |
510 | module_init(nv_tco_init_module); |
511 | module_exit(nv_tco_cleanup_module); |
512 | |
513 | MODULE_AUTHOR("Mike Waychison"); |
514 | MODULE_DESCRIPTION("TCO timer driver for NV chipsets"); |
515 | MODULE_LICENSE("GPL"); |
516 | MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR); |
517 |
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