Root/
1 | #ifndef __SAA7146__ |
2 | #define __SAA7146__ |
3 | |
4 | #include <linux/delay.h> /* for delay-stuff */ |
5 | #include <linux/slab.h> /* for kmalloc/kfree */ |
6 | #include <linux/pci.h> /* for pci-config-stuff, vendor ids etc. */ |
7 | #include <linux/init.h> /* for "__init" */ |
8 | #include <linux/interrupt.h> /* for IMMEDIATE_BH */ |
9 | #include <linux/kmod.h> /* for kernel module loader */ |
10 | #include <linux/i2c.h> /* for i2c subsystem */ |
11 | #include <asm/io.h> /* for accessing devices */ |
12 | #include <linux/stringify.h> |
13 | #include <linux/mutex.h> |
14 | #include <linux/scatterlist.h> |
15 | #include <media/v4l2-device.h> |
16 | #include <media/v4l2-ctrls.h> |
17 | |
18 | #include <linux/vmalloc.h> /* for vmalloc() */ |
19 | #include <linux/mm.h> /* for vmalloc_to_page() */ |
20 | |
21 | #define saa7146_write(sxy,adr,dat) writel((dat),(sxy->mem+(adr))) |
22 | #define saa7146_read(sxy,adr) readl(sxy->mem+(adr)) |
23 | |
24 | extern unsigned int saa7146_debug; |
25 | |
26 | #ifndef DEBUG_VARIABLE |
27 | #define DEBUG_VARIABLE saa7146_debug |
28 | #endif |
29 | |
30 | #define ERR(fmt, ...) pr_err("%s: " fmt, __func__, ##__VA_ARGS__) |
31 | |
32 | #define _DBG(mask, fmt, ...) \ |
33 | do { \ |
34 | if (DEBUG_VARIABLE & mask) \ |
35 | pr_debug("%s(): " fmt, __func__, ##__VA_ARGS__); \ |
36 | } while (0) |
37 | |
38 | /* simple debug messages */ |
39 | #define DEB_S(fmt, ...) _DBG(0x01, fmt, ##__VA_ARGS__) |
40 | /* more detailed debug messages */ |
41 | #define DEB_D(fmt, ...) _DBG(0x02, fmt, ##__VA_ARGS__) |
42 | /* print enter and exit of functions */ |
43 | #define DEB_EE(fmt, ...) _DBG(0x04, fmt, ##__VA_ARGS__) |
44 | /* i2c debug messages */ |
45 | #define DEB_I2C(fmt, ...) _DBG(0x08, fmt, ##__VA_ARGS__) |
46 | /* vbi debug messages */ |
47 | #define DEB_VBI(fmt, ...) _DBG(0x10, fmt, ##__VA_ARGS__) |
48 | /* interrupt debug messages */ |
49 | #define DEB_INT(fmt, ...) _DBG(0x20, fmt, ##__VA_ARGS__) |
50 | /* capture debug messages */ |
51 | #define DEB_CAP(fmt, ...) _DBG(0x40, fmt, ##__VA_ARGS__) |
52 | |
53 | #define SAA7146_ISR_CLEAR(x,y) \ |
54 | saa7146_write(x, ISR, (y)); |
55 | |
56 | struct module; |
57 | |
58 | struct saa7146_dev; |
59 | struct saa7146_extension; |
60 | struct saa7146_vv; |
61 | |
62 | /* saa7146 page table */ |
63 | struct saa7146_pgtable { |
64 | unsigned int size; |
65 | __le32 *cpu; |
66 | dma_addr_t dma; |
67 | /* used for offsets for u,v planes for planar capture modes */ |
68 | unsigned long offset; |
69 | /* used for custom pagetables (used for example by budget dvb cards) */ |
70 | struct scatterlist *slist; |
71 | int nents; |
72 | }; |
73 | |
74 | struct saa7146_pci_extension_data { |
75 | struct saa7146_extension *ext; |
76 | void *ext_priv; /* most likely a name string */ |
77 | }; |
78 | |
79 | #define MAKE_EXTENSION_PCI(x_var, x_vendor, x_device) \ |
80 | { \ |
81 | .vendor = PCI_VENDOR_ID_PHILIPS, \ |
82 | .device = PCI_DEVICE_ID_PHILIPS_SAA7146, \ |
83 | .subvendor = x_vendor, \ |
84 | .subdevice = x_device, \ |
85 | .driver_data = (unsigned long)& x_var, \ |
86 | } |
87 | |
88 | struct saa7146_extension |
89 | { |
90 | char name[32]; /* name of the device */ |
91 | #define SAA7146_USE_I2C_IRQ 0x1 |
92 | #define SAA7146_I2C_SHORT_DELAY 0x2 |
93 | int flags; |
94 | |
95 | /* pairs of subvendor and subdevice ids for |
96 | supported devices, last entry 0xffff, 0xfff */ |
97 | struct module *module; |
98 | struct pci_driver driver; |
99 | struct pci_device_id *pci_tbl; |
100 | |
101 | /* extension functions */ |
102 | int (*probe)(struct saa7146_dev *); |
103 | int (*attach)(struct saa7146_dev *, struct saa7146_pci_extension_data *); |
104 | int (*detach)(struct saa7146_dev*); |
105 | |
106 | u32 irq_mask; /* mask to indicate, which irq-events are handled by the extension */ |
107 | void (*irq_func)(struct saa7146_dev*, u32* irq_mask); |
108 | }; |
109 | |
110 | struct saa7146_dma |
111 | { |
112 | dma_addr_t dma_handle; |
113 | __le32 *cpu_addr; |
114 | }; |
115 | |
116 | struct saa7146_dev |
117 | { |
118 | struct module *module; |
119 | |
120 | struct list_head item; |
121 | |
122 | struct v4l2_device v4l2_dev; |
123 | struct v4l2_ctrl_handler ctrl_handler; |
124 | |
125 | /* different device locks */ |
126 | spinlock_t slock; |
127 | struct mutex v4l2_lock; |
128 | |
129 | unsigned char __iomem *mem; /* pointer to mapped IO memory */ |
130 | u32 revision; /* chip revision; needed for bug-workarounds*/ |
131 | |
132 | /* pci-device & irq stuff*/ |
133 | char name[32]; |
134 | struct pci_dev *pci; |
135 | u32 int_todo; |
136 | spinlock_t int_slock; |
137 | |
138 | /* extension handling */ |
139 | struct saa7146_extension *ext; /* indicates if handled by extension */ |
140 | void *ext_priv; /* pointer for extension private use (most likely some private data) */ |
141 | struct saa7146_ext_vv *ext_vv_data; |
142 | |
143 | /* per device video/vbi informations (if available) */ |
144 | struct saa7146_vv *vv_data; |
145 | void (*vv_callback)(struct saa7146_dev *dev, unsigned long status); |
146 | |
147 | /* i2c-stuff */ |
148 | struct mutex i2c_lock; |
149 | |
150 | u32 i2c_bitrate; |
151 | struct saa7146_dma d_i2c; /* pointer to i2c memory */ |
152 | wait_queue_head_t i2c_wq; |
153 | int i2c_op; |
154 | |
155 | /* memories */ |
156 | struct saa7146_dma d_rps0; |
157 | struct saa7146_dma d_rps1; |
158 | }; |
159 | |
160 | static inline struct saa7146_dev *to_saa7146_dev(struct v4l2_device *v4l2_dev) |
161 | { |
162 | return container_of(v4l2_dev, struct saa7146_dev, v4l2_dev); |
163 | } |
164 | |
165 | /* from saa7146_i2c.c */ |
166 | int saa7146_i2c_adapter_prepare(struct saa7146_dev *dev, struct i2c_adapter *i2c_adapter, u32 bitrate); |
167 | |
168 | /* from saa7146_core.c */ |
169 | extern struct list_head saa7146_devices; |
170 | extern struct mutex saa7146_devices_lock; |
171 | int saa7146_register_extension(struct saa7146_extension*); |
172 | int saa7146_unregister_extension(struct saa7146_extension*); |
173 | struct saa7146_format* saa7146_format_by_fourcc(struct saa7146_dev *dev, int fourcc); |
174 | int saa7146_pgtable_alloc(struct pci_dev *pci, struct saa7146_pgtable *pt); |
175 | void saa7146_pgtable_free(struct pci_dev *pci, struct saa7146_pgtable *pt); |
176 | int saa7146_pgtable_build_single(struct pci_dev *pci, struct saa7146_pgtable *pt, struct scatterlist *list, int length ); |
177 | void *saa7146_vmalloc_build_pgtable(struct pci_dev *pci, long length, struct saa7146_pgtable *pt); |
178 | void saa7146_vfree_destroy_pgtable(struct pci_dev *pci, void *mem, struct saa7146_pgtable *pt); |
179 | void saa7146_setgpio(struct saa7146_dev *dev, int port, u32 data); |
180 | int saa7146_wait_for_debi_done(struct saa7146_dev *dev, int nobusyloop); |
181 | |
182 | /* some memory sizes */ |
183 | #define SAA7146_I2C_MEM ( 1*PAGE_SIZE) |
184 | #define SAA7146_RPS_MEM ( 1*PAGE_SIZE) |
185 | |
186 | /* some i2c constants */ |
187 | #define SAA7146_I2C_TIMEOUT 100 /* i2c-timeout-value in ms */ |
188 | #define SAA7146_I2C_RETRIES 3 /* how many times shall we retry an i2c-operation? */ |
189 | #define SAA7146_I2C_DELAY 5 /* time we wait after certain i2c-operations */ |
190 | |
191 | /* unsorted defines */ |
192 | #define ME1 0x0000000800 |
193 | #define PV1 0x0000000008 |
194 | |
195 | /* gpio defines */ |
196 | #define SAA7146_GPIO_INPUT 0x00 |
197 | #define SAA7146_GPIO_IRQHI 0x10 |
198 | #define SAA7146_GPIO_IRQLO 0x20 |
199 | #define SAA7146_GPIO_IRQHL 0x30 |
200 | #define SAA7146_GPIO_OUTLO 0x40 |
201 | #define SAA7146_GPIO_OUTHI 0x50 |
202 | |
203 | /* debi defines */ |
204 | #define DEBINOSWAP 0x000e0000 |
205 | |
206 | /* define for the register programming sequencer (rps) */ |
207 | #define CMD_NOP 0x00000000 /* No operation */ |
208 | #define CMD_CLR_EVENT 0x00000000 /* Clear event */ |
209 | #define CMD_SET_EVENT 0x10000000 /* Set signal event */ |
210 | #define CMD_PAUSE 0x20000000 /* Pause */ |
211 | #define CMD_CHECK_LATE 0x30000000 /* Check late */ |
212 | #define CMD_UPLOAD 0x40000000 /* Upload */ |
213 | #define CMD_STOP 0x50000000 /* Stop */ |
214 | #define CMD_INTERRUPT 0x60000000 /* Interrupt */ |
215 | #define CMD_JUMP 0x80000000 /* Jump */ |
216 | #define CMD_WR_REG 0x90000000 /* Write (load) register */ |
217 | #define CMD_RD_REG 0xa0000000 /* Read (store) register */ |
218 | #define CMD_WR_REG_MASK 0xc0000000 /* Write register with mask */ |
219 | |
220 | #define CMD_OAN MASK_27 |
221 | #define CMD_INV MASK_26 |
222 | #define CMD_SIG4 MASK_25 |
223 | #define CMD_SIG3 MASK_24 |
224 | #define CMD_SIG2 MASK_23 |
225 | #define CMD_SIG1 MASK_22 |
226 | #define CMD_SIG0 MASK_21 |
227 | #define CMD_O_FID_B MASK_14 |
228 | #define CMD_E_FID_B MASK_13 |
229 | #define CMD_O_FID_A MASK_12 |
230 | #define CMD_E_FID_A MASK_11 |
231 | |
232 | /* some events and command modifiers for rps1 squarewave generator */ |
233 | #define EVT_HS (1<<15) // Source Line Threshold reached |
234 | #define EVT_VBI_B (1<<9) // VSYNC Event |
235 | #define RPS_OAN (1<<27) // 1: OR events, 0: AND events |
236 | #define RPS_INV (1<<26) // Invert (compound) event |
237 | #define GPIO3_MSK 0xFF000000 // GPIO #3 control bits |
238 | |
239 | /* Bit mask constants */ |
240 | #define MASK_00 0x00000001 /* Mask value for bit 0 */ |
241 | #define MASK_01 0x00000002 /* Mask value for bit 1 */ |
242 | #define MASK_02 0x00000004 /* Mask value for bit 2 */ |
243 | #define MASK_03 0x00000008 /* Mask value for bit 3 */ |
244 | #define MASK_04 0x00000010 /* Mask value for bit 4 */ |
245 | #define MASK_05 0x00000020 /* Mask value for bit 5 */ |
246 | #define MASK_06 0x00000040 /* Mask value for bit 6 */ |
247 | #define MASK_07 0x00000080 /* Mask value for bit 7 */ |
248 | #define MASK_08 0x00000100 /* Mask value for bit 8 */ |
249 | #define MASK_09 0x00000200 /* Mask value for bit 9 */ |
250 | #define MASK_10 0x00000400 /* Mask value for bit 10 */ |
251 | #define MASK_11 0x00000800 /* Mask value for bit 11 */ |
252 | #define MASK_12 0x00001000 /* Mask value for bit 12 */ |
253 | #define MASK_13 0x00002000 /* Mask value for bit 13 */ |
254 | #define MASK_14 0x00004000 /* Mask value for bit 14 */ |
255 | #define MASK_15 0x00008000 /* Mask value for bit 15 */ |
256 | #define MASK_16 0x00010000 /* Mask value for bit 16 */ |
257 | #define MASK_17 0x00020000 /* Mask value for bit 17 */ |
258 | #define MASK_18 0x00040000 /* Mask value for bit 18 */ |
259 | #define MASK_19 0x00080000 /* Mask value for bit 19 */ |
260 | #define MASK_20 0x00100000 /* Mask value for bit 20 */ |
261 | #define MASK_21 0x00200000 /* Mask value for bit 21 */ |
262 | #define MASK_22 0x00400000 /* Mask value for bit 22 */ |
263 | #define MASK_23 0x00800000 /* Mask value for bit 23 */ |
264 | #define MASK_24 0x01000000 /* Mask value for bit 24 */ |
265 | #define MASK_25 0x02000000 /* Mask value for bit 25 */ |
266 | #define MASK_26 0x04000000 /* Mask value for bit 26 */ |
267 | #define MASK_27 0x08000000 /* Mask value for bit 27 */ |
268 | #define MASK_28 0x10000000 /* Mask value for bit 28 */ |
269 | #define MASK_29 0x20000000 /* Mask value for bit 29 */ |
270 | #define MASK_30 0x40000000 /* Mask value for bit 30 */ |
271 | #define MASK_31 0x80000000 /* Mask value for bit 31 */ |
272 | |
273 | #define MASK_B0 0x000000ff /* Mask value for byte 0 */ |
274 | #define MASK_B1 0x0000ff00 /* Mask value for byte 1 */ |
275 | #define MASK_B2 0x00ff0000 /* Mask value for byte 2 */ |
276 | #define MASK_B3 0xff000000 /* Mask value for byte 3 */ |
277 | |
278 | #define MASK_W0 0x0000ffff /* Mask value for word 0 */ |
279 | #define MASK_W1 0xffff0000 /* Mask value for word 1 */ |
280 | |
281 | #define MASK_PA 0xfffffffc /* Mask value for physical address */ |
282 | #define MASK_PR 0xfffffffe /* Mask value for protection register */ |
283 | #define MASK_ER 0xffffffff /* Mask value for the entire register */ |
284 | |
285 | #define MASK_NONE 0x00000000 /* No mask */ |
286 | |
287 | /* register aliases */ |
288 | #define BASE_ODD1 0x00 /* Video DMA 1 registers */ |
289 | #define BASE_EVEN1 0x04 |
290 | #define PROT_ADDR1 0x08 |
291 | #define PITCH1 0x0C |
292 | #define BASE_PAGE1 0x10 /* Video DMA 1 base page */ |
293 | #define NUM_LINE_BYTE1 0x14 |
294 | |
295 | #define BASE_ODD2 0x18 /* Video DMA 2 registers */ |
296 | #define BASE_EVEN2 0x1C |
297 | #define PROT_ADDR2 0x20 |
298 | #define PITCH2 0x24 |
299 | #define BASE_PAGE2 0x28 /* Video DMA 2 base page */ |
300 | #define NUM_LINE_BYTE2 0x2C |
301 | |
302 | #define BASE_ODD3 0x30 /* Video DMA 3 registers */ |
303 | #define BASE_EVEN3 0x34 |
304 | #define PROT_ADDR3 0x38 |
305 | #define PITCH3 0x3C |
306 | #define BASE_PAGE3 0x40 /* Video DMA 3 base page */ |
307 | #define NUM_LINE_BYTE3 0x44 |
308 | |
309 | #define PCI_BT_V1 0x48 /* Video/FIFO 1 */ |
310 | #define PCI_BT_V2 0x49 /* Video/FIFO 2 */ |
311 | #define PCI_BT_V3 0x4A /* Video/FIFO 3 */ |
312 | #define PCI_BT_DEBI 0x4B /* DEBI */ |
313 | #define PCI_BT_A 0x4C /* Audio */ |
314 | |
315 | #define DD1_INIT 0x50 /* Init setting of DD1 interface */ |
316 | |
317 | #define DD1_STREAM_B 0x54 /* DD1 B video data stream handling */ |
318 | #define DD1_STREAM_A 0x56 /* DD1 A video data stream handling */ |
319 | |
320 | #define BRS_CTRL 0x58 /* BRS control register */ |
321 | #define HPS_CTRL 0x5C /* HPS control register */ |
322 | #define HPS_V_SCALE 0x60 /* HPS vertical scale */ |
323 | #define HPS_V_GAIN 0x64 /* HPS vertical ACL and gain */ |
324 | #define HPS_H_PRESCALE 0x68 /* HPS horizontal prescale */ |
325 | #define HPS_H_SCALE 0x6C /* HPS horizontal scale */ |
326 | #define BCS_CTRL 0x70 /* BCS control */ |
327 | #define CHROMA_KEY_RANGE 0x74 |
328 | #define CLIP_FORMAT_CTRL 0x78 /* HPS outputs formats & clipping */ |
329 | |
330 | #define DEBI_CONFIG 0x7C |
331 | #define DEBI_COMMAND 0x80 |
332 | #define DEBI_PAGE 0x84 |
333 | #define DEBI_AD 0x88 |
334 | |
335 | #define I2C_TRANSFER 0x8C |
336 | #define I2C_STATUS 0x90 |
337 | |
338 | #define BASE_A1_IN 0x94 /* Audio 1 input DMA */ |
339 | #define PROT_A1_IN 0x98 |
340 | #define PAGE_A1_IN 0x9C |
341 | |
342 | #define BASE_A1_OUT 0xA0 /* Audio 1 output DMA */ |
343 | #define PROT_A1_OUT 0xA4 |
344 | #define PAGE_A1_OUT 0xA8 |
345 | |
346 | #define BASE_A2_IN 0xAC /* Audio 2 input DMA */ |
347 | #define PROT_A2_IN 0xB0 |
348 | #define PAGE_A2_IN 0xB4 |
349 | |
350 | #define BASE_A2_OUT 0xB8 /* Audio 2 output DMA */ |
351 | #define PROT_A2_OUT 0xBC |
352 | #define PAGE_A2_OUT 0xC0 |
353 | |
354 | #define RPS_PAGE0 0xC4 /* RPS task 0 page register */ |
355 | #define RPS_PAGE1 0xC8 /* RPS task 1 page register */ |
356 | |
357 | #define RPS_THRESH0 0xCC /* HBI threshold for task 0 */ |
358 | #define RPS_THRESH1 0xD0 /* HBI threshold for task 1 */ |
359 | |
360 | #define RPS_TOV0 0xD4 /* RPS timeout for task 0 */ |
361 | #define RPS_TOV1 0xD8 /* RPS timeout for task 1 */ |
362 | |
363 | #define IER 0xDC /* Interrupt enable register */ |
364 | |
365 | #define GPIO_CTRL 0xE0 /* GPIO 0-3 register */ |
366 | |
367 | #define EC1SSR 0xE4 /* Event cnt set 1 source select */ |
368 | #define EC2SSR 0xE8 /* Event cnt set 2 source select */ |
369 | #define ECT1R 0xEC /* Event cnt set 1 thresholds */ |
370 | #define ECT2R 0xF0 /* Event cnt set 2 thresholds */ |
371 | |
372 | #define ACON1 0xF4 |
373 | #define ACON2 0xF8 |
374 | |
375 | #define MC1 0xFC /* Main control register 1 */ |
376 | #define MC2 0x100 /* Main control register 2 */ |
377 | |
378 | #define RPS_ADDR0 0x104 /* RPS task 0 address register */ |
379 | #define RPS_ADDR1 0x108 /* RPS task 1 address register */ |
380 | |
381 | #define ISR 0x10C /* Interrupt status register */ |
382 | #define PSR 0x110 /* Primary status register */ |
383 | #define SSR 0x114 /* Secondary status register */ |
384 | |
385 | #define EC1R 0x118 /* Event counter set 1 register */ |
386 | #define EC2R 0x11C /* Event counter set 2 register */ |
387 | |
388 | #define PCI_VDP1 0x120 /* Video DMA pointer of FIFO 1 */ |
389 | #define PCI_VDP2 0x124 /* Video DMA pointer of FIFO 2 */ |
390 | #define PCI_VDP3 0x128 /* Video DMA pointer of FIFO 3 */ |
391 | #define PCI_ADP1 0x12C /* Audio DMA pointer of audio out 1 */ |
392 | #define PCI_ADP2 0x130 /* Audio DMA pointer of audio in 1 */ |
393 | #define PCI_ADP3 0x134 /* Audio DMA pointer of audio out 2 */ |
394 | #define PCI_ADP4 0x138 /* Audio DMA pointer of audio in 2 */ |
395 | #define PCI_DMA_DDP 0x13C /* DEBI DMA pointer */ |
396 | |
397 | #define LEVEL_REP 0x140, |
398 | #define A_TIME_SLOT1 0x180, /* from 180 - 1BC */ |
399 | #define A_TIME_SLOT2 0x1C0, /* from 1C0 - 1FC */ |
400 | |
401 | /* isr masks */ |
402 | #define SPCI_PPEF 0x80000000 /* PCI parity error */ |
403 | #define SPCI_PABO 0x40000000 /* PCI access error (target or master abort) */ |
404 | #define SPCI_PPED 0x20000000 /* PCI parity error on 'real time data' */ |
405 | #define SPCI_RPS_I1 0x10000000 /* Interrupt issued by RPS1 */ |
406 | #define SPCI_RPS_I0 0x08000000 /* Interrupt issued by RPS0 */ |
407 | #define SPCI_RPS_LATE1 0x04000000 /* RPS task 1 is late */ |
408 | #define SPCI_RPS_LATE0 0x02000000 /* RPS task 0 is late */ |
409 | #define SPCI_RPS_E1 0x01000000 /* RPS error from task 1 */ |
410 | #define SPCI_RPS_E0 0x00800000 /* RPS error from task 0 */ |
411 | #define SPCI_RPS_TO1 0x00400000 /* RPS timeout task 1 */ |
412 | #define SPCI_RPS_TO0 0x00200000 /* RPS timeout task 0 */ |
413 | #define SPCI_UPLD 0x00100000 /* RPS in upload */ |
414 | #define SPCI_DEBI_S 0x00080000 /* DEBI status */ |
415 | #define SPCI_DEBI_E 0x00040000 /* DEBI error */ |
416 | #define SPCI_IIC_S 0x00020000 /* I2C status */ |
417 | #define SPCI_IIC_E 0x00010000 /* I2C error */ |
418 | #define SPCI_A2_IN 0x00008000 /* Audio 2 input DMA protection / limit */ |
419 | #define SPCI_A2_OUT 0x00004000 /* Audio 2 output DMA protection / limit */ |
420 | #define SPCI_A1_IN 0x00002000 /* Audio 1 input DMA protection / limit */ |
421 | #define SPCI_A1_OUT 0x00001000 /* Audio 1 output DMA protection / limit */ |
422 | #define SPCI_AFOU 0x00000800 /* Audio FIFO over- / underflow */ |
423 | #define SPCI_V_PE 0x00000400 /* Video protection address */ |
424 | #define SPCI_VFOU 0x00000200 /* Video FIFO over- / underflow */ |
425 | #define SPCI_FIDA 0x00000100 /* Field ID video port A */ |
426 | #define SPCI_FIDB 0x00000080 /* Field ID video port B */ |
427 | #define SPCI_PIN3 0x00000040 /* GPIO pin 3 */ |
428 | #define SPCI_PIN2 0x00000020 /* GPIO pin 2 */ |
429 | #define SPCI_PIN1 0x00000010 /* GPIO pin 1 */ |
430 | #define SPCI_PIN0 0x00000008 /* GPIO pin 0 */ |
431 | #define SPCI_ECS 0x00000004 /* Event counter 1, 2, 4, 5 */ |
432 | #define SPCI_EC3S 0x00000002 /* Event counter 3 */ |
433 | #define SPCI_EC0S 0x00000001 /* Event counter 0 */ |
434 | |
435 | /* i2c */ |
436 | #define SAA7146_I2C_ABORT (1<<7) |
437 | #define SAA7146_I2C_SPERR (1<<6) |
438 | #define SAA7146_I2C_APERR (1<<5) |
439 | #define SAA7146_I2C_DTERR (1<<4) |
440 | #define SAA7146_I2C_DRERR (1<<3) |
441 | #define SAA7146_I2C_AL (1<<2) |
442 | #define SAA7146_I2C_ERR (1<<1) |
443 | #define SAA7146_I2C_BUSY (1<<0) |
444 | |
445 | #define SAA7146_I2C_START (0x3) |
446 | #define SAA7146_I2C_CONT (0x2) |
447 | #define SAA7146_I2C_STOP (0x1) |
448 | #define SAA7146_I2C_NOP (0x0) |
449 | |
450 | #define SAA7146_I2C_BUS_BIT_RATE_6400 (0x500) |
451 | #define SAA7146_I2C_BUS_BIT_RATE_3200 (0x100) |
452 | #define SAA7146_I2C_BUS_BIT_RATE_480 (0x400) |
453 | #define SAA7146_I2C_BUS_BIT_RATE_320 (0x600) |
454 | #define SAA7146_I2C_BUS_BIT_RATE_240 (0x700) |
455 | #define SAA7146_I2C_BUS_BIT_RATE_120 (0x000) |
456 | #define SAA7146_I2C_BUS_BIT_RATE_80 (0x200) |
457 | #define SAA7146_I2C_BUS_BIT_RATE_60 (0x300) |
458 | |
459 | static inline void SAA7146_IER_DISABLE(struct saa7146_dev *x, unsigned y) |
460 | { |
461 | unsigned long flags; |
462 | spin_lock_irqsave(&x->int_slock, flags); |
463 | saa7146_write(x, IER, saa7146_read(x, IER) & ~y); |
464 | spin_unlock_irqrestore(&x->int_slock, flags); |
465 | } |
466 | |
467 | static inline void SAA7146_IER_ENABLE(struct saa7146_dev *x, unsigned y) |
468 | { |
469 | unsigned long flags; |
470 | spin_lock_irqsave(&x->int_slock, flags); |
471 | saa7146_write(x, IER, saa7146_read(x, IER) | y); |
472 | spin_unlock_irqrestore(&x->int_slock, flags); |
473 | } |
474 | |
475 | #endif |
476 |
Branches:
ben-wpan
ben-wpan-stefan
javiroman/ks7010
jz-2.6.34
jz-2.6.34-rc5
jz-2.6.34-rc6
jz-2.6.34-rc7
jz-2.6.35
jz-2.6.36
jz-2.6.37
jz-2.6.38
jz-2.6.39
jz-3.0
jz-3.1
jz-3.11
jz-3.12
jz-3.13
jz-3.15
jz-3.16
jz-3.18-dt
jz-3.2
jz-3.3
jz-3.4
jz-3.5
jz-3.6
jz-3.6-rc2-pwm
jz-3.9
jz-3.9-clk
jz-3.9-rc8
jz47xx
jz47xx-2.6.38
master
Tags:
od-2011-09-04
od-2011-09-18
v2.6.34-rc5
v2.6.34-rc6
v2.6.34-rc7
v3.9