Root/
1 | /* |
2 | * This file is subject to the terms and conditions of the GNU General Public |
3 | * License. See the file "COPYING" in the main directory of this archive |
4 | * for more details. |
5 | * |
6 | * Copyright (C) 2012 Cavium, Inc. |
7 | * Copyright (C) 2009 Wind River Systems, |
8 | * written by Ralf Baechle <ralf@linux-mips.org> |
9 | */ |
10 | #include <linux/module.h> |
11 | #include <linux/init.h> |
12 | #include <linux/slab.h> |
13 | #include <linux/io.h> |
14 | #include <linux/edac.h> |
15 | |
16 | #include <asm/octeon/cvmx.h> |
17 | #include <asm/octeon/cvmx-npi-defs.h> |
18 | #include <asm/octeon/cvmx-pci-defs.h> |
19 | #include <asm/octeon/octeon.h> |
20 | |
21 | #include "edac_core.h" |
22 | #include "edac_module.h" |
23 | |
24 | static void octeon_pci_poll(struct edac_pci_ctl_info *pci) |
25 | { |
26 | union cvmx_pci_cfg01 cfg01; |
27 | |
28 | cfg01.u32 = octeon_npi_read32(CVMX_NPI_PCI_CFG01); |
29 | if (cfg01.s.dpe) { /* Detected parity error */ |
30 | edac_pci_handle_pe(pci, pci->ctl_name); |
31 | cfg01.s.dpe = 1; /* Reset */ |
32 | octeon_npi_write32(CVMX_NPI_PCI_CFG01, cfg01.u32); |
33 | } |
34 | if (cfg01.s.sse) { |
35 | edac_pci_handle_npe(pci, "Signaled System Error"); |
36 | cfg01.s.sse = 1; /* Reset */ |
37 | octeon_npi_write32(CVMX_NPI_PCI_CFG01, cfg01.u32); |
38 | } |
39 | if (cfg01.s.rma) { |
40 | edac_pci_handle_npe(pci, "Received Master Abort"); |
41 | cfg01.s.rma = 1; /* Reset */ |
42 | octeon_npi_write32(CVMX_NPI_PCI_CFG01, cfg01.u32); |
43 | } |
44 | if (cfg01.s.rta) { |
45 | edac_pci_handle_npe(pci, "Received Target Abort"); |
46 | cfg01.s.rta = 1; /* Reset */ |
47 | octeon_npi_write32(CVMX_NPI_PCI_CFG01, cfg01.u32); |
48 | } |
49 | if (cfg01.s.sta) { |
50 | edac_pci_handle_npe(pci, "Signaled Target Abort"); |
51 | cfg01.s.sta = 1; /* Reset */ |
52 | octeon_npi_write32(CVMX_NPI_PCI_CFG01, cfg01.u32); |
53 | } |
54 | if (cfg01.s.mdpe) { |
55 | edac_pci_handle_npe(pci, "Master Data Parity Error"); |
56 | cfg01.s.mdpe = 1; /* Reset */ |
57 | octeon_npi_write32(CVMX_NPI_PCI_CFG01, cfg01.u32); |
58 | } |
59 | } |
60 | |
61 | static int octeon_pci_probe(struct platform_device *pdev) |
62 | { |
63 | struct edac_pci_ctl_info *pci; |
64 | int res = 0; |
65 | |
66 | pci = edac_pci_alloc_ctl_info(0, "octeon_pci_err"); |
67 | if (!pci) |
68 | return -ENOMEM; |
69 | |
70 | pci->dev = &pdev->dev; |
71 | platform_set_drvdata(pdev, pci); |
72 | pci->dev_name = dev_name(&pdev->dev); |
73 | |
74 | pci->mod_name = "octeon-pci"; |
75 | pci->ctl_name = "octeon_pci_err"; |
76 | pci->edac_check = octeon_pci_poll; |
77 | |
78 | if (edac_pci_add_device(pci, 0) > 0) { |
79 | pr_err("%s: edac_pci_add_device() failed\n", __func__); |
80 | goto err; |
81 | } |
82 | |
83 | return 0; |
84 | |
85 | err: |
86 | edac_pci_free_ctl_info(pci); |
87 | |
88 | return res; |
89 | } |
90 | |
91 | static int octeon_pci_remove(struct platform_device *pdev) |
92 | { |
93 | struct edac_pci_ctl_info *pci = platform_get_drvdata(pdev); |
94 | |
95 | edac_pci_del_device(&pdev->dev); |
96 | edac_pci_free_ctl_info(pci); |
97 | |
98 | return 0; |
99 | } |
100 | |
101 | static struct platform_driver octeon_pci_driver = { |
102 | .probe = octeon_pci_probe, |
103 | .remove = octeon_pci_remove, |
104 | .driver = { |
105 | .name = "octeon_pci_edac", |
106 | } |
107 | }; |
108 | module_platform_driver(octeon_pci_driver); |
109 | |
110 | MODULE_LICENSE("GPL"); |
111 | MODULE_AUTHOR("Ralf Baechle <ralf@linux-mips.org>"); |
112 |
Branches:
ben-wpan
ben-wpan-stefan
javiroman/ks7010
jz-2.6.34
jz-2.6.34-rc5
jz-2.6.34-rc6
jz-2.6.34-rc7
jz-2.6.35
jz-2.6.36
jz-2.6.37
jz-2.6.38
jz-2.6.39
jz-3.0
jz-3.1
jz-3.11
jz-3.12
jz-3.13
jz-3.15
jz-3.16
jz-3.18-dt
jz-3.2
jz-3.3
jz-3.4
jz-3.5
jz-3.6
jz-3.6-rc2-pwm
jz-3.9
jz-3.9-clk
jz-3.9-rc8
jz47xx
jz47xx-2.6.38
master
Tags:
od-2011-09-04
od-2011-09-18
v2.6.34-rc5
v2.6.34-rc6
v2.6.34-rc7
v3.9