Root/Documentation/memory-barriers.txt

1             ============================
2             LINUX KERNEL MEMORY BARRIERS
3             ============================
4
5By: David Howells <dhowells@redhat.com>
6    Paul E. McKenney <paulmck@linux.vnet.ibm.com>
7
8Contents:
9
10 (*) Abstract memory access model.
11
12     - Device operations.
13     - Guarantees.
14
15 (*) What are memory barriers?
16
17     - Varieties of memory barrier.
18     - What may not be assumed about memory barriers?
19     - Data dependency barriers.
20     - Control dependencies.
21     - SMP barrier pairing.
22     - Examples of memory barrier sequences.
23     - Read memory barriers vs load speculation.
24     - Transitivity
25
26 (*) Explicit kernel barriers.
27
28     - Compiler barrier.
29     - CPU memory barriers.
30     - MMIO write barrier.
31
32 (*) Implicit kernel memory barriers.
33
34     - Locking functions.
35     - Interrupt disabling functions.
36     - Sleep and wake-up functions.
37     - Miscellaneous functions.
38
39 (*) Inter-CPU locking barrier effects.
40
41     - Locks vs memory accesses.
42     - Locks vs I/O accesses.
43
44 (*) Where are memory barriers needed?
45
46     - Interprocessor interaction.
47     - Atomic operations.
48     - Accessing devices.
49     - Interrupts.
50
51 (*) Kernel I/O barrier effects.
52
53 (*) Assumed minimum execution ordering model.
54
55 (*) The effects of the cpu cache.
56
57     - Cache coherency.
58     - Cache coherency vs DMA.
59     - Cache coherency vs MMIO.
60
61 (*) The things CPUs get up to.
62
63     - And then there's the Alpha.
64
65 (*) Example uses.
66
67     - Circular buffers.
68
69 (*) References.
70
71
72============================
73ABSTRACT MEMORY ACCESS MODEL
74============================
75
76Consider the following abstract model of the system:
77
78                    : :
79                    : :
80                    : :
81        +-------+ : +--------+ : +-------+
82        | | : | | : | |
83        | | : | | : | |
84        | CPU 1 |<----->| Memory |<----->| CPU 2 |
85        | | : | | : | |
86        | | : | | : | |
87        +-------+ : +--------+ : +-------+
88            ^ : ^ : ^
89            | : | : |
90            | : | : |
91            | : v : |
92            | : +--------+ : |
93            | : | | : |
94            | : | | : |
95            +---------->| Device |<----------+
96                    : | | :
97                    : | | :
98                    : +--------+ :
99                    : :
100
101Each CPU executes a program that generates memory access operations. In the
102abstract CPU, memory operation ordering is very relaxed, and a CPU may actually
103perform the memory operations in any order it likes, provided program causality
104appears to be maintained. Similarly, the compiler may also arrange the
105instructions it emits in any order it likes, provided it doesn't affect the
106apparent operation of the program.
107
108So in the above diagram, the effects of the memory operations performed by a
109CPU are perceived by the rest of the system as the operations cross the
110interface between the CPU and rest of the system (the dotted lines).
111
112
113For example, consider the following sequence of events:
114
115    CPU 1 CPU 2
116    =============== ===============
117    { A == 1; B == 2 }
118    A = 3; x = A;
119    B = 4; y = B;
120
121The set of accesses as seen by the memory system in the middle can be arranged
122in 24 different combinations:
123
124    STORE A=3, STORE B=4, x=LOAD A->3, y=LOAD B->4
125    STORE A=3, STORE B=4, y=LOAD B->4, x=LOAD A->3
126    STORE A=3, x=LOAD A->3, STORE B=4, y=LOAD B->4
127    STORE A=3, x=LOAD A->3, y=LOAD B->2, STORE B=4
128    STORE A=3, y=LOAD B->2, STORE B=4, x=LOAD A->3
129    STORE A=3, y=LOAD B->2, x=LOAD A->3, STORE B=4
130    STORE B=4, STORE A=3, x=LOAD A->3, y=LOAD B->4
131    STORE B=4, ...
132    ...
133
134and can thus result in four different combinations of values:
135
136    x == 1, y == 2
137    x == 1, y == 4
138    x == 3, y == 2
139    x == 3, y == 4
140
141
142Furthermore, the stores committed by a CPU to the memory system may not be
143perceived by the loads made by another CPU in the same order as the stores were
144committed.
145
146
147As a further example, consider this sequence of events:
148
149    CPU 1 CPU 2
150    =============== ===============
151    { A == 1, B == 2, C = 3, P == &A, Q == &C }
152    B = 4; Q = P;
153    P = &B D = *Q;
154
155There is an obvious data dependency here, as the value loaded into D depends on
156the address retrieved from P by CPU 2. At the end of the sequence, any of the
157following results are possible:
158
159    (Q == &A) and (D == 1)
160    (Q == &B) and (D == 2)
161    (Q == &B) and (D == 4)
162
163Note that CPU 2 will never try and load C into D because the CPU will load P
164into Q before issuing the load of *Q.
165
166
167DEVICE OPERATIONS
168-----------------
169
170Some devices present their control interfaces as collections of memory
171locations, but the order in which the control registers are accessed is very
172important. For instance, imagine an ethernet card with a set of internal
173registers that are accessed through an address port register (A) and a data
174port register (D). To read internal register 5, the following code might then
175be used:
176
177    *A = 5;
178    x = *D;
179
180but this might show up as either of the following two sequences:
181
182    STORE *A = 5, x = LOAD *D
183    x = LOAD *D, STORE *A = 5
184
185the second of which will almost certainly result in a malfunction, since it set
186the address _after_ attempting to read the register.
187
188
189GUARANTEES
190----------
191
192There are some minimal guarantees that may be expected of a CPU:
193
194 (*) On any given CPU, dependent memory accesses will be issued in order, with
195     respect to itself. This means that for:
196
197    Q = P; D = *Q;
198
199     the CPU will issue the following memory operations:
200
201    Q = LOAD P, D = LOAD *Q
202
203     and always in that order.
204
205 (*) Overlapping loads and stores within a particular CPU will appear to be
206     ordered within that CPU. This means that for:
207
208    a = *X; *X = b;
209
210     the CPU will only issue the following sequence of memory operations:
211
212    a = LOAD *X, STORE *X = b
213
214     And for:
215
216    *X = c; d = *X;
217
218     the CPU will only issue:
219
220    STORE *X = c, d = LOAD *X
221
222     (Loads and stores overlap if they are targeted at overlapping pieces of
223     memory).
224
225And there are a number of things that _must_ or _must_not_ be assumed:
226
227 (*) It _must_not_ be assumed that independent loads and stores will be issued
228     in the order given. This means that for:
229
230    X = *A; Y = *B; *D = Z;
231
232     we may get any of the following sequences:
233
234    X = LOAD *A, Y = LOAD *B, STORE *D = Z
235    X = LOAD *A, STORE *D = Z, Y = LOAD *B
236    Y = LOAD *B, X = LOAD *A, STORE *D = Z
237    Y = LOAD *B, STORE *D = Z, X = LOAD *A
238    STORE *D = Z, X = LOAD *A, Y = LOAD *B
239    STORE *D = Z, Y = LOAD *B, X = LOAD *A
240
241 (*) It _must_ be assumed that overlapping memory accesses may be merged or
242     discarded. This means that for:
243
244    X = *A; Y = *(A + 4);
245
246     we may get any one of the following sequences:
247
248    X = LOAD *A; Y = LOAD *(A + 4);
249    Y = LOAD *(A + 4); X = LOAD *A;
250    {X, Y} = LOAD {*A, *(A + 4) };
251
252     And for:
253
254    *A = X; *(A + 4) = Y;
255
256     we may get any of:
257
258    STORE *A = X; STORE *(A + 4) = Y;
259    STORE *(A + 4) = Y; STORE *A = X;
260    STORE {*A, *(A + 4) } = {X, Y};
261
262
263=========================
264WHAT ARE MEMORY BARRIERS?
265=========================
266
267As can be seen above, independent memory operations are effectively performed
268in random order, but this can be a problem for CPU-CPU interaction and for I/O.
269What is required is some way of intervening to instruct the compiler and the
270CPU to restrict the order.
271
272Memory barriers are such interventions. They impose a perceived partial
273ordering over the memory operations on either side of the barrier.
274
275Such enforcement is important because the CPUs and other devices in a system
276can use a variety of tricks to improve performance, including reordering,
277deferral and combination of memory operations; speculative loads; speculative
278branch prediction and various types of caching. Memory barriers are used to
279override or suppress these tricks, allowing the code to sanely control the
280interaction of multiple CPUs and/or devices.
281
282
283VARIETIES OF MEMORY BARRIER
284---------------------------
285
286Memory barriers come in four basic varieties:
287
288 (1) Write (or store) memory barriers.
289
290     A write memory barrier gives a guarantee that all the STORE operations
291     specified before the barrier will appear to happen before all the STORE
292     operations specified after the barrier with respect to the other
293     components of the system.
294
295     A write barrier is a partial ordering on stores only; it is not required
296     to have any effect on loads.
297
298     A CPU can be viewed as committing a sequence of store operations to the
299     memory system as time progresses. All stores before a write barrier will
300     occur in the sequence _before_ all the stores after the write barrier.
301
302     [!] Note that write barriers should normally be paired with read or data
303     dependency barriers; see the "SMP barrier pairing" subsection.
304
305
306 (2) Data dependency barriers.
307
308     A data dependency barrier is a weaker form of read barrier. In the case
309     where two loads are performed such that the second depends on the result
310     of the first (eg: the first load retrieves the address to which the second
311     load will be directed), a data dependency barrier would be required to
312     make sure that the target of the second load is updated before the address
313     obtained by the first load is accessed.
314
315     A data dependency barrier is a partial ordering on interdependent loads
316     only; it is not required to have any effect on stores, independent loads
317     or overlapping loads.
318
319     As mentioned in (1), the other CPUs in the system can be viewed as
320     committing sequences of stores to the memory system that the CPU being
321     considered can then perceive. A data dependency barrier issued by the CPU
322     under consideration guarantees that for any load preceding it, if that
323     load touches one of a sequence of stores from another CPU, then by the
324     time the barrier completes, the effects of all the stores prior to that
325     touched by the load will be perceptible to any loads issued after the data
326     dependency barrier.
327
328     See the "Examples of memory barrier sequences" subsection for diagrams
329     showing the ordering constraints.
330
331     [!] Note that the first load really has to have a _data_ dependency and
332     not a control dependency. If the address for the second load is dependent
333     on the first load, but the dependency is through a conditional rather than
334     actually loading the address itself, then it's a _control_ dependency and
335     a full read barrier or better is required. See the "Control dependencies"
336     subsection for more information.
337
338     [!] Note that data dependency barriers should normally be paired with
339     write barriers; see the "SMP barrier pairing" subsection.
340
341
342 (3) Read (or load) memory barriers.
343
344     A read barrier is a data dependency barrier plus a guarantee that all the
345     LOAD operations specified before the barrier will appear to happen before
346     all the LOAD operations specified after the barrier with respect to the
347     other components of the system.
348
349     A read barrier is a partial ordering on loads only; it is not required to
350     have any effect on stores.
351
352     Read memory barriers imply data dependency barriers, and so can substitute
353     for them.
354
355     [!] Note that read barriers should normally be paired with write barriers;
356     see the "SMP barrier pairing" subsection.
357
358
359 (4) General memory barriers.
360
361     A general memory barrier gives a guarantee that all the LOAD and STORE
362     operations specified before the barrier will appear to happen before all
363     the LOAD and STORE operations specified after the barrier with respect to
364     the other components of the system.
365
366     A general memory barrier is a partial ordering over both loads and stores.
367
368     General memory barriers imply both read and write memory barriers, and so
369     can substitute for either.
370
371
372And a couple of implicit varieties:
373
374 (5) LOCK operations.
375
376     This acts as a one-way permeable barrier. It guarantees that all memory
377     operations after the LOCK operation will appear to happen after the LOCK
378     operation with respect to the other components of the system.
379
380     Memory operations that occur before a LOCK operation may appear to happen
381     after it completes.
382
383     A LOCK operation should almost always be paired with an UNLOCK operation.
384
385
386 (6) UNLOCK operations.
387
388     This also acts as a one-way permeable barrier. It guarantees that all
389     memory operations before the UNLOCK operation will appear to happen before
390     the UNLOCK operation with respect to the other components of the system.
391
392     Memory operations that occur after an UNLOCK operation may appear to
393     happen before it completes.
394
395     LOCK and UNLOCK operations are guaranteed to appear with respect to each
396     other strictly in the order specified.
397
398     The use of LOCK and UNLOCK operations generally precludes the need for
399     other sorts of memory barrier (but note the exceptions mentioned in the
400     subsection "MMIO write barrier").
401
402
403Memory barriers are only required where there's a possibility of interaction
404between two CPUs or between a CPU and a device. If it can be guaranteed that
405there won't be any such interaction in any particular piece of code, then
406memory barriers are unnecessary in that piece of code.
407
408
409Note that these are the _minimum_ guarantees. Different architectures may give
410more substantial guarantees, but they may _not_ be relied upon outside of arch
411specific code.
412
413
414WHAT MAY NOT BE ASSUMED ABOUT MEMORY BARRIERS?
415----------------------------------------------
416
417There are certain things that the Linux kernel memory barriers do not guarantee:
418
419 (*) There is no guarantee that any of the memory accesses specified before a
420     memory barrier will be _complete_ by the completion of a memory barrier
421     instruction; the barrier can be considered to draw a line in that CPU's
422     access queue that accesses of the appropriate type may not cross.
423
424 (*) There is no guarantee that issuing a memory barrier on one CPU will have
425     any direct effect on another CPU or any other hardware in the system. The
426     indirect effect will be the order in which the second CPU sees the effects
427     of the first CPU's accesses occur, but see the next point:
428
429 (*) There is no guarantee that a CPU will see the correct order of effects
430     from a second CPU's accesses, even _if_ the second CPU uses a memory
431     barrier, unless the first CPU _also_ uses a matching memory barrier (see
432     the subsection on "SMP Barrier Pairing").
433
434 (*) There is no guarantee that some intervening piece of off-the-CPU
435     hardware[*] will not reorder the memory accesses. CPU cache coherency
436     mechanisms should propagate the indirect effects of a memory barrier
437     between CPUs, but might not do so in order.
438
439    [*] For information on bus mastering DMA and coherency please read:
440
441        Documentation/PCI/pci.txt
442        Documentation/DMA-API-HOWTO.txt
443        Documentation/DMA-API.txt
444
445
446DATA DEPENDENCY BARRIERS
447------------------------
448
449The usage requirements of data dependency barriers are a little subtle, and
450it's not always obvious that they're needed. To illustrate, consider the
451following sequence of events:
452
453    CPU 1 CPU 2
454    =============== ===============
455    { A == 1, B == 2, C = 3, P == &A, Q == &C }
456    B = 4;
457    <write barrier>
458    P = &B
459            Q = P;
460            D = *Q;
461
462There's a clear data dependency here, and it would seem that by the end of the
463sequence, Q must be either &A or &B, and that:
464
465    (Q == &A) implies (D == 1)
466    (Q == &B) implies (D == 4)
467
468But! CPU 2's perception of P may be updated _before_ its perception of B, thus
469leading to the following situation:
470
471    (Q == &B) and (D == 2) ????
472
473Whilst this may seem like a failure of coherency or causality maintenance, it
474isn't, and this behaviour can be observed on certain real CPUs (such as the DEC
475Alpha).
476
477To deal with this, a data dependency barrier or better must be inserted
478between the address load and the data load:
479
480    CPU 1 CPU 2
481    =============== ===============
482    { A == 1, B == 2, C = 3, P == &A, Q == &C }
483    B = 4;
484    <write barrier>
485    P = &B
486            Q = P;
487            <data dependency barrier>
488            D = *Q;
489
490This enforces the occurrence of one of the two implications, and prevents the
491third possibility from arising.
492
493[!] Note that this extremely counterintuitive situation arises most easily on
494machines with split caches, so that, for example, one cache bank processes
495even-numbered cache lines and the other bank processes odd-numbered cache
496lines. The pointer P might be stored in an odd-numbered cache line, and the
497variable B might be stored in an even-numbered cache line. Then, if the
498even-numbered bank of the reading CPU's cache is extremely busy while the
499odd-numbered bank is idle, one can see the new value of the pointer P (&B),
500but the old value of the variable B (2).
501
502
503Another example of where data dependency barriers might by required is where a
504number is read from memory and then used to calculate the index for an array
505access:
506
507    CPU 1 CPU 2
508    =============== ===============
509    { M[0] == 1, M[1] == 2, M[3] = 3, P == 0, Q == 3 }
510    M[1] = 4;
511    <write barrier>
512    P = 1
513            Q = P;
514            <data dependency barrier>
515            D = M[Q];
516
517
518The data dependency barrier is very important to the RCU system, for example.
519See rcu_dereference() in include/linux/rcupdate.h. This permits the current
520target of an RCU'd pointer to be replaced with a new modified target, without
521the replacement target appearing to be incompletely initialised.
522
523See also the subsection on "Cache Coherency" for a more thorough example.
524
525
526CONTROL DEPENDENCIES
527--------------------
528
529A control dependency requires a full read memory barrier, not simply a data
530dependency barrier to make it work correctly. Consider the following bit of
531code:
532
533    q = &a;
534    if (p)
535        q = &b;
536    <data dependency barrier>
537    x = *q;
538
539This will not have the desired effect because there is no actual data
540dependency, but rather a control dependency that the CPU may short-circuit by
541attempting to predict the outcome in advance. In such a case what's actually
542required is:
543
544    q = &a;
545    if (p)
546        q = &b;
547    <read barrier>
548    x = *q;
549
550
551SMP BARRIER PAIRING
552-------------------
553
554When dealing with CPU-CPU interactions, certain types of memory barrier should
555always be paired. A lack of appropriate pairing is almost certainly an error.
556
557A write barrier should always be paired with a data dependency barrier or read
558barrier, though a general barrier would also be viable. Similarly a read
559barrier or a data dependency barrier should always be paired with at least an
560write barrier, though, again, a general barrier is viable:
561
562    CPU 1 CPU 2
563    =============== ===============
564    a = 1;
565    <write barrier>
566    b = 2; x = b;
567            <read barrier>
568            y = a;
569
570Or:
571
572    CPU 1 CPU 2
573    =============== ===============================
574    a = 1;
575    <write barrier>
576    b = &a; x = b;
577            <data dependency barrier>
578            y = *x;
579
580Basically, the read barrier always has to be there, even though it can be of
581the "weaker" type.
582
583[!] Note that the stores before the write barrier would normally be expected to
584match the loads after the read barrier or the data dependency barrier, and vice
585versa:
586
587    CPU 1 CPU 2
588    =============== ===============
589    a = 1; }---- --->{ v = c
590    b = 2; } \ / { w = d
591    <write barrier> \ <read barrier>
592    c = 3; } / \ { x = a;
593    d = 4; }---- --->{ y = b;
594
595
596EXAMPLES OF MEMORY BARRIER SEQUENCES
597------------------------------------
598
599Firstly, write barriers act as partial orderings on store operations.
600Consider the following sequence of events:
601
602    CPU 1
603    =======================
604    STORE A = 1
605    STORE B = 2
606    STORE C = 3
607    <write barrier>
608    STORE D = 4
609    STORE E = 5
610
611This sequence of events is committed to the memory coherence system in an order
612that the rest of the system might perceive as the unordered set of { STORE A,
613STORE B, STORE C } all occurring before the unordered set of { STORE D, STORE E
614}:
615
616    +-------+ : :
617    | | +------+
618    | |------>| C=3 | } /\
619    | | : +------+ }----- \ -----> Events perceptible to
620    | | : | A=1 | } \/ the rest of the system
621    | | : +------+ }
622    | CPU 1 | : | B=2 | }
623    | | +------+ }
624    | | wwwwwwwwwwwwwwww } <--- At this point the write barrier
625    | | +------+ } requires all stores prior to the
626    | | : | E=5 | } barrier to be committed before
627    | | : +------+ } further stores may take place
628    | |------>| D=4 | }
629    | | +------+
630    +-------+ : :
631                       |
632                       | Sequence in which stores are committed to the
633                       | memory system by CPU 1
634                       V
635
636
637Secondly, data dependency barriers act as partial orderings on data-dependent
638loads. Consider the following sequence of events:
639
640    CPU 1 CPU 2
641    ======================= =======================
642        { B = 7; X = 9; Y = 8; C = &Y }
643    STORE A = 1
644    STORE B = 2
645    <write barrier>
646    STORE C = &B LOAD X
647    STORE D = 4 LOAD C (gets &B)
648                LOAD *C (reads B)
649
650Without intervention, CPU 2 may perceive the events on CPU 1 in some
651effectively random order, despite the write barrier issued by CPU 1:
652
653    +-------+ : : : :
654    | | +------+ +-------+ | Sequence of update
655    | |------>| B=2 |----- --->| Y->8 | | of perception on
656    | | : +------+ \ +-------+ | CPU 2
657    | CPU 1 | : | A=1 | \ --->| C->&Y | V
658    | | +------+ | +-------+
659    | | wwwwwwwwwwwwwwww | : :
660    | | +------+ | : :
661    | | : | C=&B |--- | : : +-------+
662    | | : +------+ \ | +-------+ | |
663    | |------>| D=4 | ----------->| C->&B |------>| |
664    | | +------+ | +-------+ | |
665    +-------+ : : | : : | |
666                                   | : : | |
667                                   | : : | CPU 2 |
668                                   | +-------+ | |
669        Apparently incorrect ---> | | B->7 |------>| |
670        perception of B (!) | +-------+ | |
671                                   | : : | |
672                                   | +-------+ | |
673        The load of X holds ---> \ | X->9 |------>| |
674        up the maintenance \ +-------+ | |
675        of coherence of B ----->| B->2 | +-------+
676                                            +-------+
677                                            : :
678
679
680In the above example, CPU 2 perceives that B is 7, despite the load of *C
681(which would be B) coming after the LOAD of C.
682
683If, however, a data dependency barrier were to be placed between the load of C
684and the load of *C (ie: B) on CPU 2:
685
686    CPU 1 CPU 2
687    ======================= =======================
688        { B = 7; X = 9; Y = 8; C = &Y }
689    STORE A = 1
690    STORE B = 2
691    <write barrier>
692    STORE C = &B LOAD X
693    STORE D = 4 LOAD C (gets &B)
694                <data dependency barrier>
695                LOAD *C (reads B)
696
697then the following will occur:
698
699    +-------+ : : : :
700    | | +------+ +-------+
701    | |------>| B=2 |----- --->| Y->8 |
702    | | : +------+ \ +-------+
703    | CPU 1 | : | A=1 | \ --->| C->&Y |
704    | | +------+ | +-------+
705    | | wwwwwwwwwwwwwwww | : :
706    | | +------+ | : :
707    | | : | C=&B |--- | : : +-------+
708    | | : +------+ \ | +-------+ | |
709    | |------>| D=4 | ----------->| C->&B |------>| |
710    | | +------+ | +-------+ | |
711    +-------+ : : | : : | |
712                                   | : : | |
713                                   | : : | CPU 2 |
714                                   | +-------+ | |
715                                   | | X->9 |------>| |
716                                   | +-------+ | |
717      Makes sure all effects ---> \ ddddddddddddddddd | |
718      prior to the store of C \ +-------+ | |
719      are perceptible to ----->| B->2 |------>| |
720      subsequent loads +-------+ | |
721                                            : : +-------+
722
723
724And thirdly, a read barrier acts as a partial order on loads. Consider the
725following sequence of events:
726
727    CPU 1 CPU 2
728    ======================= =======================
729        { A = 0, B = 9 }
730    STORE A=1
731    <write barrier>
732    STORE B=2
733                LOAD B
734                LOAD A
735
736Without intervention, CPU 2 may then choose to perceive the events on CPU 1 in
737some effectively random order, despite the write barrier issued by CPU 1:
738
739    +-------+ : : : :
740    | | +------+ +-------+
741    | |------>| A=1 |------ --->| A->0 |
742    | | +------+ \ +-------+
743    | CPU 1 | wwwwwwwwwwwwwwww \ --->| B->9 |
744    | | +------+ | +-------+
745    | |------>| B=2 |--- | : :
746    | | +------+ \ | : : +-------+
747    +-------+ : : \ | +-------+ | |
748                                 ---------->| B->2 |------>| |
749                                    | +-------+ | CPU 2 |
750                                    | | A->0 |------>| |
751                                    | +-------+ | |
752                                    | : : +-------+
753                                     \ : :
754                                      \ +-------+
755                                       ---->| A->1 |
756                                            +-------+
757                                            : :
758
759
760If, however, a read barrier were to be placed between the load of B and the
761load of A on CPU 2:
762
763    CPU 1 CPU 2
764    ======================= =======================
765        { A = 0, B = 9 }
766    STORE A=1
767    <write barrier>
768    STORE B=2
769                LOAD B
770                <read barrier>
771                LOAD A
772
773then the partial ordering imposed by CPU 1 will be perceived correctly by CPU
7742:
775
776    +-------+ : : : :
777    | | +------+ +-------+
778    | |------>| A=1 |------ --->| A->0 |
779    | | +------+ \ +-------+
780    | CPU 1 | wwwwwwwwwwwwwwww \ --->| B->9 |
781    | | +------+ | +-------+
782    | |------>| B=2 |--- | : :
783    | | +------+ \ | : : +-------+
784    +-------+ : : \ | +-------+ | |
785                                 ---------->| B->2 |------>| |
786                                    | +-------+ | CPU 2 |
787                                    | : : | |
788                                    | : : | |
789      At this point the read ----> \ rrrrrrrrrrrrrrrrr | |
790      barrier causes all effects \ +-------+ | |
791      prior to the storage of B ---->| A->1 |------>| |
792      to be perceptible to CPU 2 +-------+ | |
793                                            : : +-------+
794
795
796To illustrate this more completely, consider what could happen if the code
797contained a load of A either side of the read barrier:
798
799    CPU 1 CPU 2
800    ======================= =======================
801        { A = 0, B = 9 }
802    STORE A=1
803    <write barrier>
804    STORE B=2
805                LOAD B
806                LOAD A [first load of A]
807                <read barrier>
808                LOAD A [second load of A]
809
810Even though the two loads of A both occur after the load of B, they may both
811come up with different values:
812
813    +-------+ : : : :
814    | | +------+ +-------+
815    | |------>| A=1 |------ --->| A->0 |
816    | | +------+ \ +-------+
817    | CPU 1 | wwwwwwwwwwwwwwww \ --->| B->9 |
818    | | +------+ | +-------+
819    | |------>| B=2 |--- | : :
820    | | +------+ \ | : : +-------+
821    +-------+ : : \ | +-------+ | |
822                                 ---------->| B->2 |------>| |
823                                    | +-------+ | CPU 2 |
824                                    | : : | |
825                                    | : : | |
826                                    | +-------+ | |
827                                    | | A->0 |------>| 1st |
828                                    | +-------+ | |
829      At this point the read ----> \ rrrrrrrrrrrrrrrrr | |
830      barrier causes all effects \ +-------+ | |
831      prior to the storage of B ---->| A->1 |------>| 2nd |
832      to be perceptible to CPU 2 +-------+ | |
833                                            : : +-------+
834
835
836But it may be that the update to A from CPU 1 becomes perceptible to CPU 2
837before the read barrier completes anyway:
838
839    +-------+ : : : :
840    | | +------+ +-------+
841    | |------>| A=1 |------ --->| A->0 |
842    | | +------+ \ +-------+
843    | CPU 1 | wwwwwwwwwwwwwwww \ --->| B->9 |
844    | | +------+ | +-------+
845    | |------>| B=2 |--- | : :
846    | | +------+ \ | : : +-------+
847    +-------+ : : \ | +-------+ | |
848                                 ---------->| B->2 |------>| |
849                                    | +-------+ | CPU 2 |
850                                    | : : | |
851                                     \ : : | |
852                                      \ +-------+ | |
853                                       ---->| A->1 |------>| 1st |
854                                            +-------+ | |
855                                        rrrrrrrrrrrrrrrrr | |
856                                            +-------+ | |
857                                            | A->1 |------>| 2nd |
858                                            +-------+ | |
859                                            : : +-------+
860
861
862The guarantee is that the second load will always come up with A == 1 if the
863load of B came up with B == 2. No such guarantee exists for the first load of
864A; that may come up with either A == 0 or A == 1.
865
866
867READ MEMORY BARRIERS VS LOAD SPECULATION
868----------------------------------------
869
870Many CPUs speculate with loads: that is they see that they will need to load an
871item from memory, and they find a time where they're not using the bus for any
872other loads, and so do the load in advance - even though they haven't actually
873got to that point in the instruction execution flow yet. This permits the
874actual load instruction to potentially complete immediately because the CPU
875already has the value to hand.
876
877It may turn out that the CPU didn't actually need the value - perhaps because a
878branch circumvented the load - in which case it can discard the value or just
879cache it for later use.
880
881Consider:
882
883    CPU 1 CPU 2
884    ======================= =======================
885                    LOAD B
886                    DIVIDE } Divide instructions generally
887                    DIVIDE } take a long time to perform
888                    LOAD A
889
890Which might appear as this:
891
892                                            : : +-------+
893                                            +-------+ | |
894                                        --->| B->2 |------>| |
895                                            +-------+ | CPU 2 |
896                                            : :DIVIDE | |
897                                            +-------+ | |
898    The CPU being busy doing a ---> --->| A->0 |~~~~ | |
899    division speculates on the +-------+ ~ | |
900    LOAD of A : : ~ | |
901                                            : :DIVIDE | |
902                                            : : ~ | |
903    Once the divisions are complete --> : : ~-->| |
904    the CPU can then perform the : : | |
905    LOAD with immediate effect : : +-------+
906
907
908Placing a read barrier or a data dependency barrier just before the second
909load:
910
911    CPU 1 CPU 2
912    ======================= =======================
913                    LOAD B
914                    DIVIDE
915                    DIVIDE
916                <read barrier>
917                    LOAD A
918
919will force any value speculatively obtained to be reconsidered to an extent
920dependent on the type of barrier used. If there was no change made to the
921speculated memory location, then the speculated value will just be used:
922
923                                            : : +-------+
924                                            +-------+ | |
925                                        --->| B->2 |------>| |
926                                            +-------+ | CPU 2 |
927                                            : :DIVIDE | |
928                                            +-------+ | |
929    The CPU being busy doing a ---> --->| A->0 |~~~~ | |
930    division speculates on the +-------+ ~ | |
931    LOAD of A : : ~ | |
932                                            : :DIVIDE | |
933                                            : : ~ | |
934                                            : : ~ | |
935                                        rrrrrrrrrrrrrrrr~ | |
936                                            : : ~ | |
937                                            : : ~-->| |
938                                            : : | |
939                                            : : +-------+
940
941
942but if there was an update or an invalidation from another CPU pending, then
943the speculation will be cancelled and the value reloaded:
944
945                                            : : +-------+
946                                            +-------+ | |
947                                        --->| B->2 |------>| |
948                                            +-------+ | CPU 2 |
949                                            : :DIVIDE | |
950                                            +-------+ | |
951    The CPU being busy doing a ---> --->| A->0 |~~~~ | |
952    division speculates on the +-------+ ~ | |
953    LOAD of A : : ~ | |
954                                            : :DIVIDE | |
955                                            : : ~ | |
956                                            : : ~ | |
957                                        rrrrrrrrrrrrrrrrr | |
958                                            +-------+ | |
959    The speculation is discarded ---> --->| A->1 |------>| |
960    and an updated value is +-------+ | |
961    retrieved : : +-------+
962
963
964TRANSITIVITY
965------------
966
967Transitivity is a deeply intuitive notion about ordering that is not
968always provided by real computer systems. The following example
969demonstrates transitivity (also called "cumulativity"):
970
971    CPU 1 CPU 2 CPU 3
972    ======================= ======================= =======================
973        { X = 0, Y = 0 }
974    STORE X=1 LOAD X STORE Y=1
975                <general barrier> <general barrier>
976                LOAD Y LOAD X
977
978Suppose that CPU 2's load from X returns 1 and its load from Y returns 0.
979This indicates that CPU 2's load from X in some sense follows CPU 1's
980store to X and that CPU 2's load from Y in some sense preceded CPU 3's
981store to Y. The question is then "Can CPU 3's load from X return 0?"
982
983Because CPU 2's load from X in some sense came after CPU 1's store, it
984is natural to expect that CPU 3's load from X must therefore return 1.
985This expectation is an example of transitivity: if a load executing on
986CPU A follows a load from the same variable executing on CPU B, then
987CPU A's load must either return the same value that CPU B's load did,
988or must return some later value.
989
990In the Linux kernel, use of general memory barriers guarantees
991transitivity. Therefore, in the above example, if CPU 2's load from X
992returns 1 and its load from Y returns 0, then CPU 3's load from X must
993also return 1.
994
995However, transitivity is -not- guaranteed for read or write barriers.
996For example, suppose that CPU 2's general barrier in the above example
997is changed to a read barrier as shown below:
998
999    CPU 1 CPU 2 CPU 3
1000    ======================= ======================= =======================
1001        { X = 0, Y = 0 }
1002    STORE X=1 LOAD X STORE Y=1
1003                <read barrier> <general barrier>
1004                LOAD Y LOAD X
1005
1006This substitution destroys transitivity: in this example, it is perfectly
1007legal for CPU 2's load from X to return 1, its load from Y to return 0,
1008and CPU 3's load from X to return 0.
1009
1010The key point is that although CPU 2's read barrier orders its pair
1011of loads, it does not guarantee to order CPU 1's store. Therefore, if
1012this example runs on a system where CPUs 1 and 2 share a store buffer
1013or a level of cache, CPU 2 might have early access to CPU 1's writes.
1014General barriers are therefore required to ensure that all CPUs agree
1015on the combined order of CPU 1's and CPU 2's accesses.
1016
1017To reiterate, if your code requires transitivity, use general barriers
1018throughout.
1019
1020
1021========================
1022EXPLICIT KERNEL BARRIERS
1023========================
1024
1025The Linux kernel has a variety of different barriers that act at different
1026levels:
1027
1028  (*) Compiler barrier.
1029
1030  (*) CPU memory barriers.
1031
1032  (*) MMIO write barrier.
1033
1034
1035COMPILER BARRIER
1036----------------
1037
1038The Linux kernel has an explicit compiler barrier function that prevents the
1039compiler from moving the memory accesses either side of it to the other side:
1040
1041    barrier();
1042
1043This is a general barrier - lesser varieties of compiler barrier do not exist.
1044
1045The compiler barrier has no direct effect on the CPU, which may then reorder
1046things however it wishes.
1047
1048
1049CPU MEMORY BARRIERS
1050-------------------
1051
1052The Linux kernel has eight basic CPU memory barriers:
1053
1054    TYPE MANDATORY SMP CONDITIONAL
1055    =============== ======================= ===========================
1056    GENERAL mb() smp_mb()
1057    WRITE wmb() smp_wmb()
1058    READ rmb() smp_rmb()
1059    DATA DEPENDENCY read_barrier_depends() smp_read_barrier_depends()
1060
1061
1062All memory barriers except the data dependency barriers imply a compiler
1063barrier. Data dependencies do not impose any additional compiler ordering.
1064
1065Aside: In the case of data dependencies, the compiler would be expected to
1066issue the loads in the correct order (eg. `a[b]` would have to load the value
1067of b before loading a[b]), however there is no guarantee in the C specification
1068that the compiler may not speculate the value of b (eg. is equal to 1) and load
1069a before b (eg. tmp = a[1]; if (b != 1) tmp = a[b]; ). There is also the
1070problem of a compiler reloading b after having loaded a[b], thus having a newer
1071copy of b than a[b]. A consensus has not yet been reached about these problems,
1072however the ACCESS_ONCE macro is a good place to start looking.
1073
1074SMP memory barriers are reduced to compiler barriers on uniprocessor compiled
1075systems because it is assumed that a CPU will appear to be self-consistent,
1076and will order overlapping accesses correctly with respect to itself.
1077
1078[!] Note that SMP memory barriers _must_ be used to control the ordering of
1079references to shared memory on SMP systems, though the use of locking instead
1080is sufficient.
1081
1082Mandatory barriers should not be used to control SMP effects, since mandatory
1083barriers unnecessarily impose overhead on UP systems. They may, however, be
1084used to control MMIO effects on accesses through relaxed memory I/O windows.
1085These are required even on non-SMP systems as they affect the order in which
1086memory operations appear to a device by prohibiting both the compiler and the
1087CPU from reordering them.
1088
1089
1090There are some more advanced barrier functions:
1091
1092 (*) set_mb(var, value)
1093
1094     This assigns the value to the variable and then inserts a full memory
1095     barrier after it, depending on the function. It isn't guaranteed to
1096     insert anything more than a compiler barrier in a UP compilation.
1097
1098
1099 (*) smp_mb__before_atomic_dec();
1100 (*) smp_mb__after_atomic_dec();
1101 (*) smp_mb__before_atomic_inc();
1102 (*) smp_mb__after_atomic_inc();
1103
1104     These are for use with atomic add, subtract, increment and decrement
1105     functions that don't return a value, especially when used for reference
1106     counting. These functions do not imply memory barriers.
1107
1108     As an example, consider a piece of code that marks an object as being dead
1109     and then decrements the object's reference count:
1110
1111    obj->dead = 1;
1112    smp_mb__before_atomic_dec();
1113    atomic_dec(&obj->ref_count);
1114
1115     This makes sure that the death mark on the object is perceived to be set
1116     *before* the reference counter is decremented.
1117
1118     See Documentation/atomic_ops.txt for more information. See the "Atomic
1119     operations" subsection for information on where to use these.
1120
1121
1122 (*) smp_mb__before_clear_bit(void);
1123 (*) smp_mb__after_clear_bit(void);
1124
1125     These are for use similar to the atomic inc/dec barriers. These are
1126     typically used for bitwise unlocking operations, so care must be taken as
1127     there are no implicit memory barriers here either.
1128
1129     Consider implementing an unlock operation of some nature by clearing a
1130     locking bit. The clear_bit() would then need to be barriered like this:
1131
1132    smp_mb__before_clear_bit();
1133    clear_bit( ... );
1134
1135     This prevents memory operations before the clear leaking to after it. See
1136     the subsection on "Locking Functions" with reference to UNLOCK operation
1137     implications.
1138
1139     See Documentation/atomic_ops.txt for more information. See the "Atomic
1140     operations" subsection for information on where to use these.
1141
1142
1143MMIO WRITE BARRIER
1144------------------
1145
1146The Linux kernel also has a special barrier for use with memory-mapped I/O
1147writes:
1148
1149    mmiowb();
1150
1151This is a variation on the mandatory write barrier that causes writes to weakly
1152ordered I/O regions to be partially ordered. Its effects may go beyond the
1153CPU->Hardware interface and actually affect the hardware at some level.
1154
1155See the subsection "Locks vs I/O accesses" for more information.
1156
1157
1158===============================
1159IMPLICIT KERNEL MEMORY BARRIERS
1160===============================
1161
1162Some of the other functions in the linux kernel imply memory barriers, amongst
1163which are locking and scheduling functions.
1164
1165This specification is a _minimum_ guarantee; any particular architecture may
1166provide more substantial guarantees, but these may not be relied upon outside
1167of arch specific code.
1168
1169
1170LOCKING FUNCTIONS
1171-----------------
1172
1173The Linux kernel has a number of locking constructs:
1174
1175 (*) spin locks
1176 (*) R/W spin locks
1177 (*) mutexes
1178 (*) semaphores
1179 (*) R/W semaphores
1180 (*) RCU
1181
1182In all cases there are variants on "LOCK" operations and "UNLOCK" operations
1183for each construct. These operations all imply certain barriers:
1184
1185 (1) LOCK operation implication:
1186
1187     Memory operations issued after the LOCK will be completed after the LOCK
1188     operation has completed.
1189
1190     Memory operations issued before the LOCK may be completed after the LOCK
1191     operation has completed.
1192
1193 (2) UNLOCK operation implication:
1194
1195     Memory operations issued before the UNLOCK will be completed before the
1196     UNLOCK operation has completed.
1197
1198     Memory operations issued after the UNLOCK may be completed before the
1199     UNLOCK operation has completed.
1200
1201 (3) LOCK vs LOCK implication:
1202
1203     All LOCK operations issued before another LOCK operation will be completed
1204     before that LOCK operation.
1205
1206 (4) LOCK vs UNLOCK implication:
1207
1208     All LOCK operations issued before an UNLOCK operation will be completed
1209     before the UNLOCK operation.
1210
1211     All UNLOCK operations issued before a LOCK operation will be completed
1212     before the LOCK operation.
1213
1214 (5) Failed conditional LOCK implication:
1215
1216     Certain variants of the LOCK operation may fail, either due to being
1217     unable to get the lock immediately, or due to receiving an unblocked
1218     signal whilst asleep waiting for the lock to become available. Failed
1219     locks do not imply any sort of barrier.
1220
1221Therefore, from (1), (2) and (4) an UNLOCK followed by an unconditional LOCK is
1222equivalent to a full barrier, but a LOCK followed by an UNLOCK is not.
1223
1224[!] Note: one of the consequences of LOCKs and UNLOCKs being only one-way
1225    barriers is that the effects of instructions outside of a critical section
1226    may seep into the inside of the critical section.
1227
1228A LOCK followed by an UNLOCK may not be assumed to be full memory barrier
1229because it is possible for an access preceding the LOCK to happen after the
1230LOCK, and an access following the UNLOCK to happen before the UNLOCK, and the
1231two accesses can themselves then cross:
1232
1233    *A = a;
1234    LOCK
1235    UNLOCK
1236    *B = b;
1237
1238may occur as:
1239
1240    LOCK, STORE *B, STORE *A, UNLOCK
1241
1242Locks and semaphores may not provide any guarantee of ordering on UP compiled
1243systems, and so cannot be counted on in such a situation to actually achieve
1244anything at all - especially with respect to I/O accesses - unless combined
1245with interrupt disabling operations.
1246
1247See also the section on "Inter-CPU locking barrier effects".
1248
1249
1250As an example, consider the following:
1251
1252    *A = a;
1253    *B = b;
1254    LOCK
1255    *C = c;
1256    *D = d;
1257    UNLOCK
1258    *E = e;
1259    *F = f;
1260
1261The following sequence of events is acceptable:
1262
1263    LOCK, {*F,*A}, *E, {*C,*D}, *B, UNLOCK
1264
1265    [+] Note that {*F,*A} indicates a combined access.
1266
1267But none of the following are:
1268
1269    {*F,*A}, *B, LOCK, *C, *D, UNLOCK, *E
1270    *A, *B, *C, LOCK, *D, UNLOCK, *E, *F
1271    *A, *B, LOCK, *C, UNLOCK, *D, *E, *F
1272    *B, LOCK, *C, *D, UNLOCK, {*F,*A}, *E
1273
1274
1275
1276INTERRUPT DISABLING FUNCTIONS
1277-----------------------------
1278
1279Functions that disable interrupts (LOCK equivalent) and enable interrupts
1280(UNLOCK equivalent) will act as compiler barriers only. So if memory or I/O
1281barriers are required in such a situation, they must be provided from some
1282other means.
1283
1284
1285SLEEP AND WAKE-UP FUNCTIONS
1286---------------------------
1287
1288Sleeping and waking on an event flagged in global data can be viewed as an
1289interaction between two pieces of data: the task state of the task waiting for
1290the event and the global data used to indicate the event. To make sure that
1291these appear to happen in the right order, the primitives to begin the process
1292of going to sleep, and the primitives to initiate a wake up imply certain
1293barriers.
1294
1295Firstly, the sleeper normally follows something like this sequence of events:
1296
1297    for (;;) {
1298        set_current_state(TASK_UNINTERRUPTIBLE);
1299        if (event_indicated)
1300            break;
1301        schedule();
1302    }
1303
1304A general memory barrier is interpolated automatically by set_current_state()
1305after it has altered the task state:
1306
1307    CPU 1
1308    ===============================
1309    set_current_state();
1310      set_mb();
1311        STORE current->state
1312        <general barrier>
1313    LOAD event_indicated
1314
1315set_current_state() may be wrapped by:
1316
1317    prepare_to_wait();
1318    prepare_to_wait_exclusive();
1319
1320which therefore also imply a general memory barrier after setting the state.
1321The whole sequence above is available in various canned forms, all of which
1322interpolate the memory barrier in the right place:
1323
1324    wait_event();
1325    wait_event_interruptible();
1326    wait_event_interruptible_exclusive();
1327    wait_event_interruptible_timeout();
1328    wait_event_killable();
1329    wait_event_timeout();
1330    wait_on_bit();
1331    wait_on_bit_lock();
1332
1333
1334Secondly, code that performs a wake up normally follows something like this:
1335
1336    event_indicated = 1;
1337    wake_up(&event_wait_queue);
1338
1339or:
1340
1341    event_indicated = 1;
1342    wake_up_process(event_daemon);
1343
1344A write memory barrier is implied by wake_up() and co. if and only if they wake
1345something up. The barrier occurs before the task state is cleared, and so sits
1346between the STORE to indicate the event and the STORE to set TASK_RUNNING:
1347
1348    CPU 1 CPU 2
1349    =============================== ===============================
1350    set_current_state(); STORE event_indicated
1351      set_mb(); wake_up();
1352        STORE current->state <write barrier>
1353        <general barrier> STORE current->state
1354    LOAD event_indicated
1355
1356The available waker functions include:
1357
1358    complete();
1359    wake_up();
1360    wake_up_all();
1361    wake_up_bit();
1362    wake_up_interruptible();
1363    wake_up_interruptible_all();
1364    wake_up_interruptible_nr();
1365    wake_up_interruptible_poll();
1366    wake_up_interruptible_sync();
1367    wake_up_interruptible_sync_poll();
1368    wake_up_locked();
1369    wake_up_locked_poll();
1370    wake_up_nr();
1371    wake_up_poll();
1372    wake_up_process();
1373
1374
1375[!] Note that the memory barriers implied by the sleeper and the waker do _not_
1376order multiple stores before the wake-up with respect to loads of those stored
1377values after the sleeper has called set_current_state(). For instance, if the
1378sleeper does:
1379
1380    set_current_state(TASK_INTERRUPTIBLE);
1381    if (event_indicated)
1382        break;
1383    __set_current_state(TASK_RUNNING);
1384    do_something(my_data);
1385
1386and the waker does:
1387
1388    my_data = value;
1389    event_indicated = 1;
1390    wake_up(&event_wait_queue);
1391
1392there's no guarantee that the change to event_indicated will be perceived by
1393the sleeper as coming after the change to my_data. In such a circumstance, the
1394code on both sides must interpolate its own memory barriers between the
1395separate data accesses. Thus the above sleeper ought to do:
1396
1397    set_current_state(TASK_INTERRUPTIBLE);
1398    if (event_indicated) {
1399        smp_rmb();
1400        do_something(my_data);
1401    }
1402
1403and the waker should do:
1404
1405    my_data = value;
1406    smp_wmb();
1407    event_indicated = 1;
1408    wake_up(&event_wait_queue);
1409
1410
1411MISCELLANEOUS FUNCTIONS
1412-----------------------
1413
1414Other functions that imply barriers:
1415
1416 (*) schedule() and similar imply full memory barriers.
1417
1418
1419=================================
1420INTER-CPU LOCKING BARRIER EFFECTS
1421=================================
1422
1423On SMP systems locking primitives give a more substantial form of barrier: one
1424that does affect memory access ordering on other CPUs, within the context of
1425conflict on any particular lock.
1426
1427
1428LOCKS VS MEMORY ACCESSES
1429------------------------
1430
1431Consider the following: the system has a pair of spinlocks (M) and (Q), and
1432three CPUs; then should the following sequence of events occur:
1433
1434    CPU 1 CPU 2
1435    =============================== ===============================
1436    *A = a; *E = e;
1437    LOCK M LOCK Q
1438    *B = b; *F = f;
1439    *C = c; *G = g;
1440    UNLOCK M UNLOCK Q
1441    *D = d; *H = h;
1442
1443Then there is no guarantee as to what order CPU 3 will see the accesses to *A
1444through *H occur in, other than the constraints imposed by the separate locks
1445on the separate CPUs. It might, for example, see:
1446
1447    *E, LOCK M, LOCK Q, *G, *C, *F, *A, *B, UNLOCK Q, *D, *H, UNLOCK M
1448
1449But it won't see any of:
1450
1451    *B, *C or *D preceding LOCK M
1452    *A, *B or *C following UNLOCK M
1453    *F, *G or *H preceding LOCK Q
1454    *E, *F or *G following UNLOCK Q
1455
1456
1457However, if the following occurs:
1458
1459    CPU 1 CPU 2
1460    =============================== ===============================
1461    *A = a;
1462    LOCK M [1]
1463    *B = b;
1464    *C = c;
1465    UNLOCK M [1]
1466    *D = d; *E = e;
1467                    LOCK M [2]
1468                    *F = f;
1469                    *G = g;
1470                    UNLOCK M [2]
1471                    *H = h;
1472
1473CPU 3 might see:
1474
1475    *E, LOCK M [1], *C, *B, *A, UNLOCK M [1],
1476        LOCK M [2], *H, *F, *G, UNLOCK M [2], *D
1477
1478But assuming CPU 1 gets the lock first, CPU 3 won't see any of:
1479
1480    *B, *C, *D, *F, *G or *H preceding LOCK M [1]
1481    *A, *B or *C following UNLOCK M [1]
1482    *F, *G or *H preceding LOCK M [2]
1483    *A, *B, *C, *E, *F or *G following UNLOCK M [2]
1484
1485
1486LOCKS VS I/O ACCESSES
1487---------------------
1488
1489Under certain circumstances (especially involving NUMA), I/O accesses within
1490two spinlocked sections on two different CPUs may be seen as interleaved by the
1491PCI bridge, because the PCI bridge does not necessarily participate in the
1492cache-coherence protocol, and is therefore incapable of issuing the required
1493read memory barriers.
1494
1495For example:
1496
1497    CPU 1 CPU 2
1498    =============================== ===============================
1499    spin_lock(Q)
1500    writel(0, ADDR)
1501    writel(1, DATA);
1502    spin_unlock(Q);
1503                    spin_lock(Q);
1504                    writel(4, ADDR);
1505                    writel(5, DATA);
1506                    spin_unlock(Q);
1507
1508may be seen by the PCI bridge as follows:
1509
1510    STORE *ADDR = 0, STORE *ADDR = 4, STORE *DATA = 1, STORE *DATA = 5
1511
1512which would probably cause the hardware to malfunction.
1513
1514
1515What is necessary here is to intervene with an mmiowb() before dropping the
1516spinlock, for example:
1517
1518    CPU 1 CPU 2
1519    =============================== ===============================
1520    spin_lock(Q)
1521    writel(0, ADDR)
1522    writel(1, DATA);
1523    mmiowb();
1524    spin_unlock(Q);
1525                    spin_lock(Q);
1526                    writel(4, ADDR);
1527                    writel(5, DATA);
1528                    mmiowb();
1529                    spin_unlock(Q);
1530
1531this will ensure that the two stores issued on CPU 1 appear at the PCI bridge
1532before either of the stores issued on CPU 2.
1533
1534
1535Furthermore, following a store by a load from the same device obviates the need
1536for the mmiowb(), because the load forces the store to complete before the load
1537is performed:
1538
1539    CPU 1 CPU 2
1540    =============================== ===============================
1541    spin_lock(Q)
1542    writel(0, ADDR)
1543    a = readl(DATA);
1544    spin_unlock(Q);
1545                    spin_lock(Q);
1546                    writel(4, ADDR);
1547                    b = readl(DATA);
1548                    spin_unlock(Q);
1549
1550
1551See Documentation/DocBook/deviceiobook.tmpl for more information.
1552
1553
1554=================================
1555WHERE ARE MEMORY BARRIERS NEEDED?
1556=================================
1557
1558Under normal operation, memory operation reordering is generally not going to
1559be a problem as a single-threaded linear piece of code will still appear to
1560work correctly, even if it's in an SMP kernel. There are, however, four
1561circumstances in which reordering definitely _could_ be a problem:
1562
1563 (*) Interprocessor interaction.
1564
1565 (*) Atomic operations.
1566
1567 (*) Accessing devices.
1568
1569 (*) Interrupts.
1570
1571
1572INTERPROCESSOR INTERACTION
1573--------------------------
1574
1575When there's a system with more than one processor, more than one CPU in the
1576system may be working on the same data set at the same time. This can cause
1577synchronisation problems, and the usual way of dealing with them is to use
1578locks. Locks, however, are quite expensive, and so it may be preferable to
1579operate without the use of a lock if at all possible. In such a case
1580operations that affect both CPUs may have to be carefully ordered to prevent
1581a malfunction.
1582
1583Consider, for example, the R/W semaphore slow path. Here a waiting process is
1584queued on the semaphore, by virtue of it having a piece of its stack linked to
1585the semaphore's list of waiting processes:
1586
1587    struct rw_semaphore {
1588        ...
1589        spinlock_t lock;
1590        struct list_head waiters;
1591    };
1592
1593    struct rwsem_waiter {
1594        struct list_head list;
1595        struct task_struct *task;
1596    };
1597
1598To wake up a particular waiter, the up_read() or up_write() functions have to:
1599
1600 (1) read the next pointer from this waiter's record to know as to where the
1601     next waiter record is;
1602
1603 (2) read the pointer to the waiter's task structure;
1604
1605 (3) clear the task pointer to tell the waiter it has been given the semaphore;
1606
1607 (4) call wake_up_process() on the task; and
1608
1609 (5) release the reference held on the waiter's task struct.
1610
1611In other words, it has to perform this sequence of events:
1612
1613    LOAD waiter->list.next;
1614    LOAD waiter->task;
1615    STORE waiter->task;
1616    CALL wakeup
1617    RELEASE task
1618
1619and if any of these steps occur out of order, then the whole thing may
1620malfunction.
1621
1622Once it has queued itself and dropped the semaphore lock, the waiter does not
1623get the lock again; it instead just waits for its task pointer to be cleared
1624before proceeding. Since the record is on the waiter's stack, this means that
1625if the task pointer is cleared _before_ the next pointer in the list is read,
1626another CPU might start processing the waiter and might clobber the waiter's
1627stack before the up*() function has a chance to read the next pointer.
1628
1629Consider then what might happen to the above sequence of events:
1630
1631    CPU 1 CPU 2
1632    =============================== ===============================
1633                    down_xxx()
1634                    Queue waiter
1635                    Sleep
1636    up_yyy()
1637    LOAD waiter->task;
1638    STORE waiter->task;
1639                    Woken up by other event
1640    <preempt>
1641                    Resume processing
1642                    down_xxx() returns
1643                    call foo()
1644                    foo() clobbers *waiter
1645    </preempt>
1646    LOAD waiter->list.next;
1647    --- OOPS ---
1648
1649This could be dealt with using the semaphore lock, but then the down_xxx()
1650function has to needlessly get the spinlock again after being woken up.
1651
1652The way to deal with this is to insert a general SMP memory barrier:
1653
1654    LOAD waiter->list.next;
1655    LOAD waiter->task;
1656    smp_mb();
1657    STORE waiter->task;
1658    CALL wakeup
1659    RELEASE task
1660
1661In this case, the barrier makes a guarantee that all memory accesses before the
1662barrier will appear to happen before all the memory accesses after the barrier
1663with respect to the other CPUs on the system. It does _not_ guarantee that all
1664the memory accesses before the barrier will be complete by the time the barrier
1665instruction itself is complete.
1666
1667On a UP system - where this wouldn't be a problem - the smp_mb() is just a
1668compiler barrier, thus making sure the compiler emits the instructions in the
1669right order without actually intervening in the CPU. Since there's only one
1670CPU, that CPU's dependency ordering logic will take care of everything else.
1671
1672
1673ATOMIC OPERATIONS
1674-----------------
1675
1676Whilst they are technically interprocessor interaction considerations, atomic
1677operations are noted specially as some of them imply full memory barriers and
1678some don't, but they're very heavily relied on as a group throughout the
1679kernel.
1680
1681Any atomic operation that modifies some state in memory and returns information
1682about the state (old or new) implies an SMP-conditional general memory barrier
1683(smp_mb()) on each side of the actual operation (with the exception of
1684explicit lock operations, described later). These include:
1685
1686    xchg();
1687    cmpxchg();
1688    atomic_xchg();
1689    atomic_cmpxchg();
1690    atomic_inc_return();
1691    atomic_dec_return();
1692    atomic_add_return();
1693    atomic_sub_return();
1694    atomic_inc_and_test();
1695    atomic_dec_and_test();
1696    atomic_sub_and_test();
1697    atomic_add_negative();
1698    atomic_add_unless(); /* when succeeds (returns 1) */
1699    test_and_set_bit();
1700    test_and_clear_bit();
1701    test_and_change_bit();
1702
1703These are used for such things as implementing LOCK-class and UNLOCK-class
1704operations and adjusting reference counters towards object destruction, and as
1705such the implicit memory barrier effects are necessary.
1706
1707
1708The following operations are potential problems as they do _not_ imply memory
1709barriers, but might be used for implementing such things as UNLOCK-class
1710operations:
1711
1712    atomic_set();
1713    set_bit();
1714    clear_bit();
1715    change_bit();
1716
1717With these the appropriate explicit memory barrier should be used if necessary
1718(smp_mb__before_clear_bit() for instance).
1719
1720
1721The following also do _not_ imply memory barriers, and so may require explicit
1722memory barriers under some circumstances (smp_mb__before_atomic_dec() for
1723instance):
1724
1725    atomic_add();
1726    atomic_sub();
1727    atomic_inc();
1728    atomic_dec();
1729
1730If they're used for statistics generation, then they probably don't need memory
1731barriers, unless there's a coupling between statistical data.
1732
1733If they're used for reference counting on an object to control its lifetime,
1734they probably don't need memory barriers because either the reference count
1735will be adjusted inside a locked section, or the caller will already hold
1736sufficient references to make the lock, and thus a memory barrier unnecessary.
1737
1738If they're used for constructing a lock of some description, then they probably
1739do need memory barriers as a lock primitive generally has to do things in a
1740specific order.
1741
1742Basically, each usage case has to be carefully considered as to whether memory
1743barriers are needed or not.
1744
1745The following operations are special locking primitives:
1746
1747    test_and_set_bit_lock();
1748    clear_bit_unlock();
1749    __clear_bit_unlock();
1750
1751These implement LOCK-class and UNLOCK-class operations. These should be used in
1752preference to other operations when implementing locking primitives, because
1753their implementations can be optimised on many architectures.
1754
1755[!] Note that special memory barrier primitives are available for these
1756situations because on some CPUs the atomic instructions used imply full memory
1757barriers, and so barrier instructions are superfluous in conjunction with them,
1758and in such cases the special barrier primitives will be no-ops.
1759
1760See Documentation/atomic_ops.txt for more information.
1761
1762
1763ACCESSING DEVICES
1764-----------------
1765
1766Many devices can be memory mapped, and so appear to the CPU as if they're just
1767a set of memory locations. To control such a device, the driver usually has to
1768make the right memory accesses in exactly the right order.
1769
1770However, having a clever CPU or a clever compiler creates a potential problem
1771in that the carefully sequenced accesses in the driver code won't reach the
1772device in the requisite order if the CPU or the compiler thinks it is more
1773efficient to reorder, combine or merge accesses - something that would cause
1774the device to malfunction.
1775
1776Inside of the Linux kernel, I/O should be done through the appropriate accessor
1777routines - such as inb() or writel() - which know how to make such accesses
1778appropriately sequential. Whilst this, for the most part, renders the explicit
1779use of memory barriers unnecessary, there are a couple of situations where they
1780might be needed:
1781
1782 (1) On some systems, I/O stores are not strongly ordered across all CPUs, and
1783     so for _all_ general drivers locks should be used and mmiowb() must be
1784     issued prior to unlocking the critical section.
1785
1786 (2) If the accessor functions are used to refer to an I/O memory window with
1787     relaxed memory access properties, then _mandatory_ memory barriers are
1788     required to enforce ordering.
1789
1790See Documentation/DocBook/deviceiobook.tmpl for more information.
1791
1792
1793INTERRUPTS
1794----------
1795
1796A driver may be interrupted by its own interrupt service routine, and thus the
1797two parts of the driver may interfere with each other's attempts to control or
1798access the device.
1799
1800This may be alleviated - at least in part - by disabling local interrupts (a
1801form of locking), such that the critical operations are all contained within
1802the interrupt-disabled section in the driver. Whilst the driver's interrupt
1803routine is executing, the driver's core may not run on the same CPU, and its
1804interrupt is not permitted to happen again until the current interrupt has been
1805handled, thus the interrupt handler does not need to lock against that.
1806
1807However, consider a driver that was talking to an ethernet card that sports an
1808address register and a data register. If that driver's core talks to the card
1809under interrupt-disablement and then the driver's interrupt handler is invoked:
1810
1811    LOCAL IRQ DISABLE
1812    writew(ADDR, 3);
1813    writew(DATA, y);
1814    LOCAL IRQ ENABLE
1815    <interrupt>
1816    writew(ADDR, 4);
1817    q = readw(DATA);
1818    </interrupt>
1819
1820The store to the data register might happen after the second store to the
1821address register if ordering rules are sufficiently relaxed:
1822
1823    STORE *ADDR = 3, STORE *ADDR = 4, STORE *DATA = y, q = LOAD *DATA
1824
1825
1826If ordering rules are relaxed, it must be assumed that accesses done inside an
1827interrupt disabled section may leak outside of it and may interleave with
1828accesses performed in an interrupt - and vice versa - unless implicit or
1829explicit barriers are used.
1830
1831Normally this won't be a problem because the I/O accesses done inside such
1832sections will include synchronous load operations on strictly ordered I/O
1833registers that form implicit I/O barriers. If this isn't sufficient then an
1834mmiowb() may need to be used explicitly.
1835
1836
1837A similar situation may occur between an interrupt routine and two routines
1838running on separate CPUs that communicate with each other. If such a case is
1839likely, then interrupt-disabling locks should be used to guarantee ordering.
1840
1841
1842==========================
1843KERNEL I/O BARRIER EFFECTS
1844==========================
1845
1846When accessing I/O memory, drivers should use the appropriate accessor
1847functions:
1848
1849 (*) inX(), outX():
1850
1851     These are intended to talk to I/O space rather than memory space, but
1852     that's primarily a CPU-specific concept. The i386 and x86_64 processors do
1853     indeed have special I/O space access cycles and instructions, but many
1854     CPUs don't have such a concept.
1855
1856     The PCI bus, amongst others, defines an I/O space concept which - on such
1857     CPUs as i386 and x86_64 - readily maps to the CPU's concept of I/O
1858     space. However, it may also be mapped as a virtual I/O space in the CPU's
1859     memory map, particularly on those CPUs that don't support alternate I/O
1860     spaces.
1861
1862     Accesses to this space may be fully synchronous (as on i386), but
1863     intermediary bridges (such as the PCI host bridge) may not fully honour
1864     that.
1865
1866     They are guaranteed to be fully ordered with respect to each other.
1867
1868     They are not guaranteed to be fully ordered with respect to other types of
1869     memory and I/O operation.
1870
1871 (*) readX(), writeX():
1872
1873     Whether these are guaranteed to be fully ordered and uncombined with
1874     respect to each other on the issuing CPU depends on the characteristics
1875     defined for the memory window through which they're accessing. On later
1876     i386 architecture machines, for example, this is controlled by way of the
1877     MTRR registers.
1878
1879     Ordinarily, these will be guaranteed to be fully ordered and uncombined,
1880     provided they're not accessing a prefetchable device.
1881
1882     However, intermediary hardware (such as a PCI bridge) may indulge in
1883     deferral if it so wishes; to flush a store, a load from the same location
1884     is preferred[*], but a load from the same device or from configuration
1885     space should suffice for PCI.
1886
1887     [*] NOTE! attempting to load from the same location as was written to may
1888          cause a malfunction - consider the 16550 Rx/Tx serial registers for
1889          example.
1890
1891     Used with prefetchable I/O memory, an mmiowb() barrier may be required to
1892     force stores to be ordered.
1893
1894     Please refer to the PCI specification for more information on interactions
1895     between PCI transactions.
1896
1897 (*) readX_relaxed()
1898
1899     These are similar to readX(), but are not guaranteed to be ordered in any
1900     way. Be aware that there is no I/O read barrier available.
1901
1902 (*) ioreadX(), iowriteX()
1903
1904     These will perform appropriately for the type of access they're actually
1905     doing, be it inX()/outX() or readX()/writeX().
1906
1907
1908========================================
1909ASSUMED MINIMUM EXECUTION ORDERING MODEL
1910========================================
1911
1912It has to be assumed that the conceptual CPU is weakly-ordered but that it will
1913maintain the appearance of program causality with respect to itself. Some CPUs
1914(such as i386 or x86_64) are more constrained than others (such as powerpc or
1915frv), and so the most relaxed case (namely DEC Alpha) must be assumed outside
1916of arch-specific code.
1917
1918This means that it must be considered that the CPU will execute its instruction
1919stream in any order it feels like - or even in parallel - provided that if an
1920instruction in the stream depends on an earlier instruction, then that
1921earlier instruction must be sufficiently complete[*] before the later
1922instruction may proceed; in other words: provided that the appearance of
1923causality is maintained.
1924
1925 [*] Some instructions have more than one effect - such as changing the
1926     condition codes, changing registers or changing memory - and different
1927     instructions may depend on different effects.
1928
1929A CPU may also discard any instruction sequence that winds up having no
1930ultimate effect. For example, if two adjacent instructions both load an
1931immediate value into the same register, the first may be discarded.
1932
1933
1934Similarly, it has to be assumed that compiler might reorder the instruction
1935stream in any way it sees fit, again provided the appearance of causality is
1936maintained.
1937
1938
1939============================
1940THE EFFECTS OF THE CPU CACHE
1941============================
1942
1943The way cached memory operations are perceived across the system is affected to
1944a certain extent by the caches that lie between CPUs and memory, and by the
1945memory coherence system that maintains the consistency of state in the system.
1946
1947As far as the way a CPU interacts with another part of the system through the
1948caches goes, the memory system has to include the CPU's caches, and memory
1949barriers for the most part act at the interface between the CPU and its cache
1950(memory barriers logically act on the dotted line in the following diagram):
1951
1952        <--- CPU ---> : <----------- Memory ----------->
1953                              :
1954    +--------+ +--------+ : +--------+ +-----------+
1955    | | | | : | | | | +--------+
1956    | CPU | | Memory | : | CPU | | | | |
1957    | Core |--->| Access |----->| Cache |<-->| | | |
1958    | | | Queue | : | | | |--->| Memory |
1959    | | | | : | | | | | |
1960    +--------+ +--------+ : +--------+ | | | |
1961                              : | Cache | +--------+
1962                              : | Coherency |
1963                              : | Mechanism | +--------+
1964    +--------+ +--------+ : +--------+ | | | |
1965    | | | | : | | | | | |
1966    | CPU | | Memory | : | CPU | | |--->| Device |
1967    | Core |--->| Access |----->| Cache |<-->| | | |
1968    | | | Queue | : | | | | | |
1969    | | | | : | | | | +--------+
1970    +--------+ +--------+ : +--------+ +-----------+
1971                              :
1972                              :
1973
1974Although any particular load or store may not actually appear outside of the
1975CPU that issued it since it may have been satisfied within the CPU's own cache,
1976it will still appear as if the full memory access had taken place as far as the
1977other CPUs are concerned since the cache coherency mechanisms will migrate the
1978cacheline over to the accessing CPU and propagate the effects upon conflict.
1979
1980The CPU core may execute instructions in any order it deems fit, provided the
1981expected program causality appears to be maintained. Some of the instructions
1982generate load and store operations which then go into the queue of memory
1983accesses to be performed. The core may place these in the queue in any order
1984it wishes, and continue execution until it is forced to wait for an instruction
1985to complete.
1986
1987What memory barriers are concerned with is controlling the order in which
1988accesses cross from the CPU side of things to the memory side of things, and
1989the order in which the effects are perceived to happen by the other observers
1990in the system.
1991
1992[!] Memory barriers are _not_ needed within a given CPU, as CPUs always see
1993their own loads and stores as if they had happened in program order.
1994
1995[!] MMIO or other device accesses may bypass the cache system. This depends on
1996the properties of the memory window through which devices are accessed and/or
1997the use of any special device communication instructions the CPU may have.
1998
1999
2000CACHE COHERENCY
2001---------------
2002
2003Life isn't quite as simple as it may appear above, however: for while the
2004caches are expected to be coherent, there's no guarantee that that coherency
2005will be ordered. This means that whilst changes made on one CPU will
2006eventually become visible on all CPUs, there's no guarantee that they will
2007become apparent in the same order on those other CPUs.
2008
2009
2010Consider dealing with a system that has a pair of CPUs (1 & 2), each of which
2011has a pair of parallel data caches (CPU 1 has A/B, and CPU 2 has C/D):
2012
2013                :
2014                : +--------+
2015                : +---------+ | |
2016    +--------+ : +--->| Cache A |<------->| |
2017    | | : | +---------+ | |
2018    | CPU 1 |<---+ | |
2019    | | : | +---------+ | |
2020    +--------+ : +--->| Cache B |<------->| |
2021                : +---------+ | |
2022                : | Memory |
2023                : +---------+ | System |
2024    +--------+ : +--->| Cache C |<------->| |
2025    | | : | +---------+ | |
2026    | CPU 2 |<---+ | |
2027    | | : | +---------+ | |
2028    +--------+ : +--->| Cache D |<------->| |
2029                : +---------+ | |
2030                : +--------+
2031                :
2032
2033Imagine the system has the following properties:
2034
2035 (*) an odd-numbered cache line may be in cache A, cache C or it may still be
2036     resident in memory;
2037
2038 (*) an even-numbered cache line may be in cache B, cache D or it may still be
2039     resident in memory;
2040
2041 (*) whilst the CPU core is interrogating one cache, the other cache may be
2042     making use of the bus to access the rest of the system - perhaps to
2043     displace a dirty cacheline or to do a speculative load;
2044
2045 (*) each cache has a queue of operations that need to be applied to that cache
2046     to maintain coherency with the rest of the system;
2047
2048 (*) the coherency queue is not flushed by normal loads to lines already
2049     present in the cache, even though the contents of the queue may
2050     potentially affect those loads.
2051
2052Imagine, then, that two writes are made on the first CPU, with a write barrier
2053between them to guarantee that they will appear to reach that CPU's caches in
2054the requisite order:
2055
2056    CPU 1 CPU 2 COMMENT
2057    =============== =============== =======================================
2058                    u == 0, v == 1 and p == &u, q == &u
2059    v = 2;
2060    smp_wmb(); Make sure change to v is visible before
2061                     change to p
2062    <A:modify v=2> v is now in cache A exclusively
2063    p = &v;
2064    <B:modify p=&v> p is now in cache B exclusively
2065
2066The write memory barrier forces the other CPUs in the system to perceive that
2067the local CPU's caches have apparently been updated in the correct order. But
2068now imagine that the second CPU wants to read those values:
2069
2070    CPU 1 CPU 2 COMMENT
2071    =============== =============== =======================================
2072    ...
2073            q = p;
2074            x = *q;
2075
2076The above pair of reads may then fail to happen in the expected order, as the
2077cacheline holding p may get updated in one of the second CPU's caches whilst
2078the update to the cacheline holding v is delayed in the other of the second
2079CPU's caches by some other cache event:
2080
2081    CPU 1 CPU 2 COMMENT
2082    =============== =============== =======================================
2083                    u == 0, v == 1 and p == &u, q == &u
2084    v = 2;
2085    smp_wmb();
2086    <A:modify v=2> <C:busy>
2087            <C:queue v=2>
2088    p = &v; q = p;
2089            <D:request p>
2090    <B:modify p=&v> <D:commit p=&v>
2091              <D:read p>
2092            x = *q;
2093            <C:read *q> Reads from v before v updated in cache
2094            <C:unbusy>
2095            <C:commit v=2>
2096
2097Basically, whilst both cachelines will be updated on CPU 2 eventually, there's
2098no guarantee that, without intervention, the order of update will be the same
2099as that committed on CPU 1.
2100
2101
2102To intervene, we need to interpolate a data dependency barrier or a read
2103barrier between the loads. This will force the cache to commit its coherency
2104queue before processing any further requests:
2105
2106    CPU 1 CPU 2 COMMENT
2107    =============== =============== =======================================
2108                    u == 0, v == 1 and p == &u, q == &u
2109    v = 2;
2110    smp_wmb();
2111    <A:modify v=2> <C:busy>
2112            <C:queue v=2>
2113    p = &v; q = p;
2114            <D:request p>
2115    <B:modify p=&v> <D:commit p=&v>
2116              <D:read p>
2117            smp_read_barrier_depends()
2118            <C:unbusy>
2119            <C:commit v=2>
2120            x = *q;
2121            <C:read *q> Reads from v after v updated in cache
2122
2123
2124This sort of problem can be encountered on DEC Alpha processors as they have a
2125split cache that improves performance by making better use of the data bus.
2126Whilst most CPUs do imply a data dependency barrier on the read when a memory
2127access depends on a read, not all do, so it may not be relied on.
2128
2129Other CPUs may also have split caches, but must coordinate between the various
2130cachelets for normal memory accesses. The semantics of the Alpha removes the
2131need for coordination in the absence of memory barriers.
2132
2133
2134CACHE COHERENCY VS DMA
2135----------------------
2136
2137Not all systems maintain cache coherency with respect to devices doing DMA. In
2138such cases, a device attempting DMA may obtain stale data from RAM because
2139dirty cache lines may be resident in the caches of various CPUs, and may not
2140have been written back to RAM yet. To deal with this, the appropriate part of
2141the kernel must flush the overlapping bits of cache on each CPU (and maybe
2142invalidate them as well).
2143
2144In addition, the data DMA'd to RAM by a device may be overwritten by dirty
2145cache lines being written back to RAM from a CPU's cache after the device has
2146installed its own data, or cache lines present in the CPU's cache may simply
2147obscure the fact that RAM has been updated, until at such time as the cacheline
2148is discarded from the CPU's cache and reloaded. To deal with this, the
2149appropriate part of the kernel must invalidate the overlapping bits of the
2150cache on each CPU.
2151
2152See Documentation/cachetlb.txt for more information on cache management.
2153
2154
2155CACHE COHERENCY VS MMIO
2156-----------------------
2157
2158Memory mapped I/O usually takes place through memory locations that are part of
2159a window in the CPU's memory space that has different properties assigned than
2160the usual RAM directed window.
2161
2162Amongst these properties is usually the fact that such accesses bypass the
2163caching entirely and go directly to the device buses. This means MMIO accesses
2164may, in effect, overtake accesses to cached memory that were emitted earlier.
2165A memory barrier isn't sufficient in such a case, but rather the cache must be
2166flushed between the cached memory write and the MMIO access if the two are in
2167any way dependent.
2168
2169
2170=========================
2171THE THINGS CPUS GET UP TO
2172=========================
2173
2174A programmer might take it for granted that the CPU will perform memory
2175operations in exactly the order specified, so that if the CPU is, for example,
2176given the following piece of code to execute:
2177
2178    a = *A;
2179    *B = b;
2180    c = *C;
2181    d = *D;
2182    *E = e;
2183
2184they would then expect that the CPU will complete the memory operation for each
2185instruction before moving on to the next one, leading to a definite sequence of
2186operations as seen by external observers in the system:
2187
2188    LOAD *A, STORE *B, LOAD *C, LOAD *D, STORE *E.
2189
2190
2191Reality is, of course, much messier. With many CPUs and compilers, the above
2192assumption doesn't hold because:
2193
2194 (*) loads are more likely to need to be completed immediately to permit
2195     execution progress, whereas stores can often be deferred without a
2196     problem;
2197
2198 (*) loads may be done speculatively, and the result discarded should it prove
2199     to have been unnecessary;
2200
2201 (*) loads may be done speculatively, leading to the result having been fetched
2202     at the wrong time in the expected sequence of events;
2203
2204 (*) the order of the memory accesses may be rearranged to promote better use
2205     of the CPU buses and caches;
2206
2207 (*) loads and stores may be combined to improve performance when talking to
2208     memory or I/O hardware that can do batched accesses of adjacent locations,
2209     thus cutting down on transaction setup costs (memory and PCI devices may
2210     both be able to do this); and
2211
2212 (*) the CPU's data cache may affect the ordering, and whilst cache-coherency
2213     mechanisms may alleviate this - once the store has actually hit the cache
2214     - there's no guarantee that the coherency management will be propagated in
2215     order to other CPUs.
2216
2217So what another CPU, say, might actually observe from the above piece of code
2218is:
2219
2220    LOAD *A, ..., LOAD {*C,*D}, STORE *E, STORE *B
2221
2222    (Where "LOAD {*C,*D}" is a combined load)
2223
2224
2225However, it is guaranteed that a CPU will be self-consistent: it will see its
2226_own_ accesses appear to be correctly ordered, without the need for a memory
2227barrier. For instance with the following code:
2228
2229    U = *A;
2230    *A = V;
2231    *A = W;
2232    X = *A;
2233    *A = Y;
2234    Z = *A;
2235
2236and assuming no intervention by an external influence, it can be assumed that
2237the final result will appear to be:
2238
2239    U == the original value of *A
2240    X == W
2241    Z == Y
2242    *A == Y
2243
2244The code above may cause the CPU to generate the full sequence of memory
2245accesses:
2246
2247    U=LOAD *A, STORE *A=V, STORE *A=W, X=LOAD *A, STORE *A=Y, Z=LOAD *A
2248
2249in that order, but, without intervention, the sequence may have almost any
2250combination of elements combined or discarded, provided the program's view of
2251the world remains consistent.
2252
2253The compiler may also combine, discard or defer elements of the sequence before
2254the CPU even sees them.
2255
2256For instance:
2257
2258    *A = V;
2259    *A = W;
2260
2261may be reduced to:
2262
2263    *A = W;
2264
2265since, without a write barrier, it can be assumed that the effect of the
2266storage of V to *A is lost. Similarly:
2267
2268    *A = Y;
2269    Z = *A;
2270
2271may, without a memory barrier, be reduced to:
2272
2273    *A = Y;
2274    Z = Y;
2275
2276and the LOAD operation never appear outside of the CPU.
2277
2278
2279AND THEN THERE'S THE ALPHA
2280--------------------------
2281
2282The DEC Alpha CPU is one of the most relaxed CPUs there is. Not only that,
2283some versions of the Alpha CPU have a split data cache, permitting them to have
2284two semantically-related cache lines updated at separate times. This is where
2285the data dependency barrier really becomes necessary as this synchronises both
2286caches with the memory coherence system, thus making it seem like pointer
2287changes vs new data occur in the right order.
2288
2289The Alpha defines the Linux kernel's memory barrier model.
2290
2291See the subsection on "Cache Coherency" above.
2292
2293
2294============
2295EXAMPLE USES
2296============
2297
2298CIRCULAR BUFFERS
2299----------------
2300
2301Memory barriers can be used to implement circular buffering without the need
2302of a lock to serialise the producer with the consumer. See:
2303
2304    Documentation/circular-buffers.txt
2305
2306for details.
2307
2308
2309==========
2310REFERENCES
2311==========
2312
2313Alpha AXP Architecture Reference Manual, Second Edition (Sites & Witek,
2314Digital Press)
2315    Chapter 5.2: Physical Address Space Characteristics
2316    Chapter 5.4: Caches and Write Buffers
2317    Chapter 5.5: Data Sharing
2318    Chapter 5.6: Read/Write Ordering
2319
2320AMD64 Architecture Programmer's Manual Volume 2: System Programming
2321    Chapter 7.1: Memory-Access Ordering
2322    Chapter 7.4: Buffering and Combining Memory Writes
2323
2324IA-32 Intel Architecture Software Developer's Manual, Volume 3:
2325System Programming Guide
2326    Chapter 7.1: Locked Atomic Operations
2327    Chapter 7.2: Memory Ordering
2328    Chapter 7.4: Serializing Instructions
2329
2330The SPARC Architecture Manual, Version 9
2331    Chapter 8: Memory Models
2332    Appendix D: Formal Specification of the Memory Models
2333    Appendix J: Programming with the Memory Models
2334
2335UltraSPARC Programmer Reference Manual
2336    Chapter 5: Memory Accesses and Cacheability
2337    Chapter 15: Sparc-V9 Memory Models
2338
2339UltraSPARC III Cu User's Manual
2340    Chapter 9: Memory Models
2341
2342UltraSPARC IIIi Processor User's Manual
2343    Chapter 8: Memory Models
2344
2345UltraSPARC Architecture 2005
2346    Chapter 9: Memory
2347    Appendix D: Formal Specifications of the Memory Models
2348
2349UltraSPARC T1 Supplement to the UltraSPARC Architecture 2005
2350    Chapter 8: Memory Models
2351    Appendix F: Caches and Cache Coherency
2352
2353Solaris Internals, Core Kernel Architecture, p63-68:
2354    Chapter 3.3: Hardware Considerations for Locks and
2355            Synchronization
2356
2357Unix Systems for Modern Architectures, Symmetric Multiprocessing and Caching
2358for Kernel Programmers:
2359    Chapter 13: Other Memory Models
2360
2361Intel Itanium Architecture Software Developer's Manual: Volume 1:
2362    Section 2.6: Speculation
2363    Section 4.4: Memory Access
2364

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