Root/Documentation/pinctrl.txt

1PINCTRL (PIN CONTROL) subsystem
2This document outlines the pin control subsystem in Linux
3
4This subsystem deals with:
5
6- Enumerating and naming controllable pins
7
8- Multiplexing of pins, pads, fingers (etc) see below for details
9
10- Configuration of pins, pads, fingers (etc), such as software-controlled
11  biasing and driving mode specific pins, such as pull-up/down, open drain,
12  load capacitance etc.
13
14Top-level interface
15===================
16
17Definition of PIN CONTROLLER:
18
19- A pin controller is a piece of hardware, usually a set of registers, that
20  can control PINs. It may be able to multiplex, bias, set load capacitance,
21  set drive strength etc for individual pins or groups of pins.
22
23Definition of PIN:
24
25- PINS are equal to pads, fingers, balls or whatever packaging input or
26  output line you want to control and these are denoted by unsigned integers
27  in the range 0..maxpin. This numberspace is local to each PIN CONTROLLER, so
28  there may be several such number spaces in a system. This pin space may
29  be sparse - i.e. there may be gaps in the space with numbers where no
30  pin exists.
31
32When a PIN CONTROLLER is instantiated, it will register a descriptor to the
33pin control framework, and this descriptor contains an array of pin descriptors
34describing the pins handled by this specific pin controller.
35
36Here is an example of a PGA (Pin Grid Array) chip seen from underneath:
37
38        A B C D E F G H
39
40   8 o o o o o o o o
41
42   7 o o o o o o o o
43
44   6 o o o o o o o o
45
46   5 o o o o o o o o
47
48   4 o o o o o o o o
49
50   3 o o o o o o o o
51
52   2 o o o o o o o o
53
54   1 o o o o o o o o
55
56To register a pin controller and name all the pins on this package we can do
57this in our driver:
58
59#include <linux/pinctrl/pinctrl.h>
60
61const struct pinctrl_pin_desc foo_pins[] = {
62      PINCTRL_PIN(0, "A8"),
63      PINCTRL_PIN(1, "B8"),
64      PINCTRL_PIN(2, "C8"),
65      ...
66      PINCTRL_PIN(61, "F1"),
67      PINCTRL_PIN(62, "G1"),
68      PINCTRL_PIN(63, "H1"),
69};
70
71static struct pinctrl_desc foo_desc = {
72    .name = "foo",
73    .pins = foo_pins,
74    .npins = ARRAY_SIZE(foo_pins),
75    .maxpin = 63,
76    .owner = THIS_MODULE,
77};
78
79int __init foo_probe(void)
80{
81    struct pinctrl_dev *pctl;
82
83    pctl = pinctrl_register(&foo_desc, <PARENT>, NULL);
84    if (IS_ERR(pctl))
85        pr_err("could not register foo pin driver\n");
86}
87
88To enable the pinctrl subsystem and the subgroups for PINMUX and PINCONF and
89selected drivers, you need to select them from your machine's Kconfig entry,
90since these are so tightly integrated with the machines they are used on.
91See for example arch/arm/mach-u300/Kconfig for an example.
92
93Pins usually have fancier names than this. You can find these in the dataheet
94for your chip. Notice that the core pinctrl.h file provides a fancy macro
95called PINCTRL_PIN() to create the struct entries. As you can see I enumerated
96the pins from 0 in the upper left corner to 63 in the lower right corner.
97This enumeration was arbitrarily chosen, in practice you need to think
98through your numbering system so that it matches the layout of registers
99and such things in your driver, or the code may become complicated. You must
100also consider matching of offsets to the GPIO ranges that may be handled by
101the pin controller.
102
103For a padring with 467 pads, as opposed to actual pins, I used an enumeration
104like this, walking around the edge of the chip, which seems to be industry
105standard too (all these pads had names, too):
106
107
108     0 ..... 104
109   466 105
110     . .
111     . .
112   358 224
113    357 .... 225
114
115
116Pin groups
117==========
118
119Many controllers need to deal with groups of pins, so the pin controller
120subsystem has a mechanism for enumerating groups of pins and retrieving the
121actual enumerated pins that are part of a certain group.
122
123For example, say that we have a group of pins dealing with an SPI interface
124on { 0, 8, 16, 24 }, and a group of pins dealing with an I2C interface on pins
125on { 24, 25 }.
126
127These two groups are presented to the pin control subsystem by implementing
128some generic pinctrl_ops like this:
129
130#include <linux/pinctrl/pinctrl.h>
131
132struct foo_group {
133    const char *name;
134    const unsigned int *pins;
135    const unsigned num_pins;
136};
137
138static const unsigned int spi0_pins[] = { 0, 8, 16, 24 };
139static const unsigned int i2c0_pins[] = { 24, 25 };
140
141static const struct foo_group foo_groups[] = {
142    {
143        .name = "spi0_grp",
144        .pins = spi0_pins,
145        .num_pins = ARRAY_SIZE(spi0_pins),
146    },
147    {
148        .name = "i2c0_grp",
149        .pins = i2c0_pins,
150        .num_pins = ARRAY_SIZE(i2c0_pins),
151    },
152};
153
154
155static int foo_get_groups_count(struct pinctrl_dev *pctldev)
156{
157    return ARRAY_SIZE(foo_groups);
158}
159
160static const char *foo_get_group_name(struct pinctrl_dev *pctldev,
161                       unsigned selector)
162{
163    return foo_groups[selector].name;
164}
165
166static int foo_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
167                   unsigned ** const pins,
168                   unsigned * const num_pins)
169{
170    *pins = (unsigned *) foo_groups[selector].pins;
171    *num_pins = foo_groups[selector].num_pins;
172    return 0;
173}
174
175static struct pinctrl_ops foo_pctrl_ops = {
176    .get_groups_count = foo_get_groups_count,
177    .get_group_name = foo_get_group_name,
178    .get_group_pins = foo_get_group_pins,
179};
180
181
182static struct pinctrl_desc foo_desc = {
183       ...
184       .pctlops = &foo_pctrl_ops,
185};
186
187The pin control subsystem will call the .get_groups_count() function to
188determine total number of legal selectors, then it will call the other functions
189to retrieve the name and pins of the group. Maintaining the data structure of
190the groups is up to the driver, this is just a simple example - in practice you
191may need more entries in your group structure, for example specific register
192ranges associated with each group and so on.
193
194
195Pin configuration
196=================
197
198Pins can sometimes be software-configured in an various ways, mostly related
199to their electronic properties when used as inputs or outputs. For example you
200may be able to make an output pin high impedance, or "tristate" meaning it is
201effectively disconnected. You may be able to connect an input pin to VDD or GND
202using a certain resistor value - pull up and pull down - so that the pin has a
203stable value when nothing is driving the rail it is connected to, or when it's
204unconnected.
205
206Pin configuration can be programmed either using the explicit APIs described
207immediately below, or by adding configuration entries into the mapping table;
208see section "Board/machine configuration" below.
209
210For example, a platform may do the following to pull up a pin to VDD:
211
212#include <linux/pinctrl/consumer.h>
213
214ret = pin_config_set("foo-dev", "FOO_GPIO_PIN", PLATFORM_X_PULL_UP);
215
216The format and meaning of the configuration parameter, PLATFORM_X_PULL_UP
217above, is entirely defined by the pin controller driver.
218
219The pin configuration driver implements callbacks for changing pin
220configuration in the pin controller ops like this:
221
222#include <linux/pinctrl/pinctrl.h>
223#include <linux/pinctrl/pinconf.h>
224#include "platform_x_pindefs.h"
225
226static int foo_pin_config_get(struct pinctrl_dev *pctldev,
227            unsigned offset,
228            unsigned long *config)
229{
230    struct my_conftype conf;
231
232    ... Find setting for pin @ offset ...
233
234    *config = (unsigned long) conf;
235}
236
237static int foo_pin_config_set(struct pinctrl_dev *pctldev,
238            unsigned offset,
239            unsigned long config)
240{
241    struct my_conftype *conf = (struct my_conftype *) config;
242
243    switch (conf) {
244        case PLATFORM_X_PULL_UP:
245        ...
246        }
247    }
248}
249
250static int foo_pin_config_group_get (struct pinctrl_dev *pctldev,
251            unsigned selector,
252            unsigned long *config)
253{
254    ...
255}
256
257static int foo_pin_config_group_set (struct pinctrl_dev *pctldev,
258            unsigned selector,
259            unsigned long config)
260{
261    ...
262}
263
264static struct pinconf_ops foo_pconf_ops = {
265    .pin_config_get = foo_pin_config_get,
266    .pin_config_set = foo_pin_config_set,
267    .pin_config_group_get = foo_pin_config_group_get,
268    .pin_config_group_set = foo_pin_config_group_set,
269};
270
271/* Pin config operations are handled by some pin controller */
272static struct pinctrl_desc foo_desc = {
273    ...
274    .confops = &foo_pconf_ops,
275};
276
277Since some controllers have special logic for handling entire groups of pins
278they can exploit the special whole-group pin control function. The
279pin_config_group_set() callback is allowed to return the error code -EAGAIN,
280for groups it does not want to handle, or if it just wants to do some
281group-level handling and then fall through to iterate over all pins, in which
282case each individual pin will be treated by separate pin_config_set() calls as
283well.
284
285
286Interaction with the GPIO subsystem
287===================================
288
289The GPIO drivers may want to perform operations of various types on the same
290physical pins that are also registered as pin controller pins.
291
292First and foremost, the two subsystems can be used as completely orthogonal,
293see the section named "pin control requests from drivers" and
294"drivers needing both pin control and GPIOs" below for details. But in some
295situations a cross-subsystem mapping between pins and GPIOs is needed.
296
297Since the pin controller subsystem have its pinspace local to the pin
298controller we need a mapping so that the pin control subsystem can figure out
299which pin controller handles control of a certain GPIO pin. Since a single
300pin controller may be muxing several GPIO ranges (typically SoCs that have
301one set of pins but internally several GPIO silicon blocks, each modeled as
302a struct gpio_chip) any number of GPIO ranges can be added to a pin controller
303instance like this:
304
305struct gpio_chip chip_a;
306struct gpio_chip chip_b;
307
308static struct pinctrl_gpio_range gpio_range_a = {
309    .name = "chip a",
310    .id = 0,
311    .base = 32,
312    .pin_base = 32,
313    .npins = 16,
314    .gc = &chip_a;
315};
316
317static struct pinctrl_gpio_range gpio_range_b = {
318    .name = "chip b",
319    .id = 0,
320    .base = 48,
321    .pin_base = 64,
322    .npins = 8,
323    .gc = &chip_b;
324};
325
326{
327    struct pinctrl_dev *pctl;
328    ...
329    pinctrl_add_gpio_range(pctl, &gpio_range_a);
330    pinctrl_add_gpio_range(pctl, &gpio_range_b);
331}
332
333So this complex system has one pin controller handling two different
334GPIO chips. "chip a" has 16 pins and "chip b" has 8 pins. The "chip a" and
335"chip b" have different .pin_base, which means a start pin number of the
336GPIO range.
337
338The GPIO range of "chip a" starts from the GPIO base of 32 and actual
339pin range also starts from 32. However "chip b" has different starting
340offset for the GPIO range and pin range. The GPIO range of "chip b" starts
341from GPIO number 48, while the pin range of "chip b" starts from 64.
342
343We can convert a gpio number to actual pin number using this "pin_base".
344They are mapped in the global GPIO pin space at:
345
346chip a:
347 - GPIO range : [32 .. 47]
348 - pin range : [32 .. 47]
349chip b:
350 - GPIO range : [48 .. 55]
351 - pin range : [64 .. 71]
352
353When GPIO-specific functions in the pin control subsystem are called, these
354ranges will be used to look up the appropriate pin controller by inspecting
355and matching the pin to the pin ranges across all controllers. When a
356pin controller handling the matching range is found, GPIO-specific functions
357will be called on that specific pin controller.
358
359For all functionalities dealing with pin biasing, pin muxing etc, the pin
360controller subsystem will subtract the range's .base offset from the passed
361in gpio number, and add the ranges's .pin_base offset to retrive a pin number.
362After that, the subsystem passes it on to the pin control driver, so the driver
363will get an pin number into its handled number range. Further it is also passed
364the range ID value, so that the pin controller knows which range it should
365deal with.
366
367Calling pinctrl_add_gpio_range from pinctrl driver is DEPRECATED. Please see
368section 2.1 of Documentation/devicetree/bindings/gpio/gpio.txt on how to bind
369pinctrl and gpio drivers.
370
371PINMUX interfaces
372=================
373
374These calls use the pinmux_* naming prefix. No other calls should use that
375prefix.
376
377
378What is pinmuxing?
379==================
380
381PINMUX, also known as padmux, ballmux, alternate functions or mission modes
382is a way for chip vendors producing some kind of electrical packages to use
383a certain physical pin (ball, pad, finger, etc) for multiple mutually exclusive
384functions, depending on the application. By "application" in this context
385we usually mean a way of soldering or wiring the package into an electronic
386system, even though the framework makes it possible to also change the function
387at runtime.
388
389Here is an example of a PGA (Pin Grid Array) chip seen from underneath:
390
391        A B C D E F G H
392      +---+
393   8 | o | o o o o o o o
394      | |
395   7 | o | o o o o o o o
396      | |
397   6 | o | o o o o o o o
398      +---+---+
399   5 | o | o | o o o o o o
400      +---+---+ +---+
401   4 o o o o o o | o | o
402                              | |
403   3 o o o o o o | o | o
404                              | |
405   2 o o o o o o | o | o
406      +-------+-------+-------+---+---+
407   1 | o o | o o | o o | o | o |
408      +-------+-------+-------+---+---+
409
410This is not tetris. The game to think of is chess. Not all PGA/BGA packages
411are chessboard-like, big ones have "holes" in some arrangement according to
412different design patterns, but we're using this as a simple example. Of the
413pins you see some will be taken by things like a few VCC and GND to feed power
414to the chip, and quite a few will be taken by large ports like an external
415memory interface. The remaining pins will often be subject to pin multiplexing.
416
417The example 8x8 PGA package above will have pin numbers 0 thru 63 assigned to
418its physical pins. It will name the pins { A1, A2, A3 ... H6, H7, H8 } using
419pinctrl_register_pins() and a suitable data set as shown earlier.
420
421In this 8x8 BGA package the pins { A8, A7, A6, A5 } can be used as an SPI port
422(these are four pins: CLK, RXD, TXD, FRM). In that case, pin B5 can be used as
423some general-purpose GPIO pin. However, in another setting, pins { A5, B5 } can
424be used as an I2C port (these are just two pins: SCL, SDA). Needless to say,
425we cannot use the SPI port and I2C port at the same time. However in the inside
426of the package the silicon performing the SPI logic can alternatively be routed
427out on pins { G4, G3, G2, G1 }.
428
429On the botton row at { A1, B1, C1, D1, E1, F1, G1, H1 } we have something
430special - it's an external MMC bus that can be 2, 4 or 8 bits wide, and it will
431consume 2, 4 or 8 pins respectively, so either { A1, B1 } are taken or
432{ A1, B1, C1, D1 } or all of them. If we use all 8 bits, we cannot use the SPI
433port on pins { G4, G3, G2, G1 } of course.
434
435This way the silicon blocks present inside the chip can be multiplexed "muxed"
436out on different pin ranges. Often contemporary SoC (systems on chip) will
437contain several I2C, SPI, SDIO/MMC, etc silicon blocks that can be routed to
438different pins by pinmux settings.
439
440Since general-purpose I/O pins (GPIO) are typically always in shortage, it is
441common to be able to use almost any pin as a GPIO pin if it is not currently
442in use by some other I/O port.
443
444
445Pinmux conventions
446==================
447
448The purpose of the pinmux functionality in the pin controller subsystem is to
449abstract and provide pinmux settings to the devices you choose to instantiate
450in your machine configuration. It is inspired by the clk, GPIO and regulator
451subsystems, so devices will request their mux setting, but it's also possible
452to request a single pin for e.g. GPIO.
453
454Definitions:
455
456- FUNCTIONS can be switched in and out by a driver residing with the pin
457  control subsystem in the drivers/pinctrl/* directory of the kernel. The
458  pin control driver knows the possible functions. In the example above you can
459  identify three pinmux functions, one for spi, one for i2c and one for mmc.
460
461- FUNCTIONS are assumed to be enumerable from zero in a one-dimensional array.
462  In this case the array could be something like: { spi0, i2c0, mmc0 }
463  for the three available functions.
464
465- FUNCTIONS have PIN GROUPS as defined on the generic level - so a certain
466  function is *always* associated with a certain set of pin groups, could
467  be just a single one, but could also be many. In the example above the
468  function i2c is associated with the pins { A5, B5 }, enumerated as
469  { 24, 25 } in the controller pin space.
470
471  The Function spi is associated with pin groups { A8, A7, A6, A5 }
472  and { G4, G3, G2, G1 }, which are enumerated as { 0, 8, 16, 24 } and
473  { 38, 46, 54, 62 } respectively.
474
475  Group names must be unique per pin controller, no two groups on the same
476  controller may have the same name.
477
478- The combination of a FUNCTION and a PIN GROUP determine a certain function
479  for a certain set of pins. The knowledge of the functions and pin groups
480  and their machine-specific particulars are kept inside the pinmux driver,
481  from the outside only the enumerators are known, and the driver core can:
482
483  - Request the name of a function with a certain selector (>= 0)
484  - A list of groups associated with a certain function
485  - Request that a certain group in that list to be activated for a certain
486    function
487
488  As already described above, pin groups are in turn self-descriptive, so
489  the core will retrieve the actual pin range in a certain group from the
490  driver.
491
492- FUNCTIONS and GROUPS on a certain PIN CONTROLLER are MAPPED to a certain
493  device by the board file, device tree or similar machine setup configuration
494  mechanism, similar to how regulators are connected to devices, usually by
495  name. Defining a pin controller, function and group thus uniquely identify
496  the set of pins to be used by a certain device. (If only one possible group
497  of pins is available for the function, no group name need to be supplied -
498  the core will simply select the first and only group available.)
499
500  In the example case we can define that this particular machine shall
501  use device spi0 with pinmux function fspi0 group gspi0 and i2c0 on function
502  fi2c0 group gi2c0, on the primary pin controller, we get mappings
503  like these:
504
505  {
506    {"map-spi0", spi0, pinctrl0, fspi0, gspi0},
507    {"map-i2c0", i2c0, pinctrl0, fi2c0, gi2c0}
508  }
509
510  Every map must be assigned a state name, pin controller, device and
511  function. The group is not compulsory - if it is omitted the first group
512  presented by the driver as applicable for the function will be selected,
513  which is useful for simple cases.
514
515  It is possible to map several groups to the same combination of device,
516  pin controller and function. This is for cases where a certain function on
517  a certain pin controller may use different sets of pins in different
518  configurations.
519
520- PINS for a certain FUNCTION using a certain PIN GROUP on a certain
521  PIN CONTROLLER are provided on a first-come first-serve basis, so if some
522  other device mux setting or GPIO pin request has already taken your physical
523  pin, you will be denied the use of it. To get (activate) a new setting, the
524  old one has to be put (deactivated) first.
525
526Sometimes the documentation and hardware registers will be oriented around
527pads (or "fingers") rather than pins - these are the soldering surfaces on the
528silicon inside the package, and may or may not match the actual number of
529pins/balls underneath the capsule. Pick some enumeration that makes sense to
530you. Define enumerators only for the pins you can control if that makes sense.
531
532Assumptions:
533
534We assume that the number of possible function maps to pin groups is limited by
535the hardware. I.e. we assume that there is no system where any function can be
536mapped to any pin, like in a phone exchange. So the available pins groups for
537a certain function will be limited to a few choices (say up to eight or so),
538not hundreds or any amount of choices. This is the characteristic we have found
539by inspecting available pinmux hardware, and a necessary assumption since we
540expect pinmux drivers to present *all* possible function vs pin group mappings
541to the subsystem.
542
543
544Pinmux drivers
545==============
546
547The pinmux core takes care of preventing conflicts on pins and calling
548the pin controller driver to execute different settings.
549
550It is the responsibility of the pinmux driver to impose further restrictions
551(say for example infer electronic limitations due to load etc) to determine
552whether or not the requested function can actually be allowed, and in case it
553is possible to perform the requested mux setting, poke the hardware so that
554this happens.
555
556Pinmux drivers are required to supply a few callback functions, some are
557optional. Usually the enable() and disable() functions are implemented,
558writing values into some certain registers to activate a certain mux setting
559for a certain pin.
560
561A simple driver for the above example will work by setting bits 0, 1, 2, 3 or 4
562into some register named MUX to select a certain function with a certain
563group of pins would work something like this:
564
565#include <linux/pinctrl/pinctrl.h>
566#include <linux/pinctrl/pinmux.h>
567
568struct foo_group {
569    const char *name;
570    const unsigned int *pins;
571    const unsigned num_pins;
572};
573
574static const unsigned spi0_0_pins[] = { 0, 8, 16, 24 };
575static const unsigned spi0_1_pins[] = { 38, 46, 54, 62 };
576static const unsigned i2c0_pins[] = { 24, 25 };
577static const unsigned mmc0_1_pins[] = { 56, 57 };
578static const unsigned mmc0_2_pins[] = { 58, 59 };
579static const unsigned mmc0_3_pins[] = { 60, 61, 62, 63 };
580
581static const struct foo_group foo_groups[] = {
582    {
583        .name = "spi0_0_grp",
584        .pins = spi0_0_pins,
585        .num_pins = ARRAY_SIZE(spi0_0_pins),
586    },
587    {
588        .name = "spi0_1_grp",
589        .pins = spi0_1_pins,
590        .num_pins = ARRAY_SIZE(spi0_1_pins),
591    },
592    {
593        .name = "i2c0_grp",
594        .pins = i2c0_pins,
595        .num_pins = ARRAY_SIZE(i2c0_pins),
596    },
597    {
598        .name = "mmc0_1_grp",
599        .pins = mmc0_1_pins,
600        .num_pins = ARRAY_SIZE(mmc0_1_pins),
601    },
602    {
603        .name = "mmc0_2_grp",
604        .pins = mmc0_2_pins,
605        .num_pins = ARRAY_SIZE(mmc0_2_pins),
606    },
607    {
608        .name = "mmc0_3_grp",
609        .pins = mmc0_3_pins,
610        .num_pins = ARRAY_SIZE(mmc0_3_pins),
611    },
612};
613
614
615static int foo_get_groups_count(struct pinctrl_dev *pctldev)
616{
617    return ARRAY_SIZE(foo_groups);
618}
619
620static const char *foo_get_group_name(struct pinctrl_dev *pctldev,
621                       unsigned selector)
622{
623    return foo_groups[selector].name;
624}
625
626static int foo_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
627                   unsigned ** const pins,
628                   unsigned * const num_pins)
629{
630    *pins = (unsigned *) foo_groups[selector].pins;
631    *num_pins = foo_groups[selector].num_pins;
632    return 0;
633}
634
635static struct pinctrl_ops foo_pctrl_ops = {
636    .get_groups_count = foo_get_groups_count,
637    .get_group_name = foo_get_group_name,
638    .get_group_pins = foo_get_group_pins,
639};
640
641struct foo_pmx_func {
642    const char *name;
643    const char * const *groups;
644    const unsigned num_groups;
645};
646
647static const char * const spi0_groups[] = { "spi0_0_grp", "spi0_1_grp" };
648static const char * const i2c0_groups[] = { "i2c0_grp" };
649static const char * const mmc0_groups[] = { "mmc0_1_grp", "mmc0_2_grp",
650                    "mmc0_3_grp" };
651
652static const struct foo_pmx_func foo_functions[] = {
653    {
654        .name = "spi0",
655        .groups = spi0_groups,
656        .num_groups = ARRAY_SIZE(spi0_groups),
657    },
658    {
659        .name = "i2c0",
660        .groups = i2c0_groups,
661        .num_groups = ARRAY_SIZE(i2c0_groups),
662    },
663    {
664        .name = "mmc0",
665        .groups = mmc0_groups,
666        .num_groups = ARRAY_SIZE(mmc0_groups),
667    },
668};
669
670int foo_get_functions_count(struct pinctrl_dev *pctldev)
671{
672    return ARRAY_SIZE(foo_functions);
673}
674
675const char *foo_get_fname(struct pinctrl_dev *pctldev, unsigned selector)
676{
677    return foo_functions[selector].name;
678}
679
680static int foo_get_groups(struct pinctrl_dev *pctldev, unsigned selector,
681              const char * const **groups,
682              unsigned * const num_groups)
683{
684    *groups = foo_functions[selector].groups;
685    *num_groups = foo_functions[selector].num_groups;
686    return 0;
687}
688
689int foo_enable(struct pinctrl_dev *pctldev, unsigned selector,
690        unsigned group)
691{
692    u8 regbit = (1 << selector + group);
693
694    writeb((readb(MUX)|regbit), MUX)
695    return 0;
696}
697
698void foo_disable(struct pinctrl_dev *pctldev, unsigned selector,
699        unsigned group)
700{
701    u8 regbit = (1 << selector + group);
702
703    writeb((readb(MUX) & ~(regbit)), MUX)
704    return 0;
705}
706
707struct pinmux_ops foo_pmxops = {
708    .get_functions_count = foo_get_functions_count,
709    .get_function_name = foo_get_fname,
710    .get_function_groups = foo_get_groups,
711    .enable = foo_enable,
712    .disable = foo_disable,
713};
714
715/* Pinmux operations are handled by some pin controller */
716static struct pinctrl_desc foo_desc = {
717    ...
718    .pctlops = &foo_pctrl_ops,
719    .pmxops = &foo_pmxops,
720};
721
722In the example activating muxing 0 and 1 at the same time setting bits
7230 and 1, uses one pin in common so they would collide.
724
725The beauty of the pinmux subsystem is that since it keeps track of all
726pins and who is using them, it will already have denied an impossible
727request like that, so the driver does not need to worry about such
728things - when it gets a selector passed in, the pinmux subsystem makes
729sure no other device or GPIO assignment is already using the selected
730pins. Thus bits 0 and 1 in the control register will never be set at the
731same time.
732
733All the above functions are mandatory to implement for a pinmux driver.
734
735
736Pin control interaction with the GPIO subsystem
737===============================================
738
739The public pinmux API contains two functions named pinctrl_request_gpio()
740and pinctrl_free_gpio(). These two functions shall *ONLY* be called from
741gpiolib-based drivers as part of their gpio_request() and
742gpio_free() semantics. Likewise the pinctrl_gpio_direction_[input|output]
743shall only be called from within respective gpio_direction_[input|output]
744gpiolib implementation.
745
746NOTE that platforms and individual drivers shall *NOT* request GPIO pins to be
747controlled e.g. muxed in. Instead, implement a proper gpiolib driver and have
748that driver request proper muxing and other control for its pins.
749
750The function list could become long, especially if you can convert every
751individual pin into a GPIO pin independent of any other pins, and then try
752the approach to define every pin as a function.
753
754In this case, the function array would become 64 entries for each GPIO
755setting and then the device functions.
756
757For this reason there are two functions a pin control driver can implement
758to enable only GPIO on an individual pin: .gpio_request_enable() and
759.gpio_disable_free().
760
761This function will pass in the affected GPIO range identified by the pin
762controller core, so you know which GPIO pins are being affected by the request
763operation.
764
765If your driver needs to have an indication from the framework of whether the
766GPIO pin shall be used for input or output you can implement the
767.gpio_set_direction() function. As described this shall be called from the
768gpiolib driver and the affected GPIO range, pin offset and desired direction
769will be passed along to this function.
770
771Alternatively to using these special functions, it is fully allowed to use
772named functions for each GPIO pin, the pinctrl_request_gpio() will attempt to
773obtain the function "gpioN" where "N" is the global GPIO pin number if no
774special GPIO-handler is registered.
775
776
777Board/machine configuration
778==================================
779
780Boards and machines define how a certain complete running system is put
781together, including how GPIOs and devices are muxed, how regulators are
782constrained and how the clock tree looks. Of course pinmux settings are also
783part of this.
784
785A pin controller configuration for a machine looks pretty much like a simple
786regulator configuration, so for the example array above we want to enable i2c
787and spi on the second function mapping:
788
789#include <linux/pinctrl/machine.h>
790
791static const struct pinctrl_map mapping[] __initconst = {
792    {
793        .dev_name = "foo-spi.0",
794        .name = PINCTRL_STATE_DEFAULT,
795        .type = PIN_MAP_TYPE_MUX_GROUP,
796        .ctrl_dev_name = "pinctrl-foo",
797        .data.mux.function = "spi0",
798    },
799    {
800        .dev_name = "foo-i2c.0",
801        .name = PINCTRL_STATE_DEFAULT,
802        .type = PIN_MAP_TYPE_MUX_GROUP,
803        .ctrl_dev_name = "pinctrl-foo",
804        .data.mux.function = "i2c0",
805    },
806    {
807        .dev_name = "foo-mmc.0",
808        .name = PINCTRL_STATE_DEFAULT,
809        .type = PIN_MAP_TYPE_MUX_GROUP,
810        .ctrl_dev_name = "pinctrl-foo",
811        .data.mux.function = "mmc0",
812    },
813};
814
815The dev_name here matches to the unique device name that can be used to look
816up the device struct (just like with clockdev or regulators). The function name
817must match a function provided by the pinmux driver handling this pin range.
818
819As you can see we may have several pin controllers on the system and thus
820we need to specify which one of them that contain the functions we wish
821to map.
822
823You register this pinmux mapping to the pinmux subsystem by simply:
824
825       ret = pinctrl_register_mappings(mapping, ARRAY_SIZE(mapping));
826
827Since the above construct is pretty common there is a helper macro to make
828it even more compact which assumes you want to use pinctrl-foo and position
8290 for mapping, for example:
830
831static struct pinctrl_map __initdata mapping[] = {
832    PIN_MAP_MUX_GROUP("foo-i2c.o", PINCTRL_STATE_DEFAULT, "pinctrl-foo", NULL, "i2c0"),
833};
834
835The mapping table may also contain pin configuration entries. It's common for
836each pin/group to have a number of configuration entries that affect it, so
837the table entries for configuration reference an array of config parameters
838and values. An example using the convenience macros is shown below:
839
840static unsigned long i2c_grp_configs[] = {
841    FOO_PIN_DRIVEN,
842    FOO_PIN_PULLUP,
843};
844
845static unsigned long i2c_pin_configs[] = {
846    FOO_OPEN_COLLECTOR,
847    FOO_SLEW_RATE_SLOW,
848};
849
850static struct pinctrl_map __initdata mapping[] = {
851    PIN_MAP_MUX_GROUP("foo-i2c.0", PINCTRL_STATE_DEFAULT, "pinctrl-foo", "i2c0", "i2c0"),
852    PIN_MAP_CONFIGS_GROUP("foo-i2c.0", PINCTRL_STATE_DEFAULT, "pinctrl-foo", "i2c0", i2c_grp_configs),
853    PIN_MAP_CONFIGS_PIN("foo-i2c.0", PINCTRL_STATE_DEFAULT, "pinctrl-foo", "i2c0scl", i2c_pin_configs),
854    PIN_MAP_CONFIGS_PIN("foo-i2c.0", PINCTRL_STATE_DEFAULT, "pinctrl-foo", "i2c0sda", i2c_pin_configs),
855};
856
857Finally, some devices expect the mapping table to contain certain specific
858named states. When running on hardware that doesn't need any pin controller
859configuration, the mapping table must still contain those named states, in
860order to explicitly indicate that the states were provided and intended to
861be empty. Table entry macro PIN_MAP_DUMMY_STATE serves the purpose of defining
862a named state without causing any pin controller to be programmed:
863
864static struct pinctrl_map __initdata mapping[] = {
865    PIN_MAP_DUMMY_STATE("foo-i2c.0", PINCTRL_STATE_DEFAULT),
866};
867
868
869Complex mappings
870================
871
872As it is possible to map a function to different groups of pins an optional
873.group can be specified like this:
874
875...
876{
877    .dev_name = "foo-spi.0",
878    .name = "spi0-pos-A",
879    .type = PIN_MAP_TYPE_MUX_GROUP,
880    .ctrl_dev_name = "pinctrl-foo",
881    .function = "spi0",
882    .group = "spi0_0_grp",
883},
884{
885    .dev_name = "foo-spi.0",
886    .name = "spi0-pos-B",
887    .type = PIN_MAP_TYPE_MUX_GROUP,
888    .ctrl_dev_name = "pinctrl-foo",
889    .function = "spi0",
890    .group = "spi0_1_grp",
891},
892...
893
894This example mapping is used to switch between two positions for spi0 at
895runtime, as described further below under the heading "Runtime pinmuxing".
896
897Further it is possible for one named state to affect the muxing of several
898groups of pins, say for example in the mmc0 example above, where you can
899additively expand the mmc0 bus from 2 to 4 to 8 pins. If we want to use all
900three groups for a total of 2+2+4 = 8 pins (for an 8-bit MMC bus as is the
901case), we define a mapping like this:
902
903...
904{
905    .dev_name = "foo-mmc.0",
906    .name = "2bit"
907    .type = PIN_MAP_TYPE_MUX_GROUP,
908    .ctrl_dev_name = "pinctrl-foo",
909    .function = "mmc0",
910    .group = "mmc0_1_grp",
911},
912{
913    .dev_name = "foo-mmc.0",
914    .name = "4bit"
915    .type = PIN_MAP_TYPE_MUX_GROUP,
916    .ctrl_dev_name = "pinctrl-foo",
917    .function = "mmc0",
918    .group = "mmc0_1_grp",
919},
920{
921    .dev_name = "foo-mmc.0",
922    .name = "4bit"
923    .type = PIN_MAP_TYPE_MUX_GROUP,
924    .ctrl_dev_name = "pinctrl-foo",
925    .function = "mmc0",
926    .group = "mmc0_2_grp",
927},
928{
929    .dev_name = "foo-mmc.0",
930    .name = "8bit"
931    .type = PIN_MAP_TYPE_MUX_GROUP,
932    .ctrl_dev_name = "pinctrl-foo",
933    .function = "mmc0",
934    .group = "mmc0_1_grp",
935},
936{
937    .dev_name = "foo-mmc.0",
938    .name = "8bit"
939    .type = PIN_MAP_TYPE_MUX_GROUP,
940    .ctrl_dev_name = "pinctrl-foo",
941    .function = "mmc0",
942    .group = "mmc0_2_grp",
943},
944{
945    .dev_name = "foo-mmc.0",
946    .name = "8bit"
947    .type = PIN_MAP_TYPE_MUX_GROUP,
948    .ctrl_dev_name = "pinctrl-foo",
949    .function = "mmc0",
950    .group = "mmc0_3_grp",
951},
952...
953
954The result of grabbing this mapping from the device with something like
955this (see next paragraph):
956
957    p = devm_pinctrl_get(dev);
958    s = pinctrl_lookup_state(p, "8bit");
959    ret = pinctrl_select_state(p, s);
960
961or more simply:
962
963    p = devm_pinctrl_get_select(dev, "8bit");
964
965Will be that you activate all the three bottom records in the mapping at
966once. Since they share the same name, pin controller device, function and
967device, and since we allow multiple groups to match to a single device, they
968all get selected, and they all get enabled and disable simultaneously by the
969pinmux core.
970
971
972Pin control requests from drivers
973=================================
974
975When a device driver is about to probe the device core will automatically
976attempt to issue pinctrl_get_select_default() on these devices.
977This way driver writers do not need to add any of the boilerplate code
978of the type found below. However when doing fine-grained state selection
979and not using the "default" state, you may have to do some device driver
980handling of the pinctrl handles and states.
981
982So if you just want to put the pins for a certain device into the default
983state and be done with it, there is nothing you need to do besides
984providing the proper mapping table. The device core will take care of
985the rest.
986
987Generally it is discouraged to let individual drivers get and enable pin
988control. So if possible, handle the pin control in platform code or some other
989place where you have access to all the affected struct device * pointers. In
990some cases where a driver needs to e.g. switch between different mux mappings
991at runtime this is not possible.
992
993A typical case is if a driver needs to switch bias of pins from normal
994operation and going to sleep, moving from the PINCTRL_STATE_DEFAULT to
995PINCTRL_STATE_SLEEP at runtime, re-biasing or even re-muxing pins to save
996current in sleep mode.
997
998A driver may request a certain control state to be activated, usually just the
999default state like this:
1000
1001#include <linux/pinctrl/consumer.h>
1002
1003struct foo_state {
1004       struct pinctrl *p;
1005       struct pinctrl_state *s;
1006       ...
1007};
1008
1009foo_probe()
1010{
1011    /* Allocate a state holder named "foo" etc */
1012    struct foo_state *foo = ...;
1013
1014    foo->p = devm_pinctrl_get(&device);
1015    if (IS_ERR(foo->p)) {
1016        /* FIXME: clean up "foo" here */
1017        return PTR_ERR(foo->p);
1018    }
1019
1020    foo->s = pinctrl_lookup_state(foo->p, PINCTRL_STATE_DEFAULT);
1021    if (IS_ERR(foo->s)) {
1022        /* FIXME: clean up "foo" here */
1023        return PTR_ERR(s);
1024    }
1025
1026    ret = pinctrl_select_state(foo->s);
1027    if (ret < 0) {
1028        /* FIXME: clean up "foo" here */
1029        return ret;
1030    }
1031}
1032
1033This get/lookup/select/put sequence can just as well be handled by bus drivers
1034if you don't want each and every driver to handle it and you know the
1035arrangement on your bus.
1036
1037The semantics of the pinctrl APIs are:
1038
1039- pinctrl_get() is called in process context to obtain a handle to all pinctrl
1040  information for a given client device. It will allocate a struct from the
1041  kernel memory to hold the pinmux state. All mapping table parsing or similar
1042  slow operations take place within this API.
1043
1044- devm_pinctrl_get() is a variant of pinctrl_get() that causes pinctrl_put()
1045  to be called automatically on the retrieved pointer when the associated
1046  device is removed. It is recommended to use this function over plain
1047  pinctrl_get().
1048
1049- pinctrl_lookup_state() is called in process context to obtain a handle to a
1050  specific state for a the client device. This operation may be slow too.
1051
1052- pinctrl_select_state() programs pin controller hardware according to the
1053  definition of the state as given by the mapping table. In theory this is a
1054  fast-path operation, since it only involved blasting some register settings
1055  into hardware. However, note that some pin controllers may have their
1056  registers on a slow/IRQ-based bus, so client devices should not assume they
1057  can call pinctrl_select_state() from non-blocking contexts.
1058
1059- pinctrl_put() frees all information associated with a pinctrl handle.
1060
1061- devm_pinctrl_put() is a variant of pinctrl_put() that may be used to
1062  explicitly destroy a pinctrl object returned by devm_pinctrl_get().
1063  However, use of this function will be rare, due to the automatic cleanup
1064  that will occur even without calling it.
1065
1066  pinctrl_get() must be paired with a plain pinctrl_put().
1067  pinctrl_get() may not be paired with devm_pinctrl_put().
1068  devm_pinctrl_get() can optionally be paired with devm_pinctrl_put().
1069  devm_pinctrl_get() may not be paired with plain pinctrl_put().
1070
1071Usually the pin control core handled the get/put pair and call out to the
1072device drivers bookkeeping operations, like checking available functions and
1073the associated pins, whereas the enable/disable pass on to the pin controller
1074driver which takes care of activating and/or deactivating the mux setting by
1075quickly poking some registers.
1076
1077The pins are allocated for your device when you issue the devm_pinctrl_get()
1078call, after this you should be able to see this in the debugfs listing of all
1079pins.
1080
1081NOTE: the pinctrl system will return -EPROBE_DEFER if it cannot find the
1082requested pinctrl handles, for example if the pinctrl driver has not yet
1083registered. Thus make sure that the error path in your driver gracefully
1084cleans up and is ready to retry the probing later in the startup process.
1085
1086
1087Drivers needing both pin control and GPIOs
1088==========================================
1089
1090Again, it is discouraged to let drivers lookup and select pin control states
1091themselves, but again sometimes this is unavoidable.
1092
1093So say that your driver is fetching its resources like this:
1094
1095#include <linux/pinctrl/consumer.h>
1096#include <linux/gpio.h>
1097
1098struct pinctrl *pinctrl;
1099int gpio;
1100
1101pinctrl = devm_pinctrl_get_select_default(&dev);
1102gpio = devm_gpio_request(&dev, 14, "foo");
1103
1104Here we first request a certain pin state and then request GPIO 14 to be
1105used. If you're using the subsystems orthogonally like this, you should
1106nominally always get your pinctrl handle and select the desired pinctrl
1107state BEFORE requesting the GPIO. This is a semantic convention to avoid
1108situations that can be electrically unpleasant, you will certainly want to
1109mux in and bias pins in a certain way before the GPIO subsystems starts to
1110deal with them.
1111
1112The above can be hidden: using the device core, the pinctrl core may be
1113setting up the config and muxing for the pins right before the device is
1114probing, nevertheless orthogonal to the GPIO subsystem.
1115
1116But there are also situations where it makes sense for the GPIO subsystem
1117to communicate directly with with the pinctrl subsystem, using the latter
1118as a back-end. This is when the GPIO driver may call out to the functions
1119described in the section "Pin control interaction with the GPIO subsystem"
1120above. This only involves per-pin multiplexing, and will be completely
1121hidden behind the gpio_*() function namespace. In this case, the driver
1122need not interact with the pin control subsystem at all.
1123
1124If a pin control driver and a GPIO driver is dealing with the same pins
1125and the use cases involve multiplexing, you MUST implement the pin controller
1126as a back-end for the GPIO driver like this, unless your hardware design
1127is such that the GPIO controller can override the pin controller's
1128multiplexing state through hardware without the need to interact with the
1129pin control system.
1130
1131
1132System pin control hogging
1133==========================
1134
1135Pin control map entries can be hogged by the core when the pin controller
1136is registered. This means that the core will attempt to call pinctrl_get(),
1137lookup_state() and select_state() on it immediately after the pin control
1138device has been registered.
1139
1140This occurs for mapping table entries where the client device name is equal
1141to the pin controller device name, and the state name is PINCTRL_STATE_DEFAULT.
1142
1143{
1144    .dev_name = "pinctrl-foo",
1145    .name = PINCTRL_STATE_DEFAULT,
1146    .type = PIN_MAP_TYPE_MUX_GROUP,
1147    .ctrl_dev_name = "pinctrl-foo",
1148    .function = "power_func",
1149},
1150
1151Since it may be common to request the core to hog a few always-applicable
1152mux settings on the primary pin controller, there is a convenience macro for
1153this:
1154
1155PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-foo", NULL /* group */, "power_func")
1156
1157This gives the exact same result as the above construction.
1158
1159
1160Runtime pinmuxing
1161=================
1162
1163It is possible to mux a certain function in and out at runtime, say to move
1164an SPI port from one set of pins to another set of pins. Say for example for
1165spi0 in the example above, we expose two different groups of pins for the same
1166function, but with different named in the mapping as described under
1167"Advanced mapping" above. So that for an SPI device, we have two states named
1168"pos-A" and "pos-B".
1169
1170This snippet first muxes the function in the pins defined by group A, enables
1171it, disables and releases it, and muxes it in on the pins defined by group B:
1172
1173#include <linux/pinctrl/consumer.h>
1174
1175struct pinctrl *p;
1176struct pinctrl_state *s1, *s2;
1177
1178foo_probe()
1179{
1180    /* Setup */
1181    p = devm_pinctrl_get(&device);
1182    if (IS_ERR(p))
1183        ...
1184
1185    s1 = pinctrl_lookup_state(foo->p, "pos-A");
1186    if (IS_ERR(s1))
1187        ...
1188
1189    s2 = pinctrl_lookup_state(foo->p, "pos-B");
1190    if (IS_ERR(s2))
1191        ...
1192}
1193
1194foo_switch()
1195{
1196    /* Enable on position A */
1197    ret = pinctrl_select_state(s1);
1198    if (ret < 0)
1199        ...
1200
1201    ...
1202
1203    /* Enable on position B */
1204    ret = pinctrl_select_state(s2);
1205    if (ret < 0)
1206        ...
1207
1208    ...
1209}
1210
1211The above has to be done from process context. The reservation of the pins
1212will be done when the state is activated, so in effect one specific pin
1213can be used by different functions at different times on a running system.
1214

Archive Download this file



interactive