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1 | /* |
2 | * sata_svw.c - ServerWorks / Apple K2 SATA |
3 | * |
4 | * Maintained by: Benjamin Herrenschmidt <benh@kernel.crashing.org> and |
5 | * Jeff Garzik <jgarzik@pobox.com> |
6 | * Please ALWAYS copy linux-ide@vger.kernel.org |
7 | * on emails. |
8 | * |
9 | * Copyright 2003 Benjamin Herrenschmidt <benh@kernel.crashing.org> |
10 | * |
11 | * Bits from Jeff Garzik, Copyright RedHat, Inc. |
12 | * |
13 | * This driver probably works with non-Apple versions of the |
14 | * Broadcom chipset... |
15 | * |
16 | * |
17 | * This program is free software; you can redistribute it and/or modify |
18 | * it under the terms of the GNU General Public License as published by |
19 | * the Free Software Foundation; either version 2, or (at your option) |
20 | * any later version. |
21 | * |
22 | * This program is distributed in the hope that it will be useful, |
23 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
24 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
25 | * GNU General Public License for more details. |
26 | * |
27 | * You should have received a copy of the GNU General Public License |
28 | * along with this program; see the file COPYING. If not, write to |
29 | * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. |
30 | * |
31 | * |
32 | * libata documentation is available via 'make {ps|pdf}docs', |
33 | * as Documentation/DocBook/libata.* |
34 | * |
35 | * Hardware documentation available under NDA. |
36 | * |
37 | */ |
38 | |
39 | #include <linux/kernel.h> |
40 | #include <linux/module.h> |
41 | #include <linux/pci.h> |
42 | #include <linux/init.h> |
43 | #include <linux/blkdev.h> |
44 | #include <linux/delay.h> |
45 | #include <linux/interrupt.h> |
46 | #include <linux/device.h> |
47 | #include <scsi/scsi_host.h> |
48 | #include <scsi/scsi_cmnd.h> |
49 | #include <scsi/scsi.h> |
50 | #include <linux/libata.h> |
51 | |
52 | #ifdef CONFIG_PPC_OF |
53 | #include <asm/prom.h> |
54 | #include <asm/pci-bridge.h> |
55 | #endif /* CONFIG_PPC_OF */ |
56 | |
57 | #define DRV_NAME "sata_svw" |
58 | #define DRV_VERSION "2.3" |
59 | |
60 | enum { |
61 | /* ap->flags bits */ |
62 | K2_FLAG_SATA_8_PORTS = (1 << 24), |
63 | K2_FLAG_NO_ATAPI_DMA = (1 << 25), |
64 | K2_FLAG_BAR_POS_3 = (1 << 26), |
65 | |
66 | /* Taskfile registers offsets */ |
67 | K2_SATA_TF_CMD_OFFSET = 0x00, |
68 | K2_SATA_TF_DATA_OFFSET = 0x00, |
69 | K2_SATA_TF_ERROR_OFFSET = 0x04, |
70 | K2_SATA_TF_NSECT_OFFSET = 0x08, |
71 | K2_SATA_TF_LBAL_OFFSET = 0x0c, |
72 | K2_SATA_TF_LBAM_OFFSET = 0x10, |
73 | K2_SATA_TF_LBAH_OFFSET = 0x14, |
74 | K2_SATA_TF_DEVICE_OFFSET = 0x18, |
75 | K2_SATA_TF_CMDSTAT_OFFSET = 0x1c, |
76 | K2_SATA_TF_CTL_OFFSET = 0x20, |
77 | |
78 | /* DMA base */ |
79 | K2_SATA_DMA_CMD_OFFSET = 0x30, |
80 | |
81 | /* SCRs base */ |
82 | K2_SATA_SCR_STATUS_OFFSET = 0x40, |
83 | K2_SATA_SCR_ERROR_OFFSET = 0x44, |
84 | K2_SATA_SCR_CONTROL_OFFSET = 0x48, |
85 | |
86 | /* Others */ |
87 | K2_SATA_SICR1_OFFSET = 0x80, |
88 | K2_SATA_SICR2_OFFSET = 0x84, |
89 | K2_SATA_SIM_OFFSET = 0x88, |
90 | |
91 | /* Port stride */ |
92 | K2_SATA_PORT_OFFSET = 0x100, |
93 | |
94 | chip_svw4 = 0, |
95 | chip_svw8 = 1, |
96 | chip_svw42 = 2, /* bar 3 */ |
97 | chip_svw43 = 3, /* bar 5 */ |
98 | }; |
99 | |
100 | static u8 k2_stat_check_status(struct ata_port *ap); |
101 | |
102 | |
103 | static int k2_sata_check_atapi_dma(struct ata_queued_cmd *qc) |
104 | { |
105 | u8 cmnd = qc->scsicmd->cmnd[0]; |
106 | |
107 | if (qc->ap->flags & K2_FLAG_NO_ATAPI_DMA) |
108 | return -1; /* ATAPI DMA not supported */ |
109 | else { |
110 | switch (cmnd) { |
111 | case READ_10: |
112 | case READ_12: |
113 | case READ_16: |
114 | case WRITE_10: |
115 | case WRITE_12: |
116 | case WRITE_16: |
117 | return 0; |
118 | |
119 | default: |
120 | return -1; |
121 | } |
122 | |
123 | } |
124 | } |
125 | |
126 | static int k2_sata_scr_read(struct ata_link *link, |
127 | unsigned int sc_reg, u32 *val) |
128 | { |
129 | if (sc_reg > SCR_CONTROL) |
130 | return -EINVAL; |
131 | *val = readl(link->ap->ioaddr.scr_addr + (sc_reg * 4)); |
132 | return 0; |
133 | } |
134 | |
135 | |
136 | static int k2_sata_scr_write(struct ata_link *link, |
137 | unsigned int sc_reg, u32 val) |
138 | { |
139 | if (sc_reg > SCR_CONTROL) |
140 | return -EINVAL; |
141 | writel(val, link->ap->ioaddr.scr_addr + (sc_reg * 4)); |
142 | return 0; |
143 | } |
144 | |
145 | static int k2_sata_softreset(struct ata_link *link, |
146 | unsigned int *class, unsigned long deadline) |
147 | { |
148 | u8 dmactl; |
149 | void __iomem *mmio = link->ap->ioaddr.bmdma_addr; |
150 | |
151 | dmactl = readb(mmio + ATA_DMA_CMD); |
152 | |
153 | /* Clear the start bit */ |
154 | if (dmactl & ATA_DMA_START) { |
155 | dmactl &= ~ATA_DMA_START; |
156 | writeb(dmactl, mmio + ATA_DMA_CMD); |
157 | } |
158 | |
159 | return ata_sff_softreset(link, class, deadline); |
160 | } |
161 | |
162 | static int k2_sata_hardreset(struct ata_link *link, |
163 | unsigned int *class, unsigned long deadline) |
164 | { |
165 | u8 dmactl; |
166 | void __iomem *mmio = link->ap->ioaddr.bmdma_addr; |
167 | |
168 | dmactl = readb(mmio + ATA_DMA_CMD); |
169 | |
170 | /* Clear the start bit */ |
171 | if (dmactl & ATA_DMA_START) { |
172 | dmactl &= ~ATA_DMA_START; |
173 | writeb(dmactl, mmio + ATA_DMA_CMD); |
174 | } |
175 | |
176 | return sata_sff_hardreset(link, class, deadline); |
177 | } |
178 | |
179 | static void k2_sata_tf_load(struct ata_port *ap, const struct ata_taskfile *tf) |
180 | { |
181 | struct ata_ioports *ioaddr = &ap->ioaddr; |
182 | unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR; |
183 | |
184 | if (tf->ctl != ap->last_ctl) { |
185 | writeb(tf->ctl, ioaddr->ctl_addr); |
186 | ap->last_ctl = tf->ctl; |
187 | ata_wait_idle(ap); |
188 | } |
189 | if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) { |
190 | writew(tf->feature | (((u16)tf->hob_feature) << 8), |
191 | ioaddr->feature_addr); |
192 | writew(tf->nsect | (((u16)tf->hob_nsect) << 8), |
193 | ioaddr->nsect_addr); |
194 | writew(tf->lbal | (((u16)tf->hob_lbal) << 8), |
195 | ioaddr->lbal_addr); |
196 | writew(tf->lbam | (((u16)tf->hob_lbam) << 8), |
197 | ioaddr->lbam_addr); |
198 | writew(tf->lbah | (((u16)tf->hob_lbah) << 8), |
199 | ioaddr->lbah_addr); |
200 | } else if (is_addr) { |
201 | writew(tf->feature, ioaddr->feature_addr); |
202 | writew(tf->nsect, ioaddr->nsect_addr); |
203 | writew(tf->lbal, ioaddr->lbal_addr); |
204 | writew(tf->lbam, ioaddr->lbam_addr); |
205 | writew(tf->lbah, ioaddr->lbah_addr); |
206 | } |
207 | |
208 | if (tf->flags & ATA_TFLAG_DEVICE) |
209 | writeb(tf->device, ioaddr->device_addr); |
210 | |
211 | ata_wait_idle(ap); |
212 | } |
213 | |
214 | |
215 | static void k2_sata_tf_read(struct ata_port *ap, struct ata_taskfile *tf) |
216 | { |
217 | struct ata_ioports *ioaddr = &ap->ioaddr; |
218 | u16 nsect, lbal, lbam, lbah, feature; |
219 | |
220 | tf->command = k2_stat_check_status(ap); |
221 | tf->device = readw(ioaddr->device_addr); |
222 | feature = readw(ioaddr->error_addr); |
223 | nsect = readw(ioaddr->nsect_addr); |
224 | lbal = readw(ioaddr->lbal_addr); |
225 | lbam = readw(ioaddr->lbam_addr); |
226 | lbah = readw(ioaddr->lbah_addr); |
227 | |
228 | tf->feature = feature; |
229 | tf->nsect = nsect; |
230 | tf->lbal = lbal; |
231 | tf->lbam = lbam; |
232 | tf->lbah = lbah; |
233 | |
234 | if (tf->flags & ATA_TFLAG_LBA48) { |
235 | tf->hob_feature = feature >> 8; |
236 | tf->hob_nsect = nsect >> 8; |
237 | tf->hob_lbal = lbal >> 8; |
238 | tf->hob_lbam = lbam >> 8; |
239 | tf->hob_lbah = lbah >> 8; |
240 | } |
241 | } |
242 | |
243 | /** |
244 | * k2_bmdma_setup_mmio - Set up PCI IDE BMDMA transaction (MMIO) |
245 | * @qc: Info associated with this ATA transaction. |
246 | * |
247 | * LOCKING: |
248 | * spin_lock_irqsave(host lock) |
249 | */ |
250 | |
251 | static void k2_bmdma_setup_mmio(struct ata_queued_cmd *qc) |
252 | { |
253 | struct ata_port *ap = qc->ap; |
254 | unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE); |
255 | u8 dmactl; |
256 | void __iomem *mmio = ap->ioaddr.bmdma_addr; |
257 | |
258 | /* load PRD table addr. */ |
259 | mb(); /* make sure PRD table writes are visible to controller */ |
260 | writel(ap->bmdma_prd_dma, mmio + ATA_DMA_TABLE_OFS); |
261 | |
262 | /* specify data direction, triple-check start bit is clear */ |
263 | dmactl = readb(mmio + ATA_DMA_CMD); |
264 | dmactl &= ~(ATA_DMA_WR | ATA_DMA_START); |
265 | if (!rw) |
266 | dmactl |= ATA_DMA_WR; |
267 | writeb(dmactl, mmio + ATA_DMA_CMD); |
268 | |
269 | /* issue r/w command if this is not a ATA DMA command*/ |
270 | if (qc->tf.protocol != ATA_PROT_DMA) |
271 | ap->ops->sff_exec_command(ap, &qc->tf); |
272 | } |
273 | |
274 | /** |
275 | * k2_bmdma_start_mmio - Start a PCI IDE BMDMA transaction (MMIO) |
276 | * @qc: Info associated with this ATA transaction. |
277 | * |
278 | * LOCKING: |
279 | * spin_lock_irqsave(host lock) |
280 | */ |
281 | |
282 | static void k2_bmdma_start_mmio(struct ata_queued_cmd *qc) |
283 | { |
284 | struct ata_port *ap = qc->ap; |
285 | void __iomem *mmio = ap->ioaddr.bmdma_addr; |
286 | u8 dmactl; |
287 | |
288 | /* start host DMA transaction */ |
289 | dmactl = readb(mmio + ATA_DMA_CMD); |
290 | writeb(dmactl | ATA_DMA_START, mmio + ATA_DMA_CMD); |
291 | /* This works around possible data corruption. |
292 | |
293 | On certain SATA controllers that can be seen when the r/w |
294 | command is given to the controller before the host DMA is |
295 | started. |
296 | |
297 | On a Read command, the controller would initiate the |
298 | command to the drive even before it sees the DMA |
299 | start. When there are very fast drives connected to the |
300 | controller, or when the data request hits in the drive |
301 | cache, there is the possibility that the drive returns a |
302 | part or all of the requested data to the controller before |
303 | the DMA start is issued. In this case, the controller |
304 | would become confused as to what to do with the data. In |
305 | the worst case when all the data is returned back to the |
306 | controller, the controller could hang. In other cases it |
307 | could return partial data returning in data |
308 | corruption. This problem has been seen in PPC systems and |
309 | can also appear on an system with very fast disks, where |
310 | the SATA controller is sitting behind a number of bridges, |
311 | and hence there is significant latency between the r/w |
312 | command and the start command. */ |
313 | /* issue r/w command if the access is to ATA */ |
314 | if (qc->tf.protocol == ATA_PROT_DMA) |
315 | ap->ops->sff_exec_command(ap, &qc->tf); |
316 | } |
317 | |
318 | |
319 | static u8 k2_stat_check_status(struct ata_port *ap) |
320 | { |
321 | return readl(ap->ioaddr.status_addr); |
322 | } |
323 | |
324 | #ifdef CONFIG_PPC_OF |
325 | /* |
326 | * k2_sata_proc_info |
327 | * inout : decides on the direction of the dataflow and the meaning of the |
328 | * variables |
329 | * buffer: If inout==FALSE data is being written to it else read from it |
330 | * *start: If inout==FALSE start of the valid data in the buffer |
331 | * offset: If inout==FALSE offset from the beginning of the imaginary file |
332 | * from which we start writing into the buffer |
333 | * length: If inout==FALSE max number of bytes to be written into the buffer |
334 | * else number of bytes in the buffer |
335 | */ |
336 | static int k2_sata_proc_info(struct Scsi_Host *shost, char *page, char **start, |
337 | off_t offset, int count, int inout) |
338 | { |
339 | struct ata_port *ap; |
340 | struct device_node *np; |
341 | int len, index; |
342 | |
343 | /* Find the ata_port */ |
344 | ap = ata_shost_to_port(shost); |
345 | if (ap == NULL) |
346 | return 0; |
347 | |
348 | /* Find the OF node for the PCI device proper */ |
349 | np = pci_device_to_OF_node(to_pci_dev(ap->host->dev)); |
350 | if (np == NULL) |
351 | return 0; |
352 | |
353 | /* Match it to a port node */ |
354 | index = (ap == ap->host->ports[0]) ? 0 : 1; |
355 | for (np = np->child; np != NULL; np = np->sibling) { |
356 | const u32 *reg = of_get_property(np, "reg", NULL); |
357 | if (!reg) |
358 | continue; |
359 | if (index == *reg) |
360 | break; |
361 | } |
362 | if (np == NULL) |
363 | return 0; |
364 | |
365 | len = sprintf(page, "devspec: %s\n", np->full_name); |
366 | |
367 | return len; |
368 | } |
369 | #endif /* CONFIG_PPC_OF */ |
370 | |
371 | |
372 | static struct scsi_host_template k2_sata_sht = { |
373 | ATA_BMDMA_SHT(DRV_NAME), |
374 | #ifdef CONFIG_PPC_OF |
375 | .proc_info = k2_sata_proc_info, |
376 | #endif |
377 | }; |
378 | |
379 | |
380 | static struct ata_port_operations k2_sata_ops = { |
381 | .inherits = &ata_bmdma_port_ops, |
382 | .softreset = k2_sata_softreset, |
383 | .hardreset = k2_sata_hardreset, |
384 | .sff_tf_load = k2_sata_tf_load, |
385 | .sff_tf_read = k2_sata_tf_read, |
386 | .sff_check_status = k2_stat_check_status, |
387 | .check_atapi_dma = k2_sata_check_atapi_dma, |
388 | .bmdma_setup = k2_bmdma_setup_mmio, |
389 | .bmdma_start = k2_bmdma_start_mmio, |
390 | .scr_read = k2_sata_scr_read, |
391 | .scr_write = k2_sata_scr_write, |
392 | }; |
393 | |
394 | static const struct ata_port_info k2_port_info[] = { |
395 | /* chip_svw4 */ |
396 | { |
397 | .flags = ATA_FLAG_SATA | K2_FLAG_NO_ATAPI_DMA, |
398 | .pio_mask = ATA_PIO4, |
399 | .mwdma_mask = ATA_MWDMA2, |
400 | .udma_mask = ATA_UDMA6, |
401 | .port_ops = &k2_sata_ops, |
402 | }, |
403 | /* chip_svw8 */ |
404 | { |
405 | .flags = ATA_FLAG_SATA | K2_FLAG_NO_ATAPI_DMA | |
406 | K2_FLAG_SATA_8_PORTS, |
407 | .pio_mask = ATA_PIO4, |
408 | .mwdma_mask = ATA_MWDMA2, |
409 | .udma_mask = ATA_UDMA6, |
410 | .port_ops = &k2_sata_ops, |
411 | }, |
412 | /* chip_svw42 */ |
413 | { |
414 | .flags = ATA_FLAG_SATA | K2_FLAG_BAR_POS_3, |
415 | .pio_mask = ATA_PIO4, |
416 | .mwdma_mask = ATA_MWDMA2, |
417 | .udma_mask = ATA_UDMA6, |
418 | .port_ops = &k2_sata_ops, |
419 | }, |
420 | /* chip_svw43 */ |
421 | { |
422 | .flags = ATA_FLAG_SATA, |
423 | .pio_mask = ATA_PIO4, |
424 | .mwdma_mask = ATA_MWDMA2, |
425 | .udma_mask = ATA_UDMA6, |
426 | .port_ops = &k2_sata_ops, |
427 | }, |
428 | }; |
429 | |
430 | static void k2_sata_setup_port(struct ata_ioports *port, void __iomem *base) |
431 | { |
432 | port->cmd_addr = base + K2_SATA_TF_CMD_OFFSET; |
433 | port->data_addr = base + K2_SATA_TF_DATA_OFFSET; |
434 | port->feature_addr = |
435 | port->error_addr = base + K2_SATA_TF_ERROR_OFFSET; |
436 | port->nsect_addr = base + K2_SATA_TF_NSECT_OFFSET; |
437 | port->lbal_addr = base + K2_SATA_TF_LBAL_OFFSET; |
438 | port->lbam_addr = base + K2_SATA_TF_LBAM_OFFSET; |
439 | port->lbah_addr = base + K2_SATA_TF_LBAH_OFFSET; |
440 | port->device_addr = base + K2_SATA_TF_DEVICE_OFFSET; |
441 | port->command_addr = |
442 | port->status_addr = base + K2_SATA_TF_CMDSTAT_OFFSET; |
443 | port->altstatus_addr = |
444 | port->ctl_addr = base + K2_SATA_TF_CTL_OFFSET; |
445 | port->bmdma_addr = base + K2_SATA_DMA_CMD_OFFSET; |
446 | port->scr_addr = base + K2_SATA_SCR_STATUS_OFFSET; |
447 | } |
448 | |
449 | |
450 | static int k2_sata_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) |
451 | { |
452 | const struct ata_port_info *ppi[] = |
453 | { &k2_port_info[ent->driver_data], NULL }; |
454 | struct ata_host *host; |
455 | void __iomem *mmio_base; |
456 | int n_ports, i, rc, bar_pos; |
457 | |
458 | ata_print_version_once(&pdev->dev, DRV_VERSION); |
459 | |
460 | /* allocate host */ |
461 | n_ports = 4; |
462 | if (ppi[0]->flags & K2_FLAG_SATA_8_PORTS) |
463 | n_ports = 8; |
464 | |
465 | host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports); |
466 | if (!host) |
467 | return -ENOMEM; |
468 | |
469 | bar_pos = 5; |
470 | if (ppi[0]->flags & K2_FLAG_BAR_POS_3) |
471 | bar_pos = 3; |
472 | /* |
473 | * If this driver happens to only be useful on Apple's K2, then |
474 | * we should check that here as it has a normal Serverworks ID |
475 | */ |
476 | rc = pcim_enable_device(pdev); |
477 | if (rc) |
478 | return rc; |
479 | |
480 | /* |
481 | * Check if we have resources mapped at all (second function may |
482 | * have been disabled by firmware) |
483 | */ |
484 | if (pci_resource_len(pdev, bar_pos) == 0) { |
485 | /* In IDE mode we need to pin the device to ensure that |
486 | pcim_release does not clear the busmaster bit in config |
487 | space, clearing causes busmaster DMA to fail on |
488 | ports 3 & 4 */ |
489 | pcim_pin_device(pdev); |
490 | return -ENODEV; |
491 | } |
492 | |
493 | /* Request and iomap PCI regions */ |
494 | rc = pcim_iomap_regions(pdev, 1 << bar_pos, DRV_NAME); |
495 | if (rc == -EBUSY) |
496 | pcim_pin_device(pdev); |
497 | if (rc) |
498 | return rc; |
499 | host->iomap = pcim_iomap_table(pdev); |
500 | mmio_base = host->iomap[bar_pos]; |
501 | |
502 | /* different controllers have different number of ports - currently 4 or 8 */ |
503 | /* All ports are on the same function. Multi-function device is no |
504 | * longer available. This should not be seen in any system. */ |
505 | for (i = 0; i < host->n_ports; i++) { |
506 | struct ata_port *ap = host->ports[i]; |
507 | unsigned int offset = i * K2_SATA_PORT_OFFSET; |
508 | |
509 | k2_sata_setup_port(&ap->ioaddr, mmio_base + offset); |
510 | |
511 | ata_port_pbar_desc(ap, 5, -1, "mmio"); |
512 | ata_port_pbar_desc(ap, 5, offset, "port"); |
513 | } |
514 | |
515 | rc = pci_set_dma_mask(pdev, ATA_DMA_MASK); |
516 | if (rc) |
517 | return rc; |
518 | rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK); |
519 | if (rc) |
520 | return rc; |
521 | |
522 | /* Clear a magic bit in SCR1 according to Darwin, those help |
523 | * some funky seagate drives (though so far, those were already |
524 | * set by the firmware on the machines I had access to) |
525 | */ |
526 | writel(readl(mmio_base + K2_SATA_SICR1_OFFSET) & ~0x00040000, |
527 | mmio_base + K2_SATA_SICR1_OFFSET); |
528 | |
529 | /* Clear SATA error & interrupts we don't use */ |
530 | writel(0xffffffff, mmio_base + K2_SATA_SCR_ERROR_OFFSET); |
531 | writel(0x0, mmio_base + K2_SATA_SIM_OFFSET); |
532 | |
533 | pci_set_master(pdev); |
534 | return ata_host_activate(host, pdev->irq, ata_bmdma_interrupt, |
535 | IRQF_SHARED, &k2_sata_sht); |
536 | } |
537 | |
538 | /* 0x240 is device ID for Apple K2 device |
539 | * 0x241 is device ID for Serverworks Frodo4 |
540 | * 0x242 is device ID for Serverworks Frodo8 |
541 | * 0x24a is device ID for BCM5785 (aka HT1000) HT southbridge integrated SATA |
542 | * controller |
543 | * */ |
544 | static const struct pci_device_id k2_sata_pci_tbl[] = { |
545 | { PCI_VDEVICE(SERVERWORKS, 0x0240), chip_svw4 }, |
546 | { PCI_VDEVICE(SERVERWORKS, 0x0241), chip_svw8 }, |
547 | { PCI_VDEVICE(SERVERWORKS, 0x0242), chip_svw4 }, |
548 | { PCI_VDEVICE(SERVERWORKS, 0x024a), chip_svw4 }, |
549 | { PCI_VDEVICE(SERVERWORKS, 0x024b), chip_svw4 }, |
550 | { PCI_VDEVICE(SERVERWORKS, 0x0410), chip_svw42 }, |
551 | { PCI_VDEVICE(SERVERWORKS, 0x0411), chip_svw43 }, |
552 | |
553 | { } |
554 | }; |
555 | |
556 | static struct pci_driver k2_sata_pci_driver = { |
557 | .name = DRV_NAME, |
558 | .id_table = k2_sata_pci_tbl, |
559 | .probe = k2_sata_init_one, |
560 | .remove = ata_pci_remove_one, |
561 | }; |
562 | |
563 | module_pci_driver(k2_sata_pci_driver); |
564 | |
565 | MODULE_AUTHOR("Benjamin Herrenschmidt"); |
566 | MODULE_DESCRIPTION("low-level driver for K2 SATA controller"); |
567 | MODULE_LICENSE("GPL"); |
568 | MODULE_DEVICE_TABLE(pci, k2_sata_pci_tbl); |
569 | MODULE_VERSION(DRV_VERSION); |
570 |
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od-2011-09-04
od-2011-09-18
v2.6.34-rc5
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v3.9