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1 | /* |
2 | * Freescale MPC85xx Memory Controller kenel module |
3 | * |
4 | * Author: Dave Jiang <djiang@mvista.com> |
5 | * |
6 | * 2006-2007 (c) MontaVista Software, Inc. This file is licensed under |
7 | * the terms of the GNU General Public License version 2. This program |
8 | * is licensed "as is" without any warranty of any kind, whether express |
9 | * or implied. |
10 | * |
11 | */ |
12 | #include <linux/module.h> |
13 | #include <linux/init.h> |
14 | #include <linux/interrupt.h> |
15 | #include <linux/ctype.h> |
16 | #include <linux/io.h> |
17 | #include <linux/mod_devicetable.h> |
18 | #include <linux/edac.h> |
19 | #include <linux/smp.h> |
20 | #include <linux/gfp.h> |
21 | |
22 | #include <linux/of_platform.h> |
23 | #include <linux/of_device.h> |
24 | #include "edac_module.h" |
25 | #include "edac_core.h" |
26 | #include "mpc85xx_edac.h" |
27 | |
28 | static int edac_dev_idx; |
29 | #ifdef CONFIG_PCI |
30 | static int edac_pci_idx; |
31 | #endif |
32 | static int edac_mc_idx; |
33 | |
34 | static u32 orig_ddr_err_disable; |
35 | static u32 orig_ddr_err_sbe; |
36 | |
37 | /* |
38 | * PCI Err defines |
39 | */ |
40 | #ifdef CONFIG_PCI |
41 | static u32 orig_pci_err_cap_dr; |
42 | static u32 orig_pci_err_en; |
43 | #endif |
44 | |
45 | static u32 orig_l2_err_disable; |
46 | #ifdef CONFIG_FSL_SOC_BOOKE |
47 | static u32 orig_hid1[2]; |
48 | #endif |
49 | |
50 | /************************ MC SYSFS parts ***********************************/ |
51 | |
52 | #define to_mci(k) container_of(k, struct mem_ctl_info, dev) |
53 | |
54 | static ssize_t mpc85xx_mc_inject_data_hi_show(struct device *dev, |
55 | struct device_attribute *mattr, |
56 | char *data) |
57 | { |
58 | struct mem_ctl_info *mci = to_mci(dev); |
59 | struct mpc85xx_mc_pdata *pdata = mci->pvt_info; |
60 | return sprintf(data, "0x%08x", |
61 | in_be32(pdata->mc_vbase + |
62 | MPC85XX_MC_DATA_ERR_INJECT_HI)); |
63 | } |
64 | |
65 | static ssize_t mpc85xx_mc_inject_data_lo_show(struct device *dev, |
66 | struct device_attribute *mattr, |
67 | char *data) |
68 | { |
69 | struct mem_ctl_info *mci = to_mci(dev); |
70 | struct mpc85xx_mc_pdata *pdata = mci->pvt_info; |
71 | return sprintf(data, "0x%08x", |
72 | in_be32(pdata->mc_vbase + |
73 | MPC85XX_MC_DATA_ERR_INJECT_LO)); |
74 | } |
75 | |
76 | static ssize_t mpc85xx_mc_inject_ctrl_show(struct device *dev, |
77 | struct device_attribute *mattr, |
78 | char *data) |
79 | { |
80 | struct mem_ctl_info *mci = to_mci(dev); |
81 | struct mpc85xx_mc_pdata *pdata = mci->pvt_info; |
82 | return sprintf(data, "0x%08x", |
83 | in_be32(pdata->mc_vbase + MPC85XX_MC_ECC_ERR_INJECT)); |
84 | } |
85 | |
86 | static ssize_t mpc85xx_mc_inject_data_hi_store(struct device *dev, |
87 | struct device_attribute *mattr, |
88 | const char *data, size_t count) |
89 | { |
90 | struct mem_ctl_info *mci = to_mci(dev); |
91 | struct mpc85xx_mc_pdata *pdata = mci->pvt_info; |
92 | if (isdigit(*data)) { |
93 | out_be32(pdata->mc_vbase + MPC85XX_MC_DATA_ERR_INJECT_HI, |
94 | simple_strtoul(data, NULL, 0)); |
95 | return count; |
96 | } |
97 | return 0; |
98 | } |
99 | |
100 | static ssize_t mpc85xx_mc_inject_data_lo_store(struct device *dev, |
101 | struct device_attribute *mattr, |
102 | const char *data, size_t count) |
103 | { |
104 | struct mem_ctl_info *mci = to_mci(dev); |
105 | struct mpc85xx_mc_pdata *pdata = mci->pvt_info; |
106 | if (isdigit(*data)) { |
107 | out_be32(pdata->mc_vbase + MPC85XX_MC_DATA_ERR_INJECT_LO, |
108 | simple_strtoul(data, NULL, 0)); |
109 | return count; |
110 | } |
111 | return 0; |
112 | } |
113 | |
114 | static ssize_t mpc85xx_mc_inject_ctrl_store(struct device *dev, |
115 | struct device_attribute *mattr, |
116 | const char *data, size_t count) |
117 | { |
118 | struct mem_ctl_info *mci = to_mci(dev); |
119 | struct mpc85xx_mc_pdata *pdata = mci->pvt_info; |
120 | if (isdigit(*data)) { |
121 | out_be32(pdata->mc_vbase + MPC85XX_MC_ECC_ERR_INJECT, |
122 | simple_strtoul(data, NULL, 0)); |
123 | return count; |
124 | } |
125 | return 0; |
126 | } |
127 | |
128 | DEVICE_ATTR(inject_data_hi, S_IRUGO | S_IWUSR, |
129 | mpc85xx_mc_inject_data_hi_show, mpc85xx_mc_inject_data_hi_store); |
130 | DEVICE_ATTR(inject_data_lo, S_IRUGO | S_IWUSR, |
131 | mpc85xx_mc_inject_data_lo_show, mpc85xx_mc_inject_data_lo_store); |
132 | DEVICE_ATTR(inject_ctrl, S_IRUGO | S_IWUSR, |
133 | mpc85xx_mc_inject_ctrl_show, mpc85xx_mc_inject_ctrl_store); |
134 | |
135 | static int mpc85xx_create_sysfs_attributes(struct mem_ctl_info *mci) |
136 | { |
137 | int rc; |
138 | |
139 | rc = device_create_file(&mci->dev, &dev_attr_inject_data_hi); |
140 | if (rc < 0) |
141 | return rc; |
142 | rc = device_create_file(&mci->dev, &dev_attr_inject_data_lo); |
143 | if (rc < 0) |
144 | return rc; |
145 | rc = device_create_file(&mci->dev, &dev_attr_inject_ctrl); |
146 | if (rc < 0) |
147 | return rc; |
148 | |
149 | return 0; |
150 | } |
151 | |
152 | static void mpc85xx_remove_sysfs_attributes(struct mem_ctl_info *mci) |
153 | { |
154 | device_remove_file(&mci->dev, &dev_attr_inject_data_hi); |
155 | device_remove_file(&mci->dev, &dev_attr_inject_data_lo); |
156 | device_remove_file(&mci->dev, &dev_attr_inject_ctrl); |
157 | } |
158 | |
159 | /**************************** PCI Err device ***************************/ |
160 | #ifdef CONFIG_PCI |
161 | |
162 | static void mpc85xx_pci_check(struct edac_pci_ctl_info *pci) |
163 | { |
164 | struct mpc85xx_pci_pdata *pdata = pci->pvt_info; |
165 | u32 err_detect; |
166 | |
167 | err_detect = in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR); |
168 | |
169 | /* master aborts can happen during PCI config cycles */ |
170 | if (!(err_detect & ~(PCI_EDE_MULTI_ERR | PCI_EDE_MST_ABRT))) { |
171 | out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR, err_detect); |
172 | return; |
173 | } |
174 | |
175 | printk(KERN_ERR "PCI error(s) detected\n"); |
176 | printk(KERN_ERR "PCI/X ERR_DR register: %#08x\n", err_detect); |
177 | |
178 | printk(KERN_ERR "PCI/X ERR_ATTRIB register: %#08x\n", |
179 | in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_ATTRIB)); |
180 | printk(KERN_ERR "PCI/X ERR_ADDR register: %#08x\n", |
181 | in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_ADDR)); |
182 | printk(KERN_ERR "PCI/X ERR_EXT_ADDR register: %#08x\n", |
183 | in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_EXT_ADDR)); |
184 | printk(KERN_ERR "PCI/X ERR_DL register: %#08x\n", |
185 | in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DL)); |
186 | printk(KERN_ERR "PCI/X ERR_DH register: %#08x\n", |
187 | in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DH)); |
188 | |
189 | /* clear error bits */ |
190 | out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR, err_detect); |
191 | |
192 | if (err_detect & PCI_EDE_PERR_MASK) |
193 | edac_pci_handle_pe(pci, pci->ctl_name); |
194 | |
195 | if ((err_detect & ~PCI_EDE_MULTI_ERR) & ~PCI_EDE_PERR_MASK) |
196 | edac_pci_handle_npe(pci, pci->ctl_name); |
197 | } |
198 | |
199 | static irqreturn_t mpc85xx_pci_isr(int irq, void *dev_id) |
200 | { |
201 | struct edac_pci_ctl_info *pci = dev_id; |
202 | struct mpc85xx_pci_pdata *pdata = pci->pvt_info; |
203 | u32 err_detect; |
204 | |
205 | err_detect = in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR); |
206 | |
207 | if (!err_detect) |
208 | return IRQ_NONE; |
209 | |
210 | mpc85xx_pci_check(pci); |
211 | |
212 | return IRQ_HANDLED; |
213 | } |
214 | |
215 | int mpc85xx_pci_err_probe(struct platform_device *op) |
216 | { |
217 | struct edac_pci_ctl_info *pci; |
218 | struct mpc85xx_pci_pdata *pdata; |
219 | struct resource r; |
220 | int res = 0; |
221 | |
222 | if (!devres_open_group(&op->dev, mpc85xx_pci_err_probe, GFP_KERNEL)) |
223 | return -ENOMEM; |
224 | |
225 | pci = edac_pci_alloc_ctl_info(sizeof(*pdata), "mpc85xx_pci_err"); |
226 | if (!pci) |
227 | return -ENOMEM; |
228 | |
229 | /* make sure error reporting method is sane */ |
230 | switch (edac_op_state) { |
231 | case EDAC_OPSTATE_POLL: |
232 | case EDAC_OPSTATE_INT: |
233 | break; |
234 | default: |
235 | edac_op_state = EDAC_OPSTATE_INT; |
236 | break; |
237 | } |
238 | |
239 | pdata = pci->pvt_info; |
240 | pdata->name = "mpc85xx_pci_err"; |
241 | pdata->irq = NO_IRQ; |
242 | dev_set_drvdata(&op->dev, pci); |
243 | pci->dev = &op->dev; |
244 | pci->mod_name = EDAC_MOD_STR; |
245 | pci->ctl_name = pdata->name; |
246 | pci->dev_name = dev_name(&op->dev); |
247 | |
248 | if (edac_op_state == EDAC_OPSTATE_POLL) |
249 | pci->edac_check = mpc85xx_pci_check; |
250 | |
251 | pdata->edac_idx = edac_pci_idx++; |
252 | |
253 | res = of_address_to_resource(op->dev.of_node, 0, &r); |
254 | if (res) { |
255 | printk(KERN_ERR "%s: Unable to get resource for " |
256 | "PCI err regs\n", __func__); |
257 | goto err; |
258 | } |
259 | |
260 | /* we only need the error registers */ |
261 | r.start += 0xe00; |
262 | |
263 | if (!devm_request_mem_region(&op->dev, r.start, resource_size(&r), |
264 | pdata->name)) { |
265 | printk(KERN_ERR "%s: Error while requesting mem region\n", |
266 | __func__); |
267 | res = -EBUSY; |
268 | goto err; |
269 | } |
270 | |
271 | pdata->pci_vbase = devm_ioremap(&op->dev, r.start, resource_size(&r)); |
272 | if (!pdata->pci_vbase) { |
273 | printk(KERN_ERR "%s: Unable to setup PCI err regs\n", __func__); |
274 | res = -ENOMEM; |
275 | goto err; |
276 | } |
277 | |
278 | orig_pci_err_cap_dr = |
279 | in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_CAP_DR); |
280 | |
281 | /* PCI master abort is expected during config cycles */ |
282 | out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_CAP_DR, 0x40); |
283 | |
284 | orig_pci_err_en = in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_EN); |
285 | |
286 | /* disable master abort reporting */ |
287 | out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_EN, ~0x40); |
288 | |
289 | /* clear error bits */ |
290 | out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR, ~0); |
291 | |
292 | if (edac_pci_add_device(pci, pdata->edac_idx) > 0) { |
293 | edac_dbg(3, "failed edac_pci_add_device()\n"); |
294 | goto err; |
295 | } |
296 | |
297 | if (edac_op_state == EDAC_OPSTATE_INT) { |
298 | pdata->irq = irq_of_parse_and_map(op->dev.of_node, 0); |
299 | res = devm_request_irq(&op->dev, pdata->irq, |
300 | mpc85xx_pci_isr, IRQF_DISABLED, |
301 | "[EDAC] PCI err", pci); |
302 | if (res < 0) { |
303 | printk(KERN_ERR |
304 | "%s: Unable to request irq %d for " |
305 | "MPC85xx PCI err\n", __func__, pdata->irq); |
306 | irq_dispose_mapping(pdata->irq); |
307 | res = -ENODEV; |
308 | goto err2; |
309 | } |
310 | |
311 | printk(KERN_INFO EDAC_MOD_STR " acquired irq %d for PCI Err\n", |
312 | pdata->irq); |
313 | } |
314 | |
315 | devres_remove_group(&op->dev, mpc85xx_pci_err_probe); |
316 | edac_dbg(3, "success\n"); |
317 | printk(KERN_INFO EDAC_MOD_STR " PCI err registered\n"); |
318 | |
319 | return 0; |
320 | |
321 | err2: |
322 | edac_pci_del_device(&op->dev); |
323 | err: |
324 | edac_pci_free_ctl_info(pci); |
325 | devres_release_group(&op->dev, mpc85xx_pci_err_probe); |
326 | return res; |
327 | } |
328 | EXPORT_SYMBOL(mpc85xx_pci_err_probe); |
329 | |
330 | static int mpc85xx_pci_err_remove(struct platform_device *op) |
331 | { |
332 | struct edac_pci_ctl_info *pci = dev_get_drvdata(&op->dev); |
333 | struct mpc85xx_pci_pdata *pdata = pci->pvt_info; |
334 | |
335 | edac_dbg(0, "\n"); |
336 | |
337 | out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_CAP_DR, |
338 | orig_pci_err_cap_dr); |
339 | |
340 | out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_EN, orig_pci_err_en); |
341 | |
342 | edac_pci_del_device(pci->dev); |
343 | |
344 | if (edac_op_state == EDAC_OPSTATE_INT) |
345 | irq_dispose_mapping(pdata->irq); |
346 | |
347 | edac_pci_free_ctl_info(pci); |
348 | |
349 | return 0; |
350 | } |
351 | |
352 | #endif /* CONFIG_PCI */ |
353 | |
354 | /**************************** L2 Err device ***************************/ |
355 | |
356 | /************************ L2 SYSFS parts ***********************************/ |
357 | |
358 | static ssize_t mpc85xx_l2_inject_data_hi_show(struct edac_device_ctl_info |
359 | *edac_dev, char *data) |
360 | { |
361 | struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info; |
362 | return sprintf(data, "0x%08x", |
363 | in_be32(pdata->l2_vbase + MPC85XX_L2_ERRINJHI)); |
364 | } |
365 | |
366 | static ssize_t mpc85xx_l2_inject_data_lo_show(struct edac_device_ctl_info |
367 | *edac_dev, char *data) |
368 | { |
369 | struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info; |
370 | return sprintf(data, "0x%08x", |
371 | in_be32(pdata->l2_vbase + MPC85XX_L2_ERRINJLO)); |
372 | } |
373 | |
374 | static ssize_t mpc85xx_l2_inject_ctrl_show(struct edac_device_ctl_info |
375 | *edac_dev, char *data) |
376 | { |
377 | struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info; |
378 | return sprintf(data, "0x%08x", |
379 | in_be32(pdata->l2_vbase + MPC85XX_L2_ERRINJCTL)); |
380 | } |
381 | |
382 | static ssize_t mpc85xx_l2_inject_data_hi_store(struct edac_device_ctl_info |
383 | *edac_dev, const char *data, |
384 | size_t count) |
385 | { |
386 | struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info; |
387 | if (isdigit(*data)) { |
388 | out_be32(pdata->l2_vbase + MPC85XX_L2_ERRINJHI, |
389 | simple_strtoul(data, NULL, 0)); |
390 | return count; |
391 | } |
392 | return 0; |
393 | } |
394 | |
395 | static ssize_t mpc85xx_l2_inject_data_lo_store(struct edac_device_ctl_info |
396 | *edac_dev, const char *data, |
397 | size_t count) |
398 | { |
399 | struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info; |
400 | if (isdigit(*data)) { |
401 | out_be32(pdata->l2_vbase + MPC85XX_L2_ERRINJLO, |
402 | simple_strtoul(data, NULL, 0)); |
403 | return count; |
404 | } |
405 | return 0; |
406 | } |
407 | |
408 | static ssize_t mpc85xx_l2_inject_ctrl_store(struct edac_device_ctl_info |
409 | *edac_dev, const char *data, |
410 | size_t count) |
411 | { |
412 | struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info; |
413 | if (isdigit(*data)) { |
414 | out_be32(pdata->l2_vbase + MPC85XX_L2_ERRINJCTL, |
415 | simple_strtoul(data, NULL, 0)); |
416 | return count; |
417 | } |
418 | return 0; |
419 | } |
420 | |
421 | static struct edac_dev_sysfs_attribute mpc85xx_l2_sysfs_attributes[] = { |
422 | { |
423 | .attr = { |
424 | .name = "inject_data_hi", |
425 | .mode = (S_IRUGO | S_IWUSR) |
426 | }, |
427 | .show = mpc85xx_l2_inject_data_hi_show, |
428 | .store = mpc85xx_l2_inject_data_hi_store}, |
429 | { |
430 | .attr = { |
431 | .name = "inject_data_lo", |
432 | .mode = (S_IRUGO | S_IWUSR) |
433 | }, |
434 | .show = mpc85xx_l2_inject_data_lo_show, |
435 | .store = mpc85xx_l2_inject_data_lo_store}, |
436 | { |
437 | .attr = { |
438 | .name = "inject_ctrl", |
439 | .mode = (S_IRUGO | S_IWUSR) |
440 | }, |
441 | .show = mpc85xx_l2_inject_ctrl_show, |
442 | .store = mpc85xx_l2_inject_ctrl_store}, |
443 | |
444 | /* End of list */ |
445 | { |
446 | .attr = {.name = NULL} |
447 | } |
448 | }; |
449 | |
450 | static void mpc85xx_set_l2_sysfs_attributes(struct edac_device_ctl_info |
451 | *edac_dev) |
452 | { |
453 | edac_dev->sysfs_attributes = mpc85xx_l2_sysfs_attributes; |
454 | } |
455 | |
456 | /***************************** L2 ops ***********************************/ |
457 | |
458 | static void mpc85xx_l2_check(struct edac_device_ctl_info *edac_dev) |
459 | { |
460 | struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info; |
461 | u32 err_detect; |
462 | |
463 | err_detect = in_be32(pdata->l2_vbase + MPC85XX_L2_ERRDET); |
464 | |
465 | if (!(err_detect & L2_EDE_MASK)) |
466 | return; |
467 | |
468 | printk(KERN_ERR "ECC Error in CPU L2 cache\n"); |
469 | printk(KERN_ERR "L2 Error Detect Register: 0x%08x\n", err_detect); |
470 | printk(KERN_ERR "L2 Error Capture Data High Register: 0x%08x\n", |
471 | in_be32(pdata->l2_vbase + MPC85XX_L2_CAPTDATAHI)); |
472 | printk(KERN_ERR "L2 Error Capture Data Lo Register: 0x%08x\n", |
473 | in_be32(pdata->l2_vbase + MPC85XX_L2_CAPTDATALO)); |
474 | printk(KERN_ERR "L2 Error Syndrome Register: 0x%08x\n", |
475 | in_be32(pdata->l2_vbase + MPC85XX_L2_CAPTECC)); |
476 | printk(KERN_ERR "L2 Error Attributes Capture Register: 0x%08x\n", |
477 | in_be32(pdata->l2_vbase + MPC85XX_L2_ERRATTR)); |
478 | printk(KERN_ERR "L2 Error Address Capture Register: 0x%08x\n", |
479 | in_be32(pdata->l2_vbase + MPC85XX_L2_ERRADDR)); |
480 | |
481 | /* clear error detect register */ |
482 | out_be32(pdata->l2_vbase + MPC85XX_L2_ERRDET, err_detect); |
483 | |
484 | if (err_detect & L2_EDE_CE_MASK) |
485 | edac_device_handle_ce(edac_dev, 0, 0, edac_dev->ctl_name); |
486 | |
487 | if (err_detect & L2_EDE_UE_MASK) |
488 | edac_device_handle_ue(edac_dev, 0, 0, edac_dev->ctl_name); |
489 | } |
490 | |
491 | static irqreturn_t mpc85xx_l2_isr(int irq, void *dev_id) |
492 | { |
493 | struct edac_device_ctl_info *edac_dev = dev_id; |
494 | struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info; |
495 | u32 err_detect; |
496 | |
497 | err_detect = in_be32(pdata->l2_vbase + MPC85XX_L2_ERRDET); |
498 | |
499 | if (!(err_detect & L2_EDE_MASK)) |
500 | return IRQ_NONE; |
501 | |
502 | mpc85xx_l2_check(edac_dev); |
503 | |
504 | return IRQ_HANDLED; |
505 | } |
506 | |
507 | static int mpc85xx_l2_err_probe(struct platform_device *op) |
508 | { |
509 | struct edac_device_ctl_info *edac_dev; |
510 | struct mpc85xx_l2_pdata *pdata; |
511 | struct resource r; |
512 | int res; |
513 | |
514 | if (!devres_open_group(&op->dev, mpc85xx_l2_err_probe, GFP_KERNEL)) |
515 | return -ENOMEM; |
516 | |
517 | edac_dev = edac_device_alloc_ctl_info(sizeof(*pdata), |
518 | "cpu", 1, "L", 1, 2, NULL, 0, |
519 | edac_dev_idx); |
520 | if (!edac_dev) { |
521 | devres_release_group(&op->dev, mpc85xx_l2_err_probe); |
522 | return -ENOMEM; |
523 | } |
524 | |
525 | pdata = edac_dev->pvt_info; |
526 | pdata->name = "mpc85xx_l2_err"; |
527 | pdata->irq = NO_IRQ; |
528 | edac_dev->dev = &op->dev; |
529 | dev_set_drvdata(edac_dev->dev, edac_dev); |
530 | edac_dev->ctl_name = pdata->name; |
531 | edac_dev->dev_name = pdata->name; |
532 | |
533 | res = of_address_to_resource(op->dev.of_node, 0, &r); |
534 | if (res) { |
535 | printk(KERN_ERR "%s: Unable to get resource for " |
536 | "L2 err regs\n", __func__); |
537 | goto err; |
538 | } |
539 | |
540 | /* we only need the error registers */ |
541 | r.start += 0xe00; |
542 | |
543 | if (!devm_request_mem_region(&op->dev, r.start, resource_size(&r), |
544 | pdata->name)) { |
545 | printk(KERN_ERR "%s: Error while requesting mem region\n", |
546 | __func__); |
547 | res = -EBUSY; |
548 | goto err; |
549 | } |
550 | |
551 | pdata->l2_vbase = devm_ioremap(&op->dev, r.start, resource_size(&r)); |
552 | if (!pdata->l2_vbase) { |
553 | printk(KERN_ERR "%s: Unable to setup L2 err regs\n", __func__); |
554 | res = -ENOMEM; |
555 | goto err; |
556 | } |
557 | |
558 | out_be32(pdata->l2_vbase + MPC85XX_L2_ERRDET, ~0); |
559 | |
560 | orig_l2_err_disable = in_be32(pdata->l2_vbase + MPC85XX_L2_ERRDIS); |
561 | |
562 | /* clear the err_dis */ |
563 | out_be32(pdata->l2_vbase + MPC85XX_L2_ERRDIS, 0); |
564 | |
565 | edac_dev->mod_name = EDAC_MOD_STR; |
566 | |
567 | if (edac_op_state == EDAC_OPSTATE_POLL) |
568 | edac_dev->edac_check = mpc85xx_l2_check; |
569 | |
570 | mpc85xx_set_l2_sysfs_attributes(edac_dev); |
571 | |
572 | pdata->edac_idx = edac_dev_idx++; |
573 | |
574 | if (edac_device_add_device(edac_dev) > 0) { |
575 | edac_dbg(3, "failed edac_device_add_device()\n"); |
576 | goto err; |
577 | } |
578 | |
579 | if (edac_op_state == EDAC_OPSTATE_INT) { |
580 | pdata->irq = irq_of_parse_and_map(op->dev.of_node, 0); |
581 | res = devm_request_irq(&op->dev, pdata->irq, |
582 | mpc85xx_l2_isr, IRQF_DISABLED, |
583 | "[EDAC] L2 err", edac_dev); |
584 | if (res < 0) { |
585 | printk(KERN_ERR |
586 | "%s: Unable to request irq %d for " |
587 | "MPC85xx L2 err\n", __func__, pdata->irq); |
588 | irq_dispose_mapping(pdata->irq); |
589 | res = -ENODEV; |
590 | goto err2; |
591 | } |
592 | |
593 | printk(KERN_INFO EDAC_MOD_STR " acquired irq %d for L2 Err\n", |
594 | pdata->irq); |
595 | |
596 | edac_dev->op_state = OP_RUNNING_INTERRUPT; |
597 | |
598 | out_be32(pdata->l2_vbase + MPC85XX_L2_ERRINTEN, L2_EIE_MASK); |
599 | } |
600 | |
601 | devres_remove_group(&op->dev, mpc85xx_l2_err_probe); |
602 | |
603 | edac_dbg(3, "success\n"); |
604 | printk(KERN_INFO EDAC_MOD_STR " L2 err registered\n"); |
605 | |
606 | return 0; |
607 | |
608 | err2: |
609 | edac_device_del_device(&op->dev); |
610 | err: |
611 | devres_release_group(&op->dev, mpc85xx_l2_err_probe); |
612 | edac_device_free_ctl_info(edac_dev); |
613 | return res; |
614 | } |
615 | |
616 | static int mpc85xx_l2_err_remove(struct platform_device *op) |
617 | { |
618 | struct edac_device_ctl_info *edac_dev = dev_get_drvdata(&op->dev); |
619 | struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info; |
620 | |
621 | edac_dbg(0, "\n"); |
622 | |
623 | if (edac_op_state == EDAC_OPSTATE_INT) { |
624 | out_be32(pdata->l2_vbase + MPC85XX_L2_ERRINTEN, 0); |
625 | irq_dispose_mapping(pdata->irq); |
626 | } |
627 | |
628 | out_be32(pdata->l2_vbase + MPC85XX_L2_ERRDIS, orig_l2_err_disable); |
629 | edac_device_del_device(&op->dev); |
630 | edac_device_free_ctl_info(edac_dev); |
631 | return 0; |
632 | } |
633 | |
634 | static struct of_device_id mpc85xx_l2_err_of_match[] = { |
635 | /* deprecate the fsl,85.. forms in the future, 2.6.30? */ |
636 | { .compatible = "fsl,8540-l2-cache-controller", }, |
637 | { .compatible = "fsl,8541-l2-cache-controller", }, |
638 | { .compatible = "fsl,8544-l2-cache-controller", }, |
639 | { .compatible = "fsl,8548-l2-cache-controller", }, |
640 | { .compatible = "fsl,8555-l2-cache-controller", }, |
641 | { .compatible = "fsl,8568-l2-cache-controller", }, |
642 | { .compatible = "fsl,mpc8536-l2-cache-controller", }, |
643 | { .compatible = "fsl,mpc8540-l2-cache-controller", }, |
644 | { .compatible = "fsl,mpc8541-l2-cache-controller", }, |
645 | { .compatible = "fsl,mpc8544-l2-cache-controller", }, |
646 | { .compatible = "fsl,mpc8548-l2-cache-controller", }, |
647 | { .compatible = "fsl,mpc8555-l2-cache-controller", }, |
648 | { .compatible = "fsl,mpc8560-l2-cache-controller", }, |
649 | { .compatible = "fsl,mpc8568-l2-cache-controller", }, |
650 | { .compatible = "fsl,mpc8569-l2-cache-controller", }, |
651 | { .compatible = "fsl,mpc8572-l2-cache-controller", }, |
652 | { .compatible = "fsl,p1020-l2-cache-controller", }, |
653 | { .compatible = "fsl,p1021-l2-cache-controller", }, |
654 | { .compatible = "fsl,p2020-l2-cache-controller", }, |
655 | {}, |
656 | }; |
657 | MODULE_DEVICE_TABLE(of, mpc85xx_l2_err_of_match); |
658 | |
659 | static struct platform_driver mpc85xx_l2_err_driver = { |
660 | .probe = mpc85xx_l2_err_probe, |
661 | .remove = mpc85xx_l2_err_remove, |
662 | .driver = { |
663 | .name = "mpc85xx_l2_err", |
664 | .owner = THIS_MODULE, |
665 | .of_match_table = mpc85xx_l2_err_of_match, |
666 | }, |
667 | }; |
668 | |
669 | /**************************** MC Err device ***************************/ |
670 | |
671 | /* |
672 | * Taken from table 8-55 in the MPC8641 User's Manual and/or 9-61 in the |
673 | * MPC8572 User's Manual. Each line represents a syndrome bit column as a |
674 | * 64-bit value, but split into an upper and lower 32-bit chunk. The labels |
675 | * below correspond to Freescale's manuals. |
676 | */ |
677 | static unsigned int ecc_table[16] = { |
678 | /* MSB LSB */ |
679 | /* [0:31] [32:63] */ |
680 | 0xf00fe11e, 0xc33c0ff7, /* Syndrome bit 7 */ |
681 | 0x00ff00ff, 0x00fff0ff, |
682 | 0x0f0f0f0f, 0x0f0fff00, |
683 | 0x11113333, 0x7777000f, |
684 | 0x22224444, 0x8888222f, |
685 | 0x44448888, 0xffff4441, |
686 | 0x8888ffff, 0x11118882, |
687 | 0xffff1111, 0x22221114, /* Syndrome bit 0 */ |
688 | }; |
689 | |
690 | /* |
691 | * Calculate the correct ECC value for a 64-bit value specified by high:low |
692 | */ |
693 | static u8 calculate_ecc(u32 high, u32 low) |
694 | { |
695 | u32 mask_low; |
696 | u32 mask_high; |
697 | int bit_cnt; |
698 | u8 ecc = 0; |
699 | int i; |
700 | int j; |
701 | |
702 | for (i = 0; i < 8; i++) { |
703 | mask_high = ecc_table[i * 2]; |
704 | mask_low = ecc_table[i * 2 + 1]; |
705 | bit_cnt = 0; |
706 | |
707 | for (j = 0; j < 32; j++) { |
708 | if ((mask_high >> j) & 1) |
709 | bit_cnt ^= (high >> j) & 1; |
710 | if ((mask_low >> j) & 1) |
711 | bit_cnt ^= (low >> j) & 1; |
712 | } |
713 | |
714 | ecc |= bit_cnt << i; |
715 | } |
716 | |
717 | return ecc; |
718 | } |
719 | |
720 | /* |
721 | * Create the syndrome code which is generated if the data line specified by |
722 | * 'bit' failed. Eg generate an 8-bit codes seen in Table 8-55 in the MPC8641 |
723 | * User's Manual and 9-61 in the MPC8572 User's Manual. |
724 | */ |
725 | static u8 syndrome_from_bit(unsigned int bit) { |
726 | int i; |
727 | u8 syndrome = 0; |
728 | |
729 | /* |
730 | * Cycle through the upper or lower 32-bit portion of each value in |
731 | * ecc_table depending on if 'bit' is in the upper or lower half of |
732 | * 64-bit data. |
733 | */ |
734 | for (i = bit < 32; i < 16; i += 2) |
735 | syndrome |= ((ecc_table[i] >> (bit % 32)) & 1) << (i / 2); |
736 | |
737 | return syndrome; |
738 | } |
739 | |
740 | /* |
741 | * Decode data and ecc syndrome to determine what went wrong |
742 | * Note: This can only decode single-bit errors |
743 | */ |
744 | static void sbe_ecc_decode(u32 cap_high, u32 cap_low, u32 cap_ecc, |
745 | int *bad_data_bit, int *bad_ecc_bit) |
746 | { |
747 | int i; |
748 | u8 syndrome; |
749 | |
750 | *bad_data_bit = -1; |
751 | *bad_ecc_bit = -1; |
752 | |
753 | /* |
754 | * Calculate the ECC of the captured data and XOR it with the captured |
755 | * ECC to find an ECC syndrome value we can search for |
756 | */ |
757 | syndrome = calculate_ecc(cap_high, cap_low) ^ cap_ecc; |
758 | |
759 | /* Check if a data line is stuck... */ |
760 | for (i = 0; i < 64; i++) { |
761 | if (syndrome == syndrome_from_bit(i)) { |
762 | *bad_data_bit = i; |
763 | return; |
764 | } |
765 | } |
766 | |
767 | /* If data is correct, check ECC bits for errors... */ |
768 | for (i = 0; i < 8; i++) { |
769 | if ((syndrome >> i) & 0x1) { |
770 | *bad_ecc_bit = i; |
771 | return; |
772 | } |
773 | } |
774 | } |
775 | |
776 | static void mpc85xx_mc_check(struct mem_ctl_info *mci) |
777 | { |
778 | struct mpc85xx_mc_pdata *pdata = mci->pvt_info; |
779 | struct csrow_info *csrow; |
780 | u32 bus_width; |
781 | u32 err_detect; |
782 | u32 syndrome; |
783 | u32 err_addr; |
784 | u32 pfn; |
785 | int row_index; |
786 | u32 cap_high; |
787 | u32 cap_low; |
788 | int bad_data_bit; |
789 | int bad_ecc_bit; |
790 | |
791 | err_detect = in_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DETECT); |
792 | if (!err_detect) |
793 | return; |
794 | |
795 | mpc85xx_mc_printk(mci, KERN_ERR, "Err Detect Register: %#8.8x\n", |
796 | err_detect); |
797 | |
798 | /* no more processing if not ECC bit errors */ |
799 | if (!(err_detect & (DDR_EDE_SBE | DDR_EDE_MBE))) { |
800 | out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DETECT, err_detect); |
801 | return; |
802 | } |
803 | |
804 | syndrome = in_be32(pdata->mc_vbase + MPC85XX_MC_CAPTURE_ECC); |
805 | |
806 | /* Mask off appropriate bits of syndrome based on bus width */ |
807 | bus_width = (in_be32(pdata->mc_vbase + MPC85XX_MC_DDR_SDRAM_CFG) & |
808 | DSC_DBW_MASK) ? 32 : 64; |
809 | if (bus_width == 64) |
810 | syndrome &= 0xff; |
811 | else |
812 | syndrome &= 0xffff; |
813 | |
814 | err_addr = in_be32(pdata->mc_vbase + MPC85XX_MC_CAPTURE_ADDRESS); |
815 | pfn = err_addr >> PAGE_SHIFT; |
816 | |
817 | for (row_index = 0; row_index < mci->nr_csrows; row_index++) { |
818 | csrow = mci->csrows[row_index]; |
819 | if ((pfn >= csrow->first_page) && (pfn <= csrow->last_page)) |
820 | break; |
821 | } |
822 | |
823 | cap_high = in_be32(pdata->mc_vbase + MPC85XX_MC_CAPTURE_DATA_HI); |
824 | cap_low = in_be32(pdata->mc_vbase + MPC85XX_MC_CAPTURE_DATA_LO); |
825 | |
826 | /* |
827 | * Analyze single-bit errors on 64-bit wide buses |
828 | * TODO: Add support for 32-bit wide buses |
829 | */ |
830 | if ((err_detect & DDR_EDE_SBE) && (bus_width == 64)) { |
831 | sbe_ecc_decode(cap_high, cap_low, syndrome, |
832 | &bad_data_bit, &bad_ecc_bit); |
833 | |
834 | if (bad_data_bit != -1) |
835 | mpc85xx_mc_printk(mci, KERN_ERR, |
836 | "Faulty Data bit: %d\n", bad_data_bit); |
837 | if (bad_ecc_bit != -1) |
838 | mpc85xx_mc_printk(mci, KERN_ERR, |
839 | "Faulty ECC bit: %d\n", bad_ecc_bit); |
840 | |
841 | mpc85xx_mc_printk(mci, KERN_ERR, |
842 | "Expected Data / ECC:\t%#8.8x_%08x / %#2.2x\n", |
843 | cap_high ^ (1 << (bad_data_bit - 32)), |
844 | cap_low ^ (1 << bad_data_bit), |
845 | syndrome ^ (1 << bad_ecc_bit)); |
846 | } |
847 | |
848 | mpc85xx_mc_printk(mci, KERN_ERR, |
849 | "Captured Data / ECC:\t%#8.8x_%08x / %#2.2x\n", |
850 | cap_high, cap_low, syndrome); |
851 | mpc85xx_mc_printk(mci, KERN_ERR, "Err addr: %#8.8x\n", err_addr); |
852 | mpc85xx_mc_printk(mci, KERN_ERR, "PFN: %#8.8x\n", pfn); |
853 | |
854 | /* we are out of range */ |
855 | if (row_index == mci->nr_csrows) |
856 | mpc85xx_mc_printk(mci, KERN_ERR, "PFN out of range!\n"); |
857 | |
858 | if (err_detect & DDR_EDE_SBE) |
859 | edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1, |
860 | pfn, err_addr & ~PAGE_MASK, syndrome, |
861 | row_index, 0, -1, |
862 | mci->ctl_name, ""); |
863 | |
864 | if (err_detect & DDR_EDE_MBE) |
865 | edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1, |
866 | pfn, err_addr & ~PAGE_MASK, syndrome, |
867 | row_index, 0, -1, |
868 | mci->ctl_name, ""); |
869 | |
870 | out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DETECT, err_detect); |
871 | } |
872 | |
873 | static irqreturn_t mpc85xx_mc_isr(int irq, void *dev_id) |
874 | { |
875 | struct mem_ctl_info *mci = dev_id; |
876 | struct mpc85xx_mc_pdata *pdata = mci->pvt_info; |
877 | u32 err_detect; |
878 | |
879 | err_detect = in_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DETECT); |
880 | if (!err_detect) |
881 | return IRQ_NONE; |
882 | |
883 | mpc85xx_mc_check(mci); |
884 | |
885 | return IRQ_HANDLED; |
886 | } |
887 | |
888 | static void mpc85xx_init_csrows(struct mem_ctl_info *mci) |
889 | { |
890 | struct mpc85xx_mc_pdata *pdata = mci->pvt_info; |
891 | struct csrow_info *csrow; |
892 | struct dimm_info *dimm; |
893 | u32 sdram_ctl; |
894 | u32 sdtype; |
895 | enum mem_type mtype; |
896 | u32 cs_bnds; |
897 | int index; |
898 | |
899 | sdram_ctl = in_be32(pdata->mc_vbase + MPC85XX_MC_DDR_SDRAM_CFG); |
900 | |
901 | sdtype = sdram_ctl & DSC_SDTYPE_MASK; |
902 | if (sdram_ctl & DSC_RD_EN) { |
903 | switch (sdtype) { |
904 | case DSC_SDTYPE_DDR: |
905 | mtype = MEM_RDDR; |
906 | break; |
907 | case DSC_SDTYPE_DDR2: |
908 | mtype = MEM_RDDR2; |
909 | break; |
910 | case DSC_SDTYPE_DDR3: |
911 | mtype = MEM_RDDR3; |
912 | break; |
913 | default: |
914 | mtype = MEM_UNKNOWN; |
915 | break; |
916 | } |
917 | } else { |
918 | switch (sdtype) { |
919 | case DSC_SDTYPE_DDR: |
920 | mtype = MEM_DDR; |
921 | break; |
922 | case DSC_SDTYPE_DDR2: |
923 | mtype = MEM_DDR2; |
924 | break; |
925 | case DSC_SDTYPE_DDR3: |
926 | mtype = MEM_DDR3; |
927 | break; |
928 | default: |
929 | mtype = MEM_UNKNOWN; |
930 | break; |
931 | } |
932 | } |
933 | |
934 | for (index = 0; index < mci->nr_csrows; index++) { |
935 | u32 start; |
936 | u32 end; |
937 | |
938 | csrow = mci->csrows[index]; |
939 | dimm = csrow->channels[0]->dimm; |
940 | |
941 | cs_bnds = in_be32(pdata->mc_vbase + MPC85XX_MC_CS_BNDS_0 + |
942 | (index * MPC85XX_MC_CS_BNDS_OFS)); |
943 | |
944 | start = (cs_bnds & 0xffff0000) >> 16; |
945 | end = (cs_bnds & 0x0000ffff); |
946 | |
947 | if (start == end) |
948 | continue; /* not populated */ |
949 | |
950 | start <<= (24 - PAGE_SHIFT); |
951 | end <<= (24 - PAGE_SHIFT); |
952 | end |= (1 << (24 - PAGE_SHIFT)) - 1; |
953 | |
954 | csrow->first_page = start; |
955 | csrow->last_page = end; |
956 | |
957 | dimm->nr_pages = end + 1 - start; |
958 | dimm->grain = 8; |
959 | dimm->mtype = mtype; |
960 | dimm->dtype = DEV_UNKNOWN; |
961 | if (sdram_ctl & DSC_X32_EN) |
962 | dimm->dtype = DEV_X32; |
963 | dimm->edac_mode = EDAC_SECDED; |
964 | } |
965 | } |
966 | |
967 | static int mpc85xx_mc_err_probe(struct platform_device *op) |
968 | { |
969 | struct mem_ctl_info *mci; |
970 | struct edac_mc_layer layers[2]; |
971 | struct mpc85xx_mc_pdata *pdata; |
972 | struct resource r; |
973 | u32 sdram_ctl; |
974 | int res; |
975 | |
976 | if (!devres_open_group(&op->dev, mpc85xx_mc_err_probe, GFP_KERNEL)) |
977 | return -ENOMEM; |
978 | |
979 | layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; |
980 | layers[0].size = 4; |
981 | layers[0].is_virt_csrow = true; |
982 | layers[1].type = EDAC_MC_LAYER_CHANNEL; |
983 | layers[1].size = 1; |
984 | layers[1].is_virt_csrow = false; |
985 | mci = edac_mc_alloc(edac_mc_idx, ARRAY_SIZE(layers), layers, |
986 | sizeof(*pdata)); |
987 | if (!mci) { |
988 | devres_release_group(&op->dev, mpc85xx_mc_err_probe); |
989 | return -ENOMEM; |
990 | } |
991 | |
992 | pdata = mci->pvt_info; |
993 | pdata->name = "mpc85xx_mc_err"; |
994 | pdata->irq = NO_IRQ; |
995 | mci->pdev = &op->dev; |
996 | pdata->edac_idx = edac_mc_idx++; |
997 | dev_set_drvdata(mci->pdev, mci); |
998 | mci->ctl_name = pdata->name; |
999 | mci->dev_name = pdata->name; |
1000 | |
1001 | res = of_address_to_resource(op->dev.of_node, 0, &r); |
1002 | if (res) { |
1003 | printk(KERN_ERR "%s: Unable to get resource for MC err regs\n", |
1004 | __func__); |
1005 | goto err; |
1006 | } |
1007 | |
1008 | if (!devm_request_mem_region(&op->dev, r.start, resource_size(&r), |
1009 | pdata->name)) { |
1010 | printk(KERN_ERR "%s: Error while requesting mem region\n", |
1011 | __func__); |
1012 | res = -EBUSY; |
1013 | goto err; |
1014 | } |
1015 | |
1016 | pdata->mc_vbase = devm_ioremap(&op->dev, r.start, resource_size(&r)); |
1017 | if (!pdata->mc_vbase) { |
1018 | printk(KERN_ERR "%s: Unable to setup MC err regs\n", __func__); |
1019 | res = -ENOMEM; |
1020 | goto err; |
1021 | } |
1022 | |
1023 | sdram_ctl = in_be32(pdata->mc_vbase + MPC85XX_MC_DDR_SDRAM_CFG); |
1024 | if (!(sdram_ctl & DSC_ECC_EN)) { |
1025 | /* no ECC */ |
1026 | printk(KERN_WARNING "%s: No ECC DIMMs discovered\n", __func__); |
1027 | res = -ENODEV; |
1028 | goto err; |
1029 | } |
1030 | |
1031 | edac_dbg(3, "init mci\n"); |
1032 | mci->mtype_cap = MEM_FLAG_RDDR | MEM_FLAG_RDDR2 | |
1033 | MEM_FLAG_DDR | MEM_FLAG_DDR2; |
1034 | mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED; |
1035 | mci->edac_cap = EDAC_FLAG_SECDED; |
1036 | mci->mod_name = EDAC_MOD_STR; |
1037 | mci->mod_ver = MPC85XX_REVISION; |
1038 | |
1039 | if (edac_op_state == EDAC_OPSTATE_POLL) |
1040 | mci->edac_check = mpc85xx_mc_check; |
1041 | |
1042 | mci->ctl_page_to_phys = NULL; |
1043 | |
1044 | mci->scrub_mode = SCRUB_SW_SRC; |
1045 | |
1046 | mpc85xx_init_csrows(mci); |
1047 | |
1048 | /* store the original error disable bits */ |
1049 | orig_ddr_err_disable = |
1050 | in_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DISABLE); |
1051 | out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DISABLE, 0); |
1052 | |
1053 | /* clear all error bits */ |
1054 | out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DETECT, ~0); |
1055 | |
1056 | if (edac_mc_add_mc(mci)) { |
1057 | edac_dbg(3, "failed edac_mc_add_mc()\n"); |
1058 | goto err; |
1059 | } |
1060 | |
1061 | if (mpc85xx_create_sysfs_attributes(mci)) { |
1062 | edac_mc_del_mc(mci->pdev); |
1063 | edac_dbg(3, "failed edac_mc_add_mc()\n"); |
1064 | goto err; |
1065 | } |
1066 | |
1067 | if (edac_op_state == EDAC_OPSTATE_INT) { |
1068 | out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_INT_EN, |
1069 | DDR_EIE_MBEE | DDR_EIE_SBEE); |
1070 | |
1071 | /* store the original error management threshold */ |
1072 | orig_ddr_err_sbe = in_be32(pdata->mc_vbase + |
1073 | MPC85XX_MC_ERR_SBE) & 0xff0000; |
1074 | |
1075 | /* set threshold to 1 error per interrupt */ |
1076 | out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_SBE, 0x10000); |
1077 | |
1078 | /* register interrupts */ |
1079 | pdata->irq = irq_of_parse_and_map(op->dev.of_node, 0); |
1080 | res = devm_request_irq(&op->dev, pdata->irq, |
1081 | mpc85xx_mc_isr, |
1082 | IRQF_DISABLED | IRQF_SHARED, |
1083 | "[EDAC] MC err", mci); |
1084 | if (res < 0) { |
1085 | printk(KERN_ERR "%s: Unable to request irq %d for " |
1086 | "MPC85xx DRAM ERR\n", __func__, pdata->irq); |
1087 | irq_dispose_mapping(pdata->irq); |
1088 | res = -ENODEV; |
1089 | goto err2; |
1090 | } |
1091 | |
1092 | printk(KERN_INFO EDAC_MOD_STR " acquired irq %d for MC\n", |
1093 | pdata->irq); |
1094 | } |
1095 | |
1096 | devres_remove_group(&op->dev, mpc85xx_mc_err_probe); |
1097 | edac_dbg(3, "success\n"); |
1098 | printk(KERN_INFO EDAC_MOD_STR " MC err registered\n"); |
1099 | |
1100 | return 0; |
1101 | |
1102 | err2: |
1103 | edac_mc_del_mc(&op->dev); |
1104 | err: |
1105 | devres_release_group(&op->dev, mpc85xx_mc_err_probe); |
1106 | edac_mc_free(mci); |
1107 | return res; |
1108 | } |
1109 | |
1110 | static int mpc85xx_mc_err_remove(struct platform_device *op) |
1111 | { |
1112 | struct mem_ctl_info *mci = dev_get_drvdata(&op->dev); |
1113 | struct mpc85xx_mc_pdata *pdata = mci->pvt_info; |
1114 | |
1115 | edac_dbg(0, "\n"); |
1116 | |
1117 | if (edac_op_state == EDAC_OPSTATE_INT) { |
1118 | out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_INT_EN, 0); |
1119 | irq_dispose_mapping(pdata->irq); |
1120 | } |
1121 | |
1122 | out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DISABLE, |
1123 | orig_ddr_err_disable); |
1124 | out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_SBE, orig_ddr_err_sbe); |
1125 | |
1126 | mpc85xx_remove_sysfs_attributes(mci); |
1127 | edac_mc_del_mc(&op->dev); |
1128 | edac_mc_free(mci); |
1129 | return 0; |
1130 | } |
1131 | |
1132 | static struct of_device_id mpc85xx_mc_err_of_match[] = { |
1133 | /* deprecate the fsl,85.. forms in the future, 2.6.30? */ |
1134 | { .compatible = "fsl,8540-memory-controller", }, |
1135 | { .compatible = "fsl,8541-memory-controller", }, |
1136 | { .compatible = "fsl,8544-memory-controller", }, |
1137 | { .compatible = "fsl,8548-memory-controller", }, |
1138 | { .compatible = "fsl,8555-memory-controller", }, |
1139 | { .compatible = "fsl,8568-memory-controller", }, |
1140 | { .compatible = "fsl,mpc8536-memory-controller", }, |
1141 | { .compatible = "fsl,mpc8540-memory-controller", }, |
1142 | { .compatible = "fsl,mpc8541-memory-controller", }, |
1143 | { .compatible = "fsl,mpc8544-memory-controller", }, |
1144 | { .compatible = "fsl,mpc8548-memory-controller", }, |
1145 | { .compatible = "fsl,mpc8555-memory-controller", }, |
1146 | { .compatible = "fsl,mpc8560-memory-controller", }, |
1147 | { .compatible = "fsl,mpc8568-memory-controller", }, |
1148 | { .compatible = "fsl,mpc8569-memory-controller", }, |
1149 | { .compatible = "fsl,mpc8572-memory-controller", }, |
1150 | { .compatible = "fsl,mpc8349-memory-controller", }, |
1151 | { .compatible = "fsl,p1020-memory-controller", }, |
1152 | { .compatible = "fsl,p1021-memory-controller", }, |
1153 | { .compatible = "fsl,p2020-memory-controller", }, |
1154 | { .compatible = "fsl,qoriq-memory-controller", }, |
1155 | {}, |
1156 | }; |
1157 | MODULE_DEVICE_TABLE(of, mpc85xx_mc_err_of_match); |
1158 | |
1159 | static struct platform_driver mpc85xx_mc_err_driver = { |
1160 | .probe = mpc85xx_mc_err_probe, |
1161 | .remove = mpc85xx_mc_err_remove, |
1162 | .driver = { |
1163 | .name = "mpc85xx_mc_err", |
1164 | .owner = THIS_MODULE, |
1165 | .of_match_table = mpc85xx_mc_err_of_match, |
1166 | }, |
1167 | }; |
1168 | |
1169 | #ifdef CONFIG_FSL_SOC_BOOKE |
1170 | static void __init mpc85xx_mc_clear_rfxe(void *data) |
1171 | { |
1172 | orig_hid1[smp_processor_id()] = mfspr(SPRN_HID1); |
1173 | mtspr(SPRN_HID1, (orig_hid1[smp_processor_id()] & ~HID1_RFXE)); |
1174 | } |
1175 | #endif |
1176 | |
1177 | static int __init mpc85xx_mc_init(void) |
1178 | { |
1179 | int res = 0; |
1180 | u32 pvr = 0; |
1181 | |
1182 | printk(KERN_INFO "Freescale(R) MPC85xx EDAC driver, " |
1183 | "(C) 2006 Montavista Software\n"); |
1184 | |
1185 | /* make sure error reporting method is sane */ |
1186 | switch (edac_op_state) { |
1187 | case EDAC_OPSTATE_POLL: |
1188 | case EDAC_OPSTATE_INT: |
1189 | break; |
1190 | default: |
1191 | edac_op_state = EDAC_OPSTATE_INT; |
1192 | break; |
1193 | } |
1194 | |
1195 | res = platform_driver_register(&mpc85xx_mc_err_driver); |
1196 | if (res) |
1197 | printk(KERN_WARNING EDAC_MOD_STR "MC fails to register\n"); |
1198 | |
1199 | res = platform_driver_register(&mpc85xx_l2_err_driver); |
1200 | if (res) |
1201 | printk(KERN_WARNING EDAC_MOD_STR "L2 fails to register\n"); |
1202 | |
1203 | #ifdef CONFIG_FSL_SOC_BOOKE |
1204 | pvr = mfspr(SPRN_PVR); |
1205 | |
1206 | if ((PVR_VER(pvr) == PVR_VER_E500V1) || |
1207 | (PVR_VER(pvr) == PVR_VER_E500V2)) { |
1208 | /* |
1209 | * need to clear HID1[RFXE] to disable machine check int |
1210 | * so we can catch it |
1211 | */ |
1212 | if (edac_op_state == EDAC_OPSTATE_INT) |
1213 | on_each_cpu(mpc85xx_mc_clear_rfxe, NULL, 0); |
1214 | } |
1215 | #endif |
1216 | |
1217 | return 0; |
1218 | } |
1219 | |
1220 | module_init(mpc85xx_mc_init); |
1221 | |
1222 | #ifdef CONFIG_FSL_SOC_BOOKE |
1223 | static void __exit mpc85xx_mc_restore_hid1(void *data) |
1224 | { |
1225 | mtspr(SPRN_HID1, orig_hid1[smp_processor_id()]); |
1226 | } |
1227 | #endif |
1228 | |
1229 | static void __exit mpc85xx_mc_exit(void) |
1230 | { |
1231 | #ifdef CONFIG_FSL_SOC_BOOKE |
1232 | u32 pvr = mfspr(SPRN_PVR); |
1233 | |
1234 | if ((PVR_VER(pvr) == PVR_VER_E500V1) || |
1235 | (PVR_VER(pvr) == PVR_VER_E500V2)) { |
1236 | on_each_cpu(mpc85xx_mc_restore_hid1, NULL, 0); |
1237 | } |
1238 | #endif |
1239 | platform_driver_unregister(&mpc85xx_l2_err_driver); |
1240 | platform_driver_unregister(&mpc85xx_mc_err_driver); |
1241 | } |
1242 | |
1243 | module_exit(mpc85xx_mc_exit); |
1244 | |
1245 | MODULE_LICENSE("GPL"); |
1246 | MODULE_AUTHOR("Montavista Software, Inc."); |
1247 | module_param(edac_op_state, int, 0444); |
1248 | MODULE_PARM_DESC(edac_op_state, |
1249 | "EDAC Error Reporting state: 0=Poll, 2=Interrupt"); |
1250 |
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