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1 | /* |
2 | * Freescale MPC85xx Memory Controller kenel module |
3 | * Author: Dave Jiang <djiang@mvista.com> |
4 | * |
5 | * 2006-2007 (c) MontaVista Software, Inc. This file is licensed under |
6 | * the terms of the GNU General Public License version 2. This program |
7 | * is licensed "as is" without any warranty of any kind, whether express |
8 | * or implied. |
9 | * |
10 | */ |
11 | #ifndef _MPC85XX_EDAC_H_ |
12 | #define _MPC85XX_EDAC_H_ |
13 | |
14 | #define MPC85XX_REVISION " Ver: 2.0.0" |
15 | #define EDAC_MOD_STR "MPC85xx_edac" |
16 | |
17 | #define mpc85xx_printk(level, fmt, arg...) \ |
18 | edac_printk(level, "MPC85xx", fmt, ##arg) |
19 | |
20 | #define mpc85xx_mc_printk(mci, level, fmt, arg...) \ |
21 | edac_mc_chipset_printk(mci, level, "MPC85xx", fmt, ##arg) |
22 | |
23 | /* |
24 | * DRAM error defines |
25 | */ |
26 | |
27 | /* DDR_SDRAM_CFG */ |
28 | #define MPC85XX_MC_DDR_SDRAM_CFG 0x0110 |
29 | #define MPC85XX_MC_CS_BNDS_0 0x0000 |
30 | #define MPC85XX_MC_CS_BNDS_1 0x0008 |
31 | #define MPC85XX_MC_CS_BNDS_2 0x0010 |
32 | #define MPC85XX_MC_CS_BNDS_3 0x0018 |
33 | #define MPC85XX_MC_CS_BNDS_OFS 0x0008 |
34 | |
35 | #define MPC85XX_MC_DATA_ERR_INJECT_HI 0x0e00 |
36 | #define MPC85XX_MC_DATA_ERR_INJECT_LO 0x0e04 |
37 | #define MPC85XX_MC_ECC_ERR_INJECT 0x0e08 |
38 | #define MPC85XX_MC_CAPTURE_DATA_HI 0x0e20 |
39 | #define MPC85XX_MC_CAPTURE_DATA_LO 0x0e24 |
40 | #define MPC85XX_MC_CAPTURE_ECC 0x0e28 |
41 | #define MPC85XX_MC_ERR_DETECT 0x0e40 |
42 | #define MPC85XX_MC_ERR_DISABLE 0x0e44 |
43 | #define MPC85XX_MC_ERR_INT_EN 0x0e48 |
44 | #define MPC85XX_MC_CAPTURE_ATRIBUTES 0x0e4c |
45 | #define MPC85XX_MC_CAPTURE_ADDRESS 0x0e50 |
46 | #define MPC85XX_MC_ERR_SBE 0x0e58 |
47 | |
48 | #define DSC_MEM_EN 0x80000000 |
49 | #define DSC_ECC_EN 0x20000000 |
50 | #define DSC_RD_EN 0x10000000 |
51 | #define DSC_DBW_MASK 0x00180000 |
52 | #define DSC_DBW_32 0x00080000 |
53 | #define DSC_DBW_64 0x00000000 |
54 | |
55 | #define DSC_SDTYPE_MASK 0x07000000 |
56 | |
57 | #define DSC_SDTYPE_DDR 0x02000000 |
58 | #define DSC_SDTYPE_DDR2 0x03000000 |
59 | #define DSC_SDTYPE_DDR3 0x07000000 |
60 | #define DSC_X32_EN 0x00000020 |
61 | |
62 | /* Err_Int_En */ |
63 | #define DDR_EIE_MSEE 0x1 /* memory select */ |
64 | #define DDR_EIE_SBEE 0x4 /* single-bit ECC error */ |
65 | #define DDR_EIE_MBEE 0x8 /* multi-bit ECC error */ |
66 | |
67 | /* Err_Detect */ |
68 | #define DDR_EDE_MSE 0x1 /* memory select */ |
69 | #define DDR_EDE_SBE 0x4 /* single-bit ECC error */ |
70 | #define DDR_EDE_MBE 0x8 /* multi-bit ECC error */ |
71 | #define DDR_EDE_MME 0x80000000 /* multiple memory errors */ |
72 | |
73 | /* Err_Disable */ |
74 | #define DDR_EDI_MSED 0x1 /* memory select disable */ |
75 | #define DDR_EDI_SBED 0x4 /* single-bit ECC error disable */ |
76 | #define DDR_EDI_MBED 0x8 /* multi-bit ECC error disable */ |
77 | |
78 | /* |
79 | * L2 Err defines |
80 | */ |
81 | #define MPC85XX_L2_ERRINJHI 0x0000 |
82 | #define MPC85XX_L2_ERRINJLO 0x0004 |
83 | #define MPC85XX_L2_ERRINJCTL 0x0008 |
84 | #define MPC85XX_L2_CAPTDATAHI 0x0020 |
85 | #define MPC85XX_L2_CAPTDATALO 0x0024 |
86 | #define MPC85XX_L2_CAPTECC 0x0028 |
87 | #define MPC85XX_L2_ERRDET 0x0040 |
88 | #define MPC85XX_L2_ERRDIS 0x0044 |
89 | #define MPC85XX_L2_ERRINTEN 0x0048 |
90 | #define MPC85XX_L2_ERRATTR 0x004c |
91 | #define MPC85XX_L2_ERRADDR 0x0050 |
92 | #define MPC85XX_L2_ERRCTL 0x0058 |
93 | |
94 | /* Error Interrupt Enable */ |
95 | #define L2_EIE_L2CFGINTEN 0x1 |
96 | #define L2_EIE_SBECCINTEN 0x4 |
97 | #define L2_EIE_MBECCINTEN 0x8 |
98 | #define L2_EIE_TPARINTEN 0x10 |
99 | #define L2_EIE_MASK (L2_EIE_L2CFGINTEN | L2_EIE_SBECCINTEN | \ |
100 | L2_EIE_MBECCINTEN | L2_EIE_TPARINTEN) |
101 | |
102 | /* Error Detect */ |
103 | #define L2_EDE_L2CFGERR 0x1 |
104 | #define L2_EDE_SBECCERR 0x4 |
105 | #define L2_EDE_MBECCERR 0x8 |
106 | #define L2_EDE_TPARERR 0x10 |
107 | #define L2_EDE_MULL2ERR 0x80000000 |
108 | |
109 | #define L2_EDE_CE_MASK L2_EDE_SBECCERR |
110 | #define L2_EDE_UE_MASK (L2_EDE_L2CFGERR | L2_EDE_MBECCERR | \ |
111 | L2_EDE_TPARERR) |
112 | #define L2_EDE_MASK (L2_EDE_L2CFGERR | L2_EDE_SBECCERR | \ |
113 | L2_EDE_MBECCERR | L2_EDE_TPARERR | L2_EDE_MULL2ERR) |
114 | |
115 | /* |
116 | * PCI Err defines |
117 | */ |
118 | #define PCI_EDE_TOE 0x00000001 |
119 | #define PCI_EDE_SCM 0x00000002 |
120 | #define PCI_EDE_IRMSV 0x00000004 |
121 | #define PCI_EDE_ORMSV 0x00000008 |
122 | #define PCI_EDE_OWMSV 0x00000010 |
123 | #define PCI_EDE_TGT_ABRT 0x00000020 |
124 | #define PCI_EDE_MST_ABRT 0x00000040 |
125 | #define PCI_EDE_TGT_PERR 0x00000080 |
126 | #define PCI_EDE_MST_PERR 0x00000100 |
127 | #define PCI_EDE_RCVD_SERR 0x00000200 |
128 | #define PCI_EDE_ADDR_PERR 0x00000400 |
129 | #define PCI_EDE_MULTI_ERR 0x80000000 |
130 | |
131 | #define PCI_EDE_PERR_MASK (PCI_EDE_TGT_PERR | PCI_EDE_MST_PERR | \ |
132 | PCI_EDE_ADDR_PERR) |
133 | |
134 | #define MPC85XX_PCI_ERR_DR 0x0000 |
135 | #define MPC85XX_PCI_ERR_CAP_DR 0x0004 |
136 | #define MPC85XX_PCI_ERR_EN 0x0008 |
137 | #define MPC85XX_PCI_ERR_ATTRIB 0x000c |
138 | #define MPC85XX_PCI_ERR_ADDR 0x0010 |
139 | #define MPC85XX_PCI_ERR_EXT_ADDR 0x0014 |
140 | #define MPC85XX_PCI_ERR_DL 0x0018 |
141 | #define MPC85XX_PCI_ERR_DH 0x001c |
142 | #define MPC85XX_PCI_GAS_TIMR 0x0020 |
143 | #define MPC85XX_PCI_PCIX_TIMR 0x0024 |
144 | |
145 | struct mpc85xx_mc_pdata { |
146 | char *name; |
147 | int edac_idx; |
148 | void __iomem *mc_vbase; |
149 | int irq; |
150 | }; |
151 | |
152 | struct mpc85xx_l2_pdata { |
153 | char *name; |
154 | int edac_idx; |
155 | void __iomem *l2_vbase; |
156 | int irq; |
157 | }; |
158 | |
159 | struct mpc85xx_pci_pdata { |
160 | char *name; |
161 | int edac_idx; |
162 | void __iomem *pci_vbase; |
163 | int irq; |
164 | }; |
165 | |
166 | #endif |
167 |
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