Root/
1 | /* |
2 | * Driver for Intel MSIC |
3 | * |
4 | * Copyright (C) 2011, Intel Corporation |
5 | * Author: Mika Westerberg <mika.westerberg@linux.intel.com> |
6 | * |
7 | * This program is free software; you can redistribute it and/or modify |
8 | * it under the terms of the GNU General Public License version 2 as |
9 | * published by the Free Software Foundation. |
10 | */ |
11 | |
12 | #include <linux/err.h> |
13 | #include <linux/gpio.h> |
14 | #include <linux/io.h> |
15 | #include <linux/module.h> |
16 | #include <linux/mfd/core.h> |
17 | #include <linux/mfd/intel_msic.h> |
18 | #include <linux/platform_device.h> |
19 | #include <linux/slab.h> |
20 | |
21 | #include <asm/intel_scu_ipc.h> |
22 | |
23 | #define MSIC_VENDOR(id) ((id >> 6) & 3) |
24 | #define MSIC_VERSION(id) (id & 0x3f) |
25 | #define MSIC_MAJOR(id) ('A' + ((id >> 3) & 7)) |
26 | #define MSIC_MINOR(id) (id & 7) |
27 | |
28 | /* |
29 | * MSIC interrupt tree is readable from SRAM at INTEL_MSIC_IRQ_PHYS_BASE. |
30 | * Since IRQ block starts from address 0x002 we need to substract that from |
31 | * the actual IRQ status register address. |
32 | */ |
33 | #define MSIC_IRQ_STATUS(x) (INTEL_MSIC_IRQ_PHYS_BASE + ((x) - 2)) |
34 | #define MSIC_IRQ_STATUS_ACCDET MSIC_IRQ_STATUS(INTEL_MSIC_ACCDET) |
35 | |
36 | /* |
37 | * The SCU hardware has limitation of 16 bytes per read/write buffer on |
38 | * Medfield. |
39 | */ |
40 | #define SCU_IPC_RWBUF_LIMIT 16 |
41 | |
42 | /** |
43 | * struct intel_msic - an MSIC MFD instance |
44 | * @pdev: pointer to the platform device |
45 | * @vendor: vendor ID |
46 | * @version: chip version |
47 | * @irq_base: base address of the mapped MSIC SRAM interrupt tree |
48 | */ |
49 | struct intel_msic { |
50 | struct platform_device *pdev; |
51 | unsigned vendor; |
52 | unsigned version; |
53 | void __iomem *irq_base; |
54 | }; |
55 | |
56 | static struct resource msic_touch_resources[] = { |
57 | { |
58 | .flags = IORESOURCE_IRQ, |
59 | }, |
60 | }; |
61 | |
62 | static struct resource msic_adc_resources[] = { |
63 | { |
64 | .flags = IORESOURCE_IRQ, |
65 | }, |
66 | }; |
67 | |
68 | static struct resource msic_battery_resources[] = { |
69 | { |
70 | .flags = IORESOURCE_IRQ, |
71 | }, |
72 | }; |
73 | |
74 | static struct resource msic_gpio_resources[] = { |
75 | { |
76 | .flags = IORESOURCE_IRQ, |
77 | }, |
78 | }; |
79 | |
80 | static struct resource msic_audio_resources[] = { |
81 | { |
82 | .name = "IRQ", |
83 | .flags = IORESOURCE_IRQ, |
84 | }, |
85 | /* |
86 | * We will pass IRQ_BASE to the driver now but this can be removed |
87 | * when/if the driver starts to use intel_msic_irq_read(). |
88 | */ |
89 | { |
90 | .name = "IRQ_BASE", |
91 | .flags = IORESOURCE_MEM, |
92 | .start = MSIC_IRQ_STATUS_ACCDET, |
93 | .end = MSIC_IRQ_STATUS_ACCDET, |
94 | }, |
95 | }; |
96 | |
97 | static struct resource msic_hdmi_resources[] = { |
98 | { |
99 | .flags = IORESOURCE_IRQ, |
100 | }, |
101 | }; |
102 | |
103 | static struct resource msic_thermal_resources[] = { |
104 | { |
105 | .flags = IORESOURCE_IRQ, |
106 | }, |
107 | }; |
108 | |
109 | static struct resource msic_power_btn_resources[] = { |
110 | { |
111 | .flags = IORESOURCE_IRQ, |
112 | }, |
113 | }; |
114 | |
115 | static struct resource msic_ocd_resources[] = { |
116 | { |
117 | .flags = IORESOURCE_IRQ, |
118 | }, |
119 | }; |
120 | |
121 | /* |
122 | * Devices that are part of the MSIC and are available via firmware |
123 | * populated SFI DEVS table. |
124 | */ |
125 | static struct mfd_cell msic_devs[] = { |
126 | [INTEL_MSIC_BLOCK_TOUCH] = { |
127 | .name = "msic_touch", |
128 | .num_resources = ARRAY_SIZE(msic_touch_resources), |
129 | .resources = msic_touch_resources, |
130 | }, |
131 | [INTEL_MSIC_BLOCK_ADC] = { |
132 | .name = "msic_adc", |
133 | .num_resources = ARRAY_SIZE(msic_adc_resources), |
134 | .resources = msic_adc_resources, |
135 | }, |
136 | [INTEL_MSIC_BLOCK_BATTERY] = { |
137 | .name = "msic_battery", |
138 | .num_resources = ARRAY_SIZE(msic_battery_resources), |
139 | .resources = msic_battery_resources, |
140 | }, |
141 | [INTEL_MSIC_BLOCK_GPIO] = { |
142 | .name = "msic_gpio", |
143 | .num_resources = ARRAY_SIZE(msic_gpio_resources), |
144 | .resources = msic_gpio_resources, |
145 | }, |
146 | [INTEL_MSIC_BLOCK_AUDIO] = { |
147 | .name = "msic_audio", |
148 | .num_resources = ARRAY_SIZE(msic_audio_resources), |
149 | .resources = msic_audio_resources, |
150 | }, |
151 | [INTEL_MSIC_BLOCK_HDMI] = { |
152 | .name = "msic_hdmi", |
153 | .num_resources = ARRAY_SIZE(msic_hdmi_resources), |
154 | .resources = msic_hdmi_resources, |
155 | }, |
156 | [INTEL_MSIC_BLOCK_THERMAL] = { |
157 | .name = "msic_thermal", |
158 | .num_resources = ARRAY_SIZE(msic_thermal_resources), |
159 | .resources = msic_thermal_resources, |
160 | }, |
161 | [INTEL_MSIC_BLOCK_POWER_BTN] = { |
162 | .name = "msic_power_btn", |
163 | .num_resources = ARRAY_SIZE(msic_power_btn_resources), |
164 | .resources = msic_power_btn_resources, |
165 | }, |
166 | [INTEL_MSIC_BLOCK_OCD] = { |
167 | .name = "msic_ocd", |
168 | .num_resources = ARRAY_SIZE(msic_ocd_resources), |
169 | .resources = msic_ocd_resources, |
170 | }, |
171 | }; |
172 | |
173 | /* |
174 | * Other MSIC related devices which are not directly available via SFI DEVS |
175 | * table. These can be pseudo devices, regulators etc. which are needed for |
176 | * different purposes. |
177 | * |
178 | * These devices appear only after the MSIC driver itself is initialized so |
179 | * we can guarantee that the SCU IPC interface is ready. |
180 | */ |
181 | static struct mfd_cell msic_other_devs[] = { |
182 | /* Audio codec in the MSIC */ |
183 | { |
184 | .id = -1, |
185 | .name = "sn95031", |
186 | }, |
187 | }; |
188 | |
189 | /** |
190 | * intel_msic_reg_read - read a single MSIC register |
191 | * @reg: register to read |
192 | * @val: register value is placed here |
193 | * |
194 | * Read a single register from MSIC. Returns %0 on success and negative |
195 | * errno in case of failure. |
196 | * |
197 | * Function may sleep. |
198 | */ |
199 | int intel_msic_reg_read(unsigned short reg, u8 *val) |
200 | { |
201 | return intel_scu_ipc_ioread8(reg, val); |
202 | } |
203 | EXPORT_SYMBOL_GPL(intel_msic_reg_read); |
204 | |
205 | /** |
206 | * intel_msic_reg_write - write a single MSIC register |
207 | * @reg: register to write |
208 | * @val: value to write to that register |
209 | * |
210 | * Write a single MSIC register. Returns 0 on success and negative |
211 | * errno in case of failure. |
212 | * |
213 | * Function may sleep. |
214 | */ |
215 | int intel_msic_reg_write(unsigned short reg, u8 val) |
216 | { |
217 | return intel_scu_ipc_iowrite8(reg, val); |
218 | } |
219 | EXPORT_SYMBOL_GPL(intel_msic_reg_write); |
220 | |
221 | /** |
222 | * intel_msic_reg_update - update a single MSIC register |
223 | * @reg: register to update |
224 | * @val: value to write to the register |
225 | * @mask: specifies which of the bits are updated (%0 = don't update, |
226 | * %1 = update) |
227 | * |
228 | * Perform an update to a register @reg. @mask is used to specify which |
229 | * bits are updated. Returns %0 in case of success and negative errno in |
230 | * case of failure. |
231 | * |
232 | * Function may sleep. |
233 | */ |
234 | int intel_msic_reg_update(unsigned short reg, u8 val, u8 mask) |
235 | { |
236 | return intel_scu_ipc_update_register(reg, val, mask); |
237 | } |
238 | EXPORT_SYMBOL_GPL(intel_msic_reg_update); |
239 | |
240 | /** |
241 | * intel_msic_bulk_read - read an array of registers |
242 | * @reg: array of register addresses to read |
243 | * @buf: array where the read values are placed |
244 | * @count: number of registers to read |
245 | * |
246 | * Function reads @count registers from the MSIC using addresses passed in |
247 | * @reg. Read values are placed in @buf. Reads are performed atomically |
248 | * wrt. MSIC. |
249 | * |
250 | * Returns %0 in case of success and negative errno in case of failure. |
251 | * |
252 | * Function may sleep. |
253 | */ |
254 | int intel_msic_bulk_read(unsigned short *reg, u8 *buf, size_t count) |
255 | { |
256 | if (WARN_ON(count > SCU_IPC_RWBUF_LIMIT)) |
257 | return -EINVAL; |
258 | |
259 | return intel_scu_ipc_readv(reg, buf, count); |
260 | } |
261 | EXPORT_SYMBOL_GPL(intel_msic_bulk_read); |
262 | |
263 | /** |
264 | * intel_msic_bulk_write - write an array of values to the MSIC registers |
265 | * @reg: array of registers to write |
266 | * @buf: values to write to each register |
267 | * @count: number of registers to write |
268 | * |
269 | * Function writes @count registers in @buf to MSIC. Writes are performed |
270 | * atomically wrt MSIC. Returns %0 in case of success and negative errno in |
271 | * case of failure. |
272 | * |
273 | * Function may sleep. |
274 | */ |
275 | int intel_msic_bulk_write(unsigned short *reg, u8 *buf, size_t count) |
276 | { |
277 | if (WARN_ON(count > SCU_IPC_RWBUF_LIMIT)) |
278 | return -EINVAL; |
279 | |
280 | return intel_scu_ipc_writev(reg, buf, count); |
281 | } |
282 | EXPORT_SYMBOL_GPL(intel_msic_bulk_write); |
283 | |
284 | /** |
285 | * intel_msic_irq_read - read a register from an MSIC interrupt tree |
286 | * @msic: MSIC instance |
287 | * @reg: interrupt register (between %INTEL_MSIC_IRQLVL1 and |
288 | * %INTEL_MSIC_RESETIRQ2) |
289 | * @val: value of the register is placed here |
290 | * |
291 | * This function can be used by an MSIC subdevice interrupt handler to read |
292 | * a register value from the MSIC interrupt tree. In this way subdevice |
293 | * drivers don't have to map in the interrupt tree themselves but can just |
294 | * call this function instead. |
295 | * |
296 | * Function doesn't sleep and is callable from interrupt context. |
297 | * |
298 | * Returns %-EINVAL if @reg is outside of the allowed register region. |
299 | */ |
300 | int intel_msic_irq_read(struct intel_msic *msic, unsigned short reg, u8 *val) |
301 | { |
302 | if (WARN_ON(reg < INTEL_MSIC_IRQLVL1 || reg > INTEL_MSIC_RESETIRQ2)) |
303 | return -EINVAL; |
304 | |
305 | *val = readb(msic->irq_base + (reg - INTEL_MSIC_IRQLVL1)); |
306 | return 0; |
307 | } |
308 | EXPORT_SYMBOL_GPL(intel_msic_irq_read); |
309 | |
310 | static int intel_msic_init_devices(struct intel_msic *msic) |
311 | { |
312 | struct platform_device *pdev = msic->pdev; |
313 | struct intel_msic_platform_data *pdata = pdev->dev.platform_data; |
314 | int ret, i; |
315 | |
316 | if (pdata->gpio) { |
317 | struct mfd_cell *cell = &msic_devs[INTEL_MSIC_BLOCK_GPIO]; |
318 | |
319 | cell->platform_data = pdata->gpio; |
320 | cell->pdata_size = sizeof(*pdata->gpio); |
321 | } |
322 | |
323 | if (pdata->ocd) { |
324 | unsigned gpio = pdata->ocd->gpio; |
325 | |
326 | ret = gpio_request_one(gpio, GPIOF_IN, "ocd_gpio"); |
327 | if (ret) { |
328 | dev_err(&pdev->dev, "failed to register OCD GPIO\n"); |
329 | return ret; |
330 | } |
331 | |
332 | ret = gpio_to_irq(gpio); |
333 | if (ret < 0) { |
334 | dev_err(&pdev->dev, "no IRQ number for OCD GPIO\n"); |
335 | gpio_free(gpio); |
336 | return ret; |
337 | } |
338 | |
339 | /* Update the IRQ number for the OCD */ |
340 | pdata->irq[INTEL_MSIC_BLOCK_OCD] = ret; |
341 | } |
342 | |
343 | for (i = 0; i < ARRAY_SIZE(msic_devs); i++) { |
344 | if (!pdata->irq[i]) |
345 | continue; |
346 | |
347 | ret = mfd_add_devices(&pdev->dev, -1, &msic_devs[i], 1, NULL, |
348 | pdata->irq[i], NULL); |
349 | if (ret) |
350 | goto fail; |
351 | } |
352 | |
353 | ret = mfd_add_devices(&pdev->dev, 0, msic_other_devs, |
354 | ARRAY_SIZE(msic_other_devs), NULL, 0, NULL); |
355 | if (ret) |
356 | goto fail; |
357 | |
358 | return 0; |
359 | |
360 | fail: |
361 | mfd_remove_devices(&pdev->dev); |
362 | if (pdata->ocd) |
363 | gpio_free(pdata->ocd->gpio); |
364 | |
365 | return ret; |
366 | } |
367 | |
368 | static void intel_msic_remove_devices(struct intel_msic *msic) |
369 | { |
370 | struct platform_device *pdev = msic->pdev; |
371 | struct intel_msic_platform_data *pdata = pdev->dev.platform_data; |
372 | |
373 | mfd_remove_devices(&pdev->dev); |
374 | |
375 | if (pdata->ocd) |
376 | gpio_free(pdata->ocd->gpio); |
377 | } |
378 | |
379 | static int intel_msic_probe(struct platform_device *pdev) |
380 | { |
381 | struct intel_msic_platform_data *pdata = pdev->dev.platform_data; |
382 | struct intel_msic *msic; |
383 | struct resource *res; |
384 | u8 id0, id1; |
385 | int ret; |
386 | |
387 | if (!pdata) { |
388 | dev_err(&pdev->dev, "no platform data passed\n"); |
389 | return -EINVAL; |
390 | } |
391 | |
392 | /* First validate that we have an MSIC in place */ |
393 | ret = intel_scu_ipc_ioread8(INTEL_MSIC_ID0, &id0); |
394 | if (ret) { |
395 | dev_err(&pdev->dev, "failed to identify the MSIC chip (ID0)\n"); |
396 | return -ENXIO; |
397 | } |
398 | |
399 | ret = intel_scu_ipc_ioread8(INTEL_MSIC_ID1, &id1); |
400 | if (ret) { |
401 | dev_err(&pdev->dev, "failed to identify the MSIC chip (ID1)\n"); |
402 | return -ENXIO; |
403 | } |
404 | |
405 | if (MSIC_VENDOR(id0) != MSIC_VENDOR(id1)) { |
406 | dev_err(&pdev->dev, "invalid vendor ID: %x, %x\n", id0, id1); |
407 | return -ENXIO; |
408 | } |
409 | |
410 | msic = devm_kzalloc(&pdev->dev, sizeof(*msic), GFP_KERNEL); |
411 | if (!msic) |
412 | return -ENOMEM; |
413 | |
414 | msic->vendor = MSIC_VENDOR(id0); |
415 | msic->version = MSIC_VERSION(id0); |
416 | msic->pdev = pdev; |
417 | |
418 | /* |
419 | * Map in the MSIC interrupt tree area in SRAM. This is exposed to |
420 | * the clients via intel_msic_irq_read(). |
421 | */ |
422 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
423 | if (!res) { |
424 | dev_err(&pdev->dev, "failed to get SRAM iomem resource\n"); |
425 | return -ENODEV; |
426 | } |
427 | |
428 | msic->irq_base = devm_ioremap_resource(&pdev->dev, res); |
429 | if (IS_ERR(msic->irq_base)) |
430 | return PTR_ERR(msic->irq_base); |
431 | |
432 | platform_set_drvdata(pdev, msic); |
433 | |
434 | ret = intel_msic_init_devices(msic); |
435 | if (ret) { |
436 | dev_err(&pdev->dev, "failed to initialize MSIC devices\n"); |
437 | return ret; |
438 | } |
439 | |
440 | dev_info(&pdev->dev, "Intel MSIC version %c%d (vendor %#x)\n", |
441 | MSIC_MAJOR(msic->version), MSIC_MINOR(msic->version), |
442 | msic->vendor); |
443 | |
444 | return 0; |
445 | } |
446 | |
447 | static int intel_msic_remove(struct platform_device *pdev) |
448 | { |
449 | struct intel_msic *msic = platform_get_drvdata(pdev); |
450 | |
451 | intel_msic_remove_devices(msic); |
452 | platform_set_drvdata(pdev, NULL); |
453 | |
454 | return 0; |
455 | } |
456 | |
457 | static struct platform_driver intel_msic_driver = { |
458 | .probe = intel_msic_probe, |
459 | .remove = intel_msic_remove, |
460 | .driver = { |
461 | .name = "intel_msic", |
462 | .owner = THIS_MODULE, |
463 | }, |
464 | }; |
465 | |
466 | module_platform_driver(intel_msic_driver); |
467 | |
468 | MODULE_DESCRIPTION("Driver for Intel MSIC"); |
469 | MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>"); |
470 | MODULE_LICENSE("GPL"); |
471 |
Branches:
ben-wpan
ben-wpan-stefan
javiroman/ks7010
jz-2.6.34
jz-2.6.34-rc5
jz-2.6.34-rc6
jz-2.6.34-rc7
jz-2.6.35
jz-2.6.36
jz-2.6.37
jz-2.6.38
jz-2.6.39
jz-3.0
jz-3.1
jz-3.11
jz-3.12
jz-3.13
jz-3.15
jz-3.16
jz-3.18-dt
jz-3.2
jz-3.3
jz-3.4
jz-3.5
jz-3.6
jz-3.6-rc2-pwm
jz-3.9
jz-3.9-clk
jz-3.9-rc8
jz47xx
jz47xx-2.6.38
master
Tags:
od-2011-09-04
od-2011-09-18
v2.6.34-rc5
v2.6.34-rc6
v2.6.34-rc7
v3.9