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1 | /* |
2 | * This file is provided under a dual BSD/GPLv2 license. When using or |
3 | * redistributing this file, you may do so under either license. |
4 | * |
5 | * GPL LICENSE SUMMARY |
6 | * |
7 | * Copyright(c) 2012 Intel Corporation. All rights reserved. |
8 | * |
9 | * This program is free software; you can redistribute it and/or modify |
10 | * it under the terms of version 2 of the GNU General Public License as |
11 | * published by the Free Software Foundation. |
12 | * |
13 | * BSD LICENSE |
14 | * |
15 | * Copyright(c) 2012 Intel Corporation. All rights reserved. |
16 | * |
17 | * Redistribution and use in source and binary forms, with or without |
18 | * modification, are permitted provided that the following conditions |
19 | * are met: |
20 | * |
21 | * * Redistributions of source code must retain the above copyright |
22 | * notice, this list of conditions and the following disclaimer. |
23 | * * Redistributions in binary form must reproduce the above copy |
24 | * notice, this list of conditions and the following disclaimer in |
25 | * the documentation and/or other materials provided with the |
26 | * distribution. |
27 | * * Neither the name of Intel Corporation nor the names of its |
28 | * contributors may be used to endorse or promote products derived |
29 | * from this software without specific prior written permission. |
30 | * |
31 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
32 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
33 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR |
34 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT |
35 | * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, |
36 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT |
37 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
38 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
39 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
40 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
41 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
42 | * |
43 | * Intel PCIe NTB Linux driver |
44 | * |
45 | * Contact Information: |
46 | * Jon Mason <jon.mason@intel.com> |
47 | */ |
48 | |
49 | #define NTB_LINK_ENABLE 0x0000 |
50 | #define NTB_LINK_DISABLE 0x0002 |
51 | #define NTB_LINK_STATUS_ACTIVE 0x2000 |
52 | #define NTB_LINK_SPEED_MASK 0x000f |
53 | #define NTB_LINK_WIDTH_MASK 0x03f0 |
54 | |
55 | #define SNB_MSIX_CNT 4 |
56 | #define SNB_MAX_SPADS 16 |
57 | #define SNB_MAX_COMPAT_SPADS 8 |
58 | /* Reserve the uppermost bit for link interrupt */ |
59 | #define SNB_MAX_DB_BITS 15 |
60 | #define SNB_DB_BITS_PER_VEC 5 |
61 | |
62 | #define SNB_DB_HW_LINK 0x8000 |
63 | |
64 | #define SNB_PCICMD_OFFSET 0x0504 |
65 | #define SNB_DEVCTRL_OFFSET 0x0598 |
66 | #define SNB_LINK_STATUS_OFFSET 0x01A2 |
67 | |
68 | #define SNB_PBAR2LMT_OFFSET 0x0000 |
69 | #define SNB_PBAR4LMT_OFFSET 0x0008 |
70 | #define SNB_PBAR2XLAT_OFFSET 0x0010 |
71 | #define SNB_PBAR4XLAT_OFFSET 0x0018 |
72 | #define SNB_SBAR2LMT_OFFSET 0x0020 |
73 | #define SNB_SBAR4LMT_OFFSET 0x0028 |
74 | #define SNB_SBAR2XLAT_OFFSET 0x0030 |
75 | #define SNB_SBAR4XLAT_OFFSET 0x0038 |
76 | #define SNB_SBAR0BASE_OFFSET 0x0040 |
77 | #define SNB_SBAR2BASE_OFFSET 0x0048 |
78 | #define SNB_SBAR4BASE_OFFSET 0x0050 |
79 | #define SNB_NTBCNTL_OFFSET 0x0058 |
80 | #define SNB_SBDF_OFFSET 0x005C |
81 | #define SNB_PDOORBELL_OFFSET 0x0060 |
82 | #define SNB_PDBMSK_OFFSET 0x0062 |
83 | #define SNB_SDOORBELL_OFFSET 0x0064 |
84 | #define SNB_SDBMSK_OFFSET 0x0066 |
85 | #define SNB_USMEMMISS 0x0070 |
86 | #define SNB_SPAD_OFFSET 0x0080 |
87 | #define SNB_SPADSEMA4_OFFSET 0x00c0 |
88 | #define SNB_WCCNTRL_OFFSET 0x00e0 |
89 | #define SNB_B2B_SPAD_OFFSET 0x0100 |
90 | #define SNB_B2B_DOORBELL_OFFSET 0x0140 |
91 | #define SNB_B2B_XLAT_OFFSET 0x0144 |
92 | |
93 | #define BWD_MSIX_CNT 34 |
94 | #define BWD_MAX_SPADS 16 |
95 | #define BWD_MAX_COMPAT_SPADS 16 |
96 | #define BWD_MAX_DB_BITS 34 |
97 | #define BWD_DB_BITS_PER_VEC 1 |
98 | |
99 | #define BWD_PCICMD_OFFSET 0xb004 |
100 | #define BWD_MBAR23_OFFSET 0xb018 |
101 | #define BWD_MBAR45_OFFSET 0xb020 |
102 | #define BWD_DEVCTRL_OFFSET 0xb048 |
103 | #define BWD_LINK_STATUS_OFFSET 0xb052 |
104 | |
105 | #define BWD_SBAR2XLAT_OFFSET 0x0008 |
106 | #define BWD_SBAR4XLAT_OFFSET 0x0010 |
107 | #define BWD_PDOORBELL_OFFSET 0x0020 |
108 | #define BWD_PDBMSK_OFFSET 0x0028 |
109 | #define BWD_NTBCNTL_OFFSET 0x0060 |
110 | #define BWD_EBDF_OFFSET 0x0064 |
111 | #define BWD_SPAD_OFFSET 0x0080 |
112 | #define BWD_SPADSEMA_OFFSET 0x00c0 |
113 | #define BWD_STKYSPAD_OFFSET 0x00c4 |
114 | #define BWD_PBAR2XLAT_OFFSET 0x8008 |
115 | #define BWD_PBAR4XLAT_OFFSET 0x8010 |
116 | #define BWD_B2B_DOORBELL_OFFSET 0x8020 |
117 | #define BWD_B2B_SPAD_OFFSET 0x8080 |
118 | #define BWD_B2B_SPADSEMA_OFFSET 0x80c0 |
119 | #define BWD_B2B_STKYSPAD_OFFSET 0x80c4 |
120 | |
121 | #define NTB_CNTL_BAR23_SNOOP (1 << 2) |
122 | #define NTB_CNTL_BAR45_SNOOP (1 << 6) |
123 | #define BWD_CNTL_LINK_DOWN (1 << 16) |
124 | |
125 | #define NTB_PPD_OFFSET 0x00D4 |
126 | #define SNB_PPD_CONN_TYPE 0x0003 |
127 | #define SNB_PPD_DEV_TYPE 0x0010 |
128 | #define BWD_PPD_INIT_LINK 0x0008 |
129 | #define BWD_PPD_CONN_TYPE 0x0300 |
130 | #define BWD_PPD_DEV_TYPE 0x1000 |
131 | |
132 | #define BWD_PBAR2XLAT_USD_ADDR 0x0000004000000000 |
133 | #define BWD_PBAR4XLAT_USD_ADDR 0x0000008000000000 |
134 | #define BWD_MBAR23_USD_ADDR 0x000000410000000C |
135 | #define BWD_MBAR45_USD_ADDR 0x000000810000000C |
136 | #define BWD_PBAR2XLAT_DSD_ADDR 0x0000004100000000 |
137 | #define BWD_PBAR4XLAT_DSD_ADDR 0x0000008100000000 |
138 | #define BWD_MBAR23_DSD_ADDR 0x000000400000000C |
139 | #define BWD_MBAR45_DSD_ADDR 0x000000800000000C |
140 |
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Tags:
od-2011-09-04
od-2011-09-18
v2.6.34-rc5
v2.6.34-rc6
v2.6.34-rc7
v3.9